KR100376171B1 - Picture-in-guide generator - Google Patents

Abstract

The picture-in guide generator 21 according to the present invention includes an output suitable for driving the display monitor 62 and an input suitable for receiving a television signal. The display generator 34 supplies a drive signal to the output terminal synchronously with the display monitor 62. EPG information is extracted from the television signal and stored in the memory 26. The number of pixels in the television signal is reduced. The reduced pixel number television signal is stored in the memory 26. The EPG data and the television signal are fed from the display generator 34 to the output in a continuous data stream arranged to produce a picture in guide display 10 on the monitor 62. The picture in guide generator 21 is preferably implemented on a single integrated circuit chip.

Description

Picture-in-Guide Generator {PICTURE-IN-GUIDE GENERATOR}

US Patent Application No. 08 / 475,395 (filed June 7, 1995, International Publication No. WO96 / 07270); United States Patent Application No. 60 / 053,330 filed July 21, 1997; United States Patent Application No. 60 / 061,119 filed October 6, 1997; And US Patent Application No. 60 / 055,237 (filed August 12, 1997) are incorporated herein by reference and form part of this specification. Also incorporated herein by reference is "The CTC140 Picture in Picture System (CPIP) Technical Training Manual," available from "Thomson Consumer Electronics, Inc., Indianapolis, Indiana, USA, which forms part of this specification.

The Electronic Program Guide (EPG) allows television viewers to update television scheduler information in the form of on-screen graphical displays. The EPG may provide scheduler information for current and future broadcast programs as well as summary information of television program contents corresponding to a specific program.

One conventional EPG format is a picture in guide (PIG) display. The PIG display includes a real time video image of a tuned television program displayed in a small window inserted into a large graphical guide. PIG displays offer viewers many options. The viewer can continue to watch the television program he is currently watching while browsing the entire television scheduler information in the guide before entering the guide. In other cases, the program displayed in the PIG window may change corresponding to the selected channel in the guide as the viewer moves the cursor along the list of programs in the guide. Viewers can also watch the program continuously through the embedded PIG window, pulling the PIG display up for more information about the program that they are currently watching, such as start / end times or program synopsis. have.

PIG EPG displays typically include a microprocessor, a vertical blanking interval (VBI) decoder / slicer, an on-screen display generator, a digital-to-analog converter (DAC), and a synchronization ( synch) an EPG comprising one single chip implementing circuitry and memory, and a separate chip comprising a Picture-In-Picture (PIP) generator, a DAC, a synchronization circuit, and a microprocessor interface circuit. Produced using a generator.

The PIP generator uses two video signals to generate a large background picture and an inset small picture. Small screens are created by decimating a subordinate video signal, for example by writing one pixel out of three pixels present on one line selected from three lines into the video memory. . Composite displays with large background screens and small screens inserted usually have a high-speed switch that scans a large screen and then scans a small picture image from video memory when the scanner reaches the PIP window area on the display monitor screen. Is generated using The high speed switch thus operates at the scan line frequency of the display monitor.

However, it is not necessary to provide two real-time images for the PIG display, since the main display contains textual and graphical information such as program guides, moving video images rather than real time. PIP's high speed switches are relatively expensive. In addition, the use of separate EPG generator chips and PIP generator chips increases the number of components, making it difficult to integrate with consumer electronics such as televisions, VCRs, satellite receivers, and the like.

Therefore, it is desirable to integrate the necessary components to provide a PIG display on one chip.

The present invention relates to a PIG generator for producing a picture-in-guide (PIG) display on a television screen or computer monitor.

1 illustrates a program guide display in Picture in Guide (PIG) format.

2 is a schematic diagram of a PIG generator in accordance with an embodiment of the present invention.

3 is a schematic diagram of a data structure of a RAM in accordance with an embodiment of the present invention.

4 is a schematic diagram illustrating the YUV component of a standard color bar video signal.

5 is a schematic diagram of analog-to-digital conversion (ADC) and clamping circuitry in accordance with one embodiment of the present invention.

The picture in guide generator has an output suitable for driving a display monitor and an input coupled to receive a television signal. The display generator supplies a drive signal to the output in synchronization with the display monitor. EPG information is extracted from the television signal and stored in memory. The number of pixels in the television signal is reduced. The reduced pixel count television signal is stored in memory. EPG data and television signals are retrieved from memory and stored in the display generator. The EPG data and the television signal are fed from the display generator to the output in a continuous data stream arranged to produce a picture-in-guide display on the monitor. The picture-in guide generator is preferably implemented on a single integrated circuit chip.

In accordance with the present invention, a Picture In Guide (PIG) generator is for generating a PIG display on a television screen or computer monitor. In general, there are two types of displays that can be used in a television system using a PIG generator. The first form is a full screen video display containing a live image of a broadcast television program, and the second form is a PIG display comprising a background graphic and a real time video image in a small window inserted therein. to be.

1 illustrates a PIG display 10 of an electronic program guide (EPG) that includes a graphics area 12 and a picture window 14. The picture window 14, referred to below as the PIG window, comprises a video image of a television program displayed on a full screen video display, but in general, both width and height are reduced by three factors, i.e., the screen. It has a reduced size that is 1/9 the size of. Another possible screen displayed in the PIG system is a full screen graphical display.

The graphics area 12 of the PIG display 10 occupies most of the screen. Graphics area 12 generally includes text, icons, and background graphics composed of various colors. Graphics can highlight text or portions of the screen. In an EPG system, a viewer can navigate through the various guides generally without changing the television program displayed in the PIG window 14. In some EPG systems, when the viewer places the cursor on a different channel designation 18 or program title 20 in the graphics area, the system automatically tunes the tuner 50 associated with the selected channel and PIG. The window 14 displays the program broadcast of that channel.

According to a preferred embodiment of the present invention, the components necessary to produce the PIG display 10 are provided on a single chip that will be located in a television, VCR, stand-alone unit, satellite receiver, or the like. By providing all the components on a single chip, it is possible to reduce the total gate count, reduce the chip's bus interface size as well as reduce the overall package size.

2 is a schematic diagram of components provided on a single chip 21 in accordance with a preferred embodiment of the present invention. These components include microprocessor 22, memory controller or direct memory access (DMA; 24), RAM (26), synchronization regenerating circuitry (28), analog-to-digital conversion (ADC), and clamp circuits. 30, PIG window generator 32, display generator 34, and digital-to-analog conversion (DAC) circuit 36. Among these components are microprocessors 22 connected directly to memory access 24, VBI decoders / slicers 37 receiving signals from outside and connected to microprocessors 22, ADCs / clamps receiving analog signals from outside, and The PIG window generator 32 coupled with the ADC / clamp 30 constitutes a display controller 100. In this case, it will be apparent to those skilled in the art that the display controller 100 may include only some of the components shown in FIG. 2 or may include more components.

Microprocessor 22 receives raw text data, such as EPG data, from a data source and stores this raw text data in RAM 26. For example, the EPG data may be embedded in the VBI of the television signal received by the television tuner 50 and extracted by the VBI decoder / slicer 37. Preferably, the RAM 26 has a storage capacity of 4 Mbit or more, a data RAM 31 for storing text data, a video RAM (VRAM) 33 for storing video data, as shown in FIG. A free space used as a working space 35 located between the data RAM 31 and the VRAM 33. The microprocessor 22 may organize the data stored in the RAM 26 and assign addresses to both text data and video data. However, the microprocessor 22 operates relatively slow compared to video processing hardware, such as the PIG window generator 32 and the display generator 34. Therefore, the microprocessor 22 generally processes only addressing data and text data, not video data. The microprocessor 22 communicates bidirectionally with the DMA 24. The microprocessor 22 communicates with the DMA 24 to access the RAM 26 via the data bus and the address bus.

It is desirable to have only one RAM. RAM 26 is accessed by three different components: microprocessor 22, PIG window generator 32, and display generator 34. This creates a large access load on the RAM 26 because all three of these components can compete to access the RAM 26 simultaneously. However, only one sample of this many bits can be accessed per access cycle, for example 8 bits in the case of 516K x 8-bit RAM. The multiplexing device needs to perform arbitration between these components. Thus, each of the microprocessor 22, PIG window generator 32, and display generator 34 accesses RAM via DMA 24. DMA 24 is a multiplexing and arbitration circuit that facilitates sharing of RAM 26 by alternately switching access between these three components. DMA 24 includes a buffer memory for temporarily storing data input from out-of-turn components between access cycles. DMA 24 stores text data and video data at the correct address in RAM 26 and then retrieves the appropriate data from the selected address in RAM 26 if necessary.

As mentioned above, RAM 26 preferably has a storage capacity of 4 Mbits or more and is subject to a fast access load. One way to balance high-speed access loads and transfer data at high speed is to choose 256K x 16-bit RAM over 512K x 8-bit RAM, so that DMA 24 has more information, 16 bits instead of 8 bits per access cycle. Is to allow sampling. The system receives a video signal from tuner 50. The horizontal and vertical (H- and V-) sync signals are separated from the video signal and routed to the sync circuit 28. The synchronization circuit 28 includes a pixel clock 38. Pixel clock 28 defines the x and y coordinates of each pixel displayed on the screen. The y coordinate matches the number of scan lines on the screen, and the x coordinate matches the number of pixels on each scan line.

The video region of video input from tuner 50 is converted into a YUV analog video signal by a television's chrominance processor 52. This is an intermediate signal conversion commonly used between input video and RGB signals displayed on a cathode ray tube (CRT) 62 in a television system.

4A, 4B, and 4C illustrate the YUV components 54, 56, 58 of a standard color bar video signal. Component 54 is a luminance (Y) signal with horizontal sync pulse 55. Component 56 is a chrom-signal (-V). Component 58 is the back porch region of the chroma-signal (-U) for video clamping. As illustrated in more detail in FIG. 5, each component of the signal is converted into digital form by the ADC / clamp circuit 30. The clamping area of ADC / clamp circuit 30 during signal switching reduces signal distortion due to low frequency noise and DC bounce, for example.

PIG window generator 32 receives a digital YUV video signal corresponding to a video image of the full screen. The PIG window generator 32 reduces the size of the entire picture by transferring the video data to the DMA 24 and decimating the video data before storing it in the VRAM 33. To decimate the video data, the PIG window generator 32 cooperates with the synchronization circuit 28 to select, for example, one scan line out of three scan lines and one pixel out of three pixels at a ratio of 1: 3. The data is then transferred to the DMA 24 and stored in the VRAM 33. To create PIG windows of different sizes, other decimation ratios such as 1: 4 may be used.

The exact address for storing video data from the PIG window generator 32 in the VRAM 33 is determined by the address mapping circuit 40 which is preferably located in the DAM 24. The address mapping circuit 40 uses the synchronization signals from the synchronization circuit 28 and the pixel clock 38 to store video data corresponding to each pixel on the CRT at an appropriate address location in the VRAM 33. Is accessed for display. This process is commonly referred to as "bit mapping."

Display generator 34 includes a graphics generator that formats the text, icons, colors, and highlighting fonts to be displayed, and the background graphics of graphics area 12 of PIG display 10. Graphic data is routed to an address mapping circuit 40 which, in cooperation with the DMA 24, stores the video data at an address location in the VRAM 33 corresponding to the pixel coordinates on the screen.

Hereinafter, the generation of the PIG display 10 according to the preferred embodiment of the present invention will be described.

The microprocessor 22 accesses the appropriate text data to be displayed from the raw text data in the RAM 31 in response to the viewer command device 70, such as an IR remote for a given PIG EPG display. The microprocessor 22 constructs the text data for display and routes the text data to the DMA 24 using the appropriate address for displaying the text and stores it in the VRAM 33.

All video data for generating the PIG display 10 including the text and graphics of the graphics area 12 and the video image of the PIG window 14 are stored in the VRAM 33 as described above. The display generator 34 cooperates with the address mapping circuit 40 and the synchronization circuit 28 to pre-configure the contents of the VRAM to generate a screen to be displayed on the screen of the CRT 62. Data for each pixel to be displayed on the screen is stored in the VRAM 33 using addresses corresponding to the x and y coordinates on the screen for the same pixel. The display generator 34 uses the sync signal from the sync circuit 28 and accesses the appropriate data for each pixel from the VRAM 33 in the order determined by the pixel clock 38. This sync signal is generated by the sync circuit 28 from the H-SYNCH and V-SYNCH signals of the input video.

Although it is preferable to store the entire screen field or frame in the VRAM 33 at once in the bit mapping format, it is possible to store a portion of the screen smaller than the entire screen at once, and in fact, the display processing can be performed with a group of pixels smaller than the entire screen. .

In order to suitably produce a PIG display similar to that illustrated in FIG. 1 on the screen of the CRT 62, the display generator 34 converts the digital YUV signal for each pixel and converts the DAC circuit 36 into a continuous data stream. ) The DAC circuit converts the data into an analog YUV video signal. These analog YUV video signals are converted into analog RGB signals by the RGB conversion circuit 60 in the television before being displayed on the screen of the CRT 62.

In another embodiment of the present invention, the RAM 26 is located "off the chip" and is connected to the DAM 24 by a data bus.

Tuner 50, chrominance processor 52, RGB conversion circuit 60, CRT 62, and viewer command 70 are part of the television apparatus. That is, these components, as in the prior art, perform a dual function of helping to display a television signal in full screen format while simultaneously displaying a PIG format. Other components are unique only in the PIG format.

The PIG circuit design implemented on the single chip 21 in accordance with the present invention makes the packaging more economical by reducing the size of the circuit and reducing the number of gates. Unlike conventional television systems that require two gate arrays for each of the components on a separate PIP chip and an EPG chip to produce a PIG display, in the present invention, the microprocessor 22, the synchronization circuit 28, Requiring a single gate array for each of the DAC circuit 36 and the DMA 24 reduces the total number of gates. It should be noted that under the control of the pixel clock 38 and the synchronization circuit 28, the display generator 34 transmits both image information and EPG information to the CRT 62 in the form of a continuous data stream. Thus, a video (ie moving picture image) image is generated on the EPG display without using a high speed switch.

The foregoing embodiments of the present invention belong to preferred embodiments for illustrating the spirit of the present invention, and the scope of the present invention is not limited to these embodiments. Those skilled in the art can devise many different arrangements without departing from the spirit and scope of the invention. For example, separate RAMs can be used to store EPG data and reduced pixel count television signals. The invention can also be used in digital television transmission systems that do not require an ADC, a DAC, and a VBI slicer.

Claims (10)

Output stage suitable for driving display monitor, A display generator for supplying a drive signal to the output terminal in synchronization with the display monitor, An input suitable for receiving a television signal, Means for extracting EPG information from the television signal connected to the input terminal; Means for storing the EPG information in a memory, Means for reducing the number of pixels of the television signal, Means for storing the reduced number of television signals in the memory; Means for retrieving the EPG information and the television signal from the memory, Means for storing the retrieved EPG information and television signal in the display generator, and Means for supplying the EPG information and the television signal from the display generator to the output in the form of a continuous data stream arranged to produce a PIG display on the monitor Including, The means for storing the reduced pixel number television signal in the memory is configured to store the reduced pixel number television signal in the memory as a group of pixels representing a portion of a full screen field. Picture in guide generator. In claim 1, The display generator is a picture-in guide generator implemented by an integrated circuit chip. In claim 2, And a picture in guide generator, wherein said extraction means is a VBI decoder. In claim 3, A picture in guide generator wherein the memory comprises one or more RAMs. A display controller configured to receive a television signal, reduce the number of pixels of the television signal, and extract electronic program guide information from the television signal; A memory for storing the extracted electronic program guide information and the reduced pixel number television signal, and A display generator for driving a display monitor and retrieving the electronic program guide information and the television signal Including, The electronic program guide information and the television signal are then stored and supplied to the display monitor in the form of a continuous data stream arranged to produce a picture in guide display on the display monitor. Picture in guide generator. In claim 5, And further comprising address mapping circuitry configured to store the reduced number of television signals as video data, wherein the video data corresponds to one pixel of a full screen field, each pixel having an address representing a portion of the memory. Picture-in-guide generator that is mapped. In claim 5, And the memory is a group of pixels representing a portion of an entire screen field and is configured to store the reduced number of television signals in the memory at one time. Receiving a television signal, Extracting electronic program guide information from the television signal; Storing the electronic program guide information in a memory; Reducing the number of pixels of the television signal, Storing the reduced number of television signals in the memory; Retrieving the electronic program guide information and the television signal from the memory; Storing the retrieved electronic program guide information and the television signal in a display generator, and Supplying said electronic program guide information and said television signal of said display generator in the form of a continuous data stream arranged to produce a picture in guide display on said display monitor at an output suitable for driving a display monitor; Including, Storing the reduced pixel number television signal in the memory includes storing each pixel of a full screen field and mapping each pixel to an address representing a particular portion within the memory. How to display picture in guide. delete In claim 8, Storing the reduced number of television signals in a memory comprises grouping the reduced number of television signals into a group of pixels representing a portion of a full screen field, and each of the groups of pixels into a memory at a time Picture in guide display method comprising the step of storing.