JP2002503898A - Guide image generator - Google Patents

Abstract

(57) [Summary] The in-guide image generator (21) has an output unit for driving a display monitor (62) and an input unit for receiving a television signal. The display generator (34) sends the drive signal to the output in synchronization with the display monitor (62). EPG (Electronic Program Guide) information is extracted from the television signal and stored in the memory (26). The pixel size of the television signal is reduced. The reduced pixel size television signal is stored in memory (26). EPG data and television signals are retrieved from memory (26) and stored in display generator (34). The EPG data and the television signal are sent from the display generator (34) to the output as a continuous data stream ordered to generate the in-guide image display (10) on the monitor (62). Preferably, the in-guide image generator (21) is implemented on a single integrated circuit chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a picture-in-guide generator such as a television receiver.

[0002] This application is related to US application Ser. No. 60/072, filed Jan. 26, 1998.
Claim 428 priority. And all of the disclosure contents are incorporated herein by reference.

[0003]

[Prior art]

The disclosures of the following patent applications are incorporated herein by reference. No. 08 / 475,395, filed Jun. 7, 1995,
International Patent Publication No. WO 96/07270, U.S. Patent Application No. 60 / 053,330, filed July 21, 1997, U.S. Patent Application No. 60 / 061,119, filed October 6, 1997, No. 60 / 055,237, filed Aug. 12, 1997. Also, Thomson Consumer Electroni
`` The CTC140 Picture in Picture, available from cs. Inc., Indianapolis, IN
The publication titled “System (CPIP) Technical Training Manual” is also incorporated as reference material.

[0004] Electronic Program Guides (EPGs) provide television viewers with updatable television schedule information in the form of on-screen graphic displays. The EPG can provide schedule information for current and future broadcast programs as well as an overview of television program content for certain programs.

[0005] One particularly useful format for the EPG is an in-guide image (PIG = Pic
ture-In-Guide) display. The PIG display includes a real-time video image of a tuned television program displayed with a small window insertion in a larger graphic guide. The PIG display gives the viewer many options (optional). Viewers can continue to watch the television program they were watching before entering the guide while browsing via the television scheduling information in the guide. Alternatively, the program displayed in the PIG window can be changed to match the selected channel in the guide as the viewer browses through the program listings in the guide. The viewer can raise the PIG display and continue watching the program in the PIG window while discovering more information about the currently watching program, for example, start / stop times or program synopses.

[0006] Typically, the PIG EPG representation is generated using an EPG generator. The EPG generator includes a microprocessor, a vertical blanking interval (VBI) decoder / slicer, an on-screen display generator, and a digital / analog converter (
DAC), a synchronization (Synch) circuit, a memory on one chip, and an image in a picture (PIP).
= Picture-In-Picture) generator, a digital-to-analog converter (DAC), a synchronization circuit, and a separate chip containing an microprocessor interface circuit.

[0007] The PIP generator uses two video signals to create a large background image and a small inset image. Small images are generated by taking one-tenth of the lower video signal, for example, by writing one pixel for every three pixels on one line to the video memory every three lines. A composite display with a large image in the background and a small image as an inset image usually scans the large image and then resizes the small image from video memory when the scanner reaches the PIP window area on the screen of the display monitor. Generated by using a fast switch to scan the image. Therefore, the high speed switch must operate at the display monitor scan line frequency.

However, in the case of a PIG display, it is not necessary to provide two real-time video images since the main display contains textual information, graphic information (eg, a program guide) and does not include real-time moving video images. Absent. PIP high speed switches are relatively expensive. Also, using separate chips for the EPG generator and the PIP generator requires more components, and consumer electronic components such as televisions, VCRs (video cassette recorders), satellites It is more difficult to incorporate into a receiver or the like.

Therefore, it is desirable to integrate and arrange the components necessary for obtaining the PIG display on one chip.

SUMMARY OF THE INVENTION An in-guide image generator has an output adapted to drive a display monitor and an input adapted to receive television signals. The display generator supplies a drive signal to the output in synchronization with the display monitor. EPG information is extracted from the television signal and stored in a memory. The pixel size of the television signal is reduced. The reduced pixel size television signal is stored in memory. EPG data and television signals are retrieved from memory and stored in a display generator. EPG data and television signals are provided to the output from the display generator as a continuous data stream ordered to generate an in-guide image display on a monitor. Preferably, the in-guide image generator is implemented on a single integrated circuit chip.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

According to the invention, an image-in-graphics (PIG = Picture-In-Graphics) generator for generating an image-in-guide (PIG = Picture-In-Guide) display on a television screen or computer monitor. Is provided. Generally, PIG
Two types of displays can be utilized in a television system using a generator. The first type is a full-screen video display that includes real-time images of television broadcast programs. The second type (PIG display) includes a background screen and a real-time video image in a small inset window.

FIG. 1 shows an electronic program guide (EPG) PIG (image in guide) display 10 that includes a graphics portion 12 and an image window 14. The image window 14 (referred to as the PIG window) contains a video image of a television program displayed in a full-screen video display, but generally at reduced size,
It is reduced by a third in width and height, ie, 1/9 of the screen size.
Another potential screen for display in a PIG system is a full-screen graphics display.

The graphics portion 12 of the PIG display 10 occupies most of the screen. The graphics portion generally includes several different colored text, icons and background graphics. The graphics may include text or section highlighting on the screen. In the EPG system,
Viewers can generally search through different guides without changing the television program displayed in the PIG window 14. In some EPG systems, when the viewer positions the cursor 16 on a program title 20 in a different channel designator 18 or graphics portion, the system automatically adjusts the associated tuner 50 to the selected channel. , The program broadcast on the channel is displayed in the PIG window 14.

According to a preferred embodiment of the present invention, the components required to generate PIG display 10 are on a single chip that is to be incorporated into a television, VCR, stand-alone unit, satellite receiver, or the like. Is provided. By providing all components on a single chip, the overall package size and the overall gate count and bus interface size of the chip can be reduced.

FIG. 2 is a schematic diagram of components of a preferred embodiment of the present invention provided on a single chip 21. The components include a microprocessor 22, a memory controller or direct memory access (DMA) device 24, a random access memory (RAM) 26, a synchronous playback (sink) circuit 28, and an analog-to-digital converter (ADC). There are a clamping circuit 30, a PIG window generator 32, a display generator 34, and a digital / analog conversion (DAC) circuit 36.

The microprocessor 22 includes raw text data from a data source (eg,
EPG data) and stores the raw text data in the RAM 26. For example, the EPG data may be embedded in a vertical blanking interval (VBI) of a television signal received by the television tuner 50 and extracted by the VBI decoder / slicer 37. Preferably, the RAM 26 has a storage capacity of 4 Mbit or more. Then, a data RAM 31 for storing text data, a video RAM (VRAM) 31 for storing video data, and a work space 35 between the data RAM 31 and the VRAM 33 as shown in FIG. And free space. Microprocessor 22 can organize the data storage in RAM 26 and assign addresses for both text and video data. However, microprocessor 22 is relatively slow as compared to video processing hardware, such as PIG window generator 32 and display generator 34. Thus, in general, microprocessor 22 processes only addressing data and text data, and does not process video data. The microprocessor performs bidirectional communication with the DMA 24. Microprocessor 22 communicates with DMA 24 to access RAM 26 via both a data bus and an address bus.

Preferably, there is only one RAM. This RAM 26 is accessed by three different components: a microprocessor 22, a PIG window generator 32, and a display generator 34. This places a high access load on the RAM, since all three components can access the RAM at the same time.
However, only one sample of a significant number of bits can be accessed per access cycle. For example, in the case of a 516K × 8-bit RAM, it is 8 bits. Multiplexers are required to determine arbitration between components.
Thus, microprocessor 22, PIG window generator 32 and display generator 34 each access RAM via DMA 24. DMA 24 serves as a multiplexer and arbitration circuit that facilitates sharing of RAM 26 by sequentially switching access between the three components. DMA 24 includes a buffer memory that temporarily stores data input from out-of-turn components during access cycles. DMA 24 stores the text and video data at the correct addresses in RAM 26 and retrieves the appropriate data from the selected address in RAM as needed.

As mentioned above, RAM 26 preferably has a storage capacity of 4 Mbit or more and is subject to high access loading. One way to adapt to high access loads and to transfer data more quickly is to choose 256K × 16 bit RAM rather than 512K × 8 bit RAM, and DMA 24 provides more information,
The purpose is to be able to sample 16 bits instead of 8 bits per access cycle. This system accepts a video signal from tuner 50. The horizontal and vertical (h and v) synchronization signals are split from the video signal and sent to the synchronization circuit 28. The synchronization circuit includes a pixel clock 28. Pixel clock 28 determines the x and y coordinates of each pixel that is to be displayed on the screen. The y-coordinate corresponds to the scan line number of the screen, and the x-coordinate corresponds to the pixel number in each scan line.

The video portion of the input video from tuner 50 is converted to a YUV analog video signal by chrominance processor 52 in the television. this is,
An intermediate signal conversion commonly used in television systems between input video and RGB signals displayed on a cathode ray tube (CRT) 62.

FIGS. 4A, 4B, and 4C show the YUV components 54, 56, and 58 of the standard color bar video signal, respectively. The component 54 is a luminance (Y) signal having a horizontal synchronization pulse 55. Component 56 is the chrome signal (V). Component 58 is the back porch area of the chroma signal (U) for video clamping. Each component of this signal is converted to digital form by an ADC / clamp circuit 30, shown in more detail in FIG. The clamping portion of the ADC / clamping circuit 30 reduces distortion in the signal, for example, due to low frequency noise and DC bounce when switching signals.

The PIG window generator 32 receives a digital YUV video signal corresponding to a full screen video image. PIG window generator 32 reduces the overall image size by reducing the video data by a factor of ten before transmitting to DMA 24 for storage in VRAM. In order to reduce the video data by a factor of ten, the PIG window generator 32 cooperates with the synchronization circuit 28, for example: one pixel from every three pixels, one scan from every three lines. A line is selected, ie, a ratio of 1: 3, and this data is sent to DMA 24 for storage in VRAM 33. Other 1/10 ratios are possible to generate PIG windows of different sizes. For example, it may be 1: 4.

The correct address for storing video data from the PIG window generator 32 in the VRAM 33 is determined by the address mapping circuit 40 which is preferably incorporated in the DMA 24. By using the sync signal from the synchronization circuit 28 and the pixel clock 38, the address mapping circuit 40 corresponds to each pixel on the CRT at the appropriate address site in VRAM for later access to the display. Store video data. This process is commonly referred to as "bit mapping."

The display generator 34 includes a graphics generator that formats fonts, icons, colors and highlights for the text to be displayed and background graphics for the graphics portion 12 of the PIG display 10. I do.
The graphics data is sent to an address mapping circuit 40 which, in cooperation with DMA 24, stores the video data at an address site in VRAM 33 corresponding to the pixel coordinates on the screen. Let it.

The generation of a PIG display 10 (FIG. 1) according to a preferred embodiment is described below. In response to a viewer command device 70 for PIG / EPG display, for example, an IR remote (infrared type remote controller), the microprocessor 22
Accesses the appropriate text data for display from the raw text data in the data RAM 31. Microprocessor 22 constructs the text data for display and routes the text data with the appropriate address to DMA 24 for display of the text for storage in VRAM 33.

All video data for generating the PIG display 10, including text in the graphics portion 12, graphics and video images in the PIG window 14, are stored in the VRAM 33 as described above. The display generator 34, in cooperation with the address mapping circuit 40 and the synchronizing circuit 28, accesses the pre-organized contents of the VRAM and creates an image for display on the screen of the CRT 62. The data of each pixel to be displayed on the screen is stored in the VRAM 33 with an address corresponding to the x coordinate and the y coordinate of the pixel on the screen. The display generator 34 uses the sync signal from the synchronization circuit 28 to
Appropriate data from VRAM 33 for each pixel is accessed sequentially, such as determined by clock 38. This sync signal corresponds to h in the input video.
Generated by the synchronization circuit 28 from the sync signal and the v-sync signal.

Although it is preferred to store the entire screen field or screen frame in VRAM 33 at a time in a bit-mapped manner, less than the entire screen, ie, only a portion of the screen, is stored at one time, The display processing may be effectively performed as a pixel group smaller than the whole.

The display generator 34 converts the digital YUV signal on a pixel-by-pixel basis and outputs it to the DAC circuit 36 as a continuous data stream in the proper order, on a screen of the CRT 62 in a guide similar to that shown in FIG. Generate an image display. The DAC circuit converts the data into an analog YUV video signal. These analog YUV video signals are converted into analog RGB signals by an RGB conversion circuit 60 in the television, and then displayed on the screen of the CRT 62.

In another embodiment of the present invention, RAM 30 is located “off chip” and is connected to DMA 24 by a data bus.

Tuner 50, chrominance processor 52, RGB converter 60, CR
T62 and the viewer command 70 are part of the television device. In other words, these components serve the dual function of displaying the television signal normally in full screen format and helping to display the in-guide image format.
Other components are specific to the in-guide image format.

The design of the PIG circuit according to the invention on a single chip 21 makes the package more economical by reducing the size and the number of gates. The present invention replaces the use of a micro gate instead of a two gate array for each of these components on a separate PIP chip, EPG chip, as used in known television systems to generate PIG displays. By requiring only one gate array for each of processor 22, synchronization circuit 28, DAC circuit 36 and DMA 24, the overall gate count is reduced. Note also that display generator 34 sends both image information and EPG information to CRT 62 as a continuous data stream under the control of pixel clock 38 and synchronization circuit 28. Thus, a video image (ie, a moving image) is created in an EPG display without a high-speed switch.

The above embodiments of the present invention are only for explaining the concept of the present invention, which is considered preferable, and the scope of the present invention is not limited to such embodiments. Various other arrangements can be devised by those skilled in the art without departing from the spirit and scope of the invention. For example, a separate RAM may be used to store EPG data and reduced size television signals. Further, the invention can be used in digital television transmission systems as well, in which case the ADC, DAC and VB
The I slicer may be omitted.

[Brief description of the drawings]

FIG. 1 shows a program guide display in an in-guide image (PIG) format.

FIG. 2 is a schematic diagram of a PIG generator according to one embodiment of the present invention.

FIG. 3 is a schematic diagram of a data organization in a RAM according to one embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating the YUV component of a standard color bar video signal.

FIG. 5 is a schematic diagram of an analog-to-digital conversion and clamping circuit according to one embodiment of the present invention.

[Procedure amendment]

[Submission date] July 26, 2000 (2000.7.26)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

──────────────────────────────────────────────────続 き Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE , KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZW (72) Inventor O'Connor Dan, Massachusetts, USA 01915 Beverly Hathaway Avenue 41 ( 72) Inventor Yuen Henry C. United States of America 91102-0438 Pasadena P.A. Box 438 F-term (reference) 5C025 AA25 CA06 CA09 CB10 DA05 5C063 AB07 CA23 DA03 DB02 EB33 EB38 EB40

Claims (4)

[Claims] 1. An image-in-guide (PIG) generator, comprising: an output configured to drive a display monitor; and a display generator for providing a drive signal to the output in synchronization with the display monitor. An input unit configured to accept a television signal; a means connected to the input unit for extracting EPG (Electronic Program Guide) information from the television signal; a means for storing EPG information in a memory; Means for reducing the pixel size of the television signal, means for storing the reduced pixel size television signal in the memory, means for retrieving EPG data and the television signal from the memory, and means for retrieving the retrieved EPG data and the television signal. Means for storage in a display generator; and a continuous data stream ordered to generate an in-guide image display on a monitor. Guide image generator, characterized in that it comprises a means for sending to the output unit EPG data and television signals from the display generator in beam. 2. The in-guide image generator according to claim 1, wherein the in-guide image generator is mounted on a single integrated circuit chip. 3. The in-guide image generator according to claim 2, wherein the extracting means is a VBI decoder. 4. The in-guide image generator of claim 3, wherein the memory includes one or more RAMs.