MXPA00007291A - Picture-in-guide generator - Google Patents

Abstract

A picture-in-guide generator (21) has an output adapted to drive a display monitor (62) and an input adapted to receive a television signal.A display generator (34) feeds drive signals to the output in synchronism with the display monitor (62). EPG information is extracted from the television signal and stored in memory (26). The pixel size of the television signal is reduced. The reduced pixel size television signal is stored in memory (26). The EPG data and the television signal are retrieved from memory (26) and stored in the display generator (34). The EPG data and the television signal are fed from the display generator (34) to the output in a continuous data stream ordered to produce a picture-in-guide display (10) on the monitor (62). Preferably, the picture-in-guide generator (21) is implemented on a single integrated circuit chip.

Description

GENERATOR OF IMAGES IN GUIA FIELD AND BACKGROUND OF THE INVENTION The descriptions of the following patent applications are fully incorporated herein by reference: Application No. 08 / 475,395 filed June 7, 1995; International Application O96 / 07270; Application No. 60 / 053,330 filed July 21, 1997, Application No. 60 / 061,119 filed October 6, 1997; and Application No. 60 / 055,237 filed August 12, 1997. Also incorporated as reference is the publication entitled "CTC140 Image-in-Picture (CPIP) Technical Training Manual" available from Thomson Consumer Electronics, Inc., I ndianápol is, IN. An electronic program guide (EPG) provides a viewer with information on television programs that can be updated in the form of on-screen graphic display. The EPG can provide information on the programming of television broadcasting programs, ongoing and future, as well REF .: 122110 as summaries of the content of television programs for a particular program. A particularly convenient format for an EPG is a guided image display (PIG). A PIG visualization includes a video image, in real time, of a tuned television program, presented in a small window inserted in a larger graphic guide. The PIG display provides many options to the viewer. The viewer can continue to watch the television program he was watching before entering the guide, while quickly reviewing the television programming information found in the guide. Alternatively, the program presented in the PIG window may change to correspond to a selected channel found in the guide, when the viewer moves the cursor through listings of programs found in the guide. The viewer can also stop the visual! PIG to discover more information about the program you are viewing, such as the start and end time, or a synopsis of the program, while continuing to observe the program that is in the inserted PIG window. Typically, an electronic guidance display of programs in PIG format is produced using an EPG generator, which includes a microprocessor, a vertical erase interval decoder (VBI), and an on-screen display generator. , a digital-to-analog converter (DAC), a set of synchronization circuits (sync), and a memory in a microcircuit of integrated circuits, and a separate integrated circuit microcircuit, including an image generator in image (PIP), a digital-to-analog converter, synchronization circuit sets, and microprocessor interface circuitry sets. The PIP generator uses two video signals to create a large background image and a small inserted image. The small image is generated by the decimation of a subordinate video signal, for example, by writing one out of every three image elements in one of every three lines, in a video memory. A composite display that has the large image in the background and the small image as an insert, is generated by scanning the large image normally and then using a high-speed switch to scan the small image of the video memory, when the scanner reaches the area of the PIP window on the display monitor screen. In this way, the high-speed switch must operate at the scanning line frequency of the display monitor. However, for a PIG display, it is not necessary to provide two video images in real time, since the main display comprises text and graphic information, for example, a program guide, and not a moving video image in time. real. The high-speed PIP switch is relatively expensive. Also, using separate integrated circuit microplates for the EPG generator and for the PIP generator requires more components and is more difficult to integrate consumer electronic components, such as such as televisions, videocases, satellite receivers, or similar. Therefore, it is desirable to consolidate the necessary components to provide a PIG visualization, in a microcircuit of integrated circuits.

BRIEF DESCRIPTION OF THE INVENTION A guide image generator has an output adapted to activate a display monitor, and an input adapted to receive a television signal. A display generator feeds excitation signals at the output, in synchronization with the display monitor. The EPG information is extracted from the television signal and stored in memory. The image element size of the television signal is reduced. The television signal with reduced image element size is stored in memory. The data of the EPG and the television signal are recovered from the memory and stored in the display generator. The EPG data and the television signal are fed from the display generator towards the output, in a continuous stream of data, ordered, to produce a display of images in a guide, on the monitor. Preferably, the imager in the guide is implemented in a single micr oplaque t of integrated circuits.

DESCRIPTION OF THE DRAWINGS The characteristics of the specific modalities of the best mode contemplated for carrying out the invention are illustrated in the drawings in which: Figure 1 illustrates a program guide display in a guide image format (PIG); Figure 2 is a schematic view of a PIG generator in accordance with one embodiment of the invention; Figure 3 is a schematic view of the organization of the data in Memory of Random Access (RAM) in accordance with one embodiment of the invention; Figure 4 is a schematic representation of the Y U V components of a standard chromatic strip video signal; Figure 5 is a schematic view of the analog-to-digital conversion and the level setting circuitry, in accordance with one embodiment of the invention.

DETAILED DESCRIPTION OF A SPECIFIC MODALITY In accordance with the invention, a graphics image generator (PIG) is provided to produce a PIG display on a television screen or on a computer monitor. There are, in general, two types of visualization available on a television system that uses a PIG generator. The first type is a video display in full screen, comprising a real-time image of a television broadcast program. The second type, a PIG visualization, includes background graphics and a video image in real time, in a small inserted window.

Figure 1 illustrates a PIG display 10 of an electronic program guide (EPG) containing a portion of graphics 12 and an image window 14. The image window 14, referred to hereinafter as a PIG window , it contains a video image of the television program shown in the video display in full screen, but in reduced size, generally reduced by a factor of three, both in width and height, that is, 1/9 of the size of the screen. Another possible screen for viewing in a PIG system is the display of graphics on a complete screen. The graphics portion 12 of the PIG display 10 occupies most of the screen. The graphics portion usually includes text, icons, and background graphics of many different colors. Graphics can include highlighting text or sections of the screen. In an EPG system, the viewer can generally navigate through different guides without changing the television program displayed in the PIG window 14. In some EPG systems, when the viewer puts a cursor 16 on a different channel designation 18 or program title 20 on the graphics portion, the system automatically tunes the associated tuner 50 to the associated channel and displays the program televised on that channel, in the PIG window 14. In accordance with a preferred embodiment of the invention, the components necessary to generate a PIG display 10 are provided in a single my op crel of integrated circuits, incorporated in the television, videoca set er as, independent units, satellite receivers or similar. By providing all the components in a single integrated circuit, the overall size of the package can be reduced, as can the global gate count and busbar interface size, from that point of view. integrated circuits . Figure 2 is a schematic view of the components of a preferred embodiment of the invention, provided in a single circuit of integrated circuits 21. they include a microprocessor 22, a memory controller or a direct memory access device (DMA) 24, a random access memory (RAM) 26, synchronization regeneration circuit sets (sync) 28, analog conversion to digital (ADC) and level 30 circuit assemblies, a PIG window generator 32, a wind generator 34, and circuit assemblies 36 for digital-to-analog conversion (DAC). The microprocessor 22 receives unprocessed text data, for example EPG data, from a data source and stores the raw text data in the RAM 26. For example, the EPG data can be inserted in the vertical blanking interval. (VBI) of the television signal received by the television tuner 50 and extracted by a decoder / section BVI 37. Preferably, the RAM 26 has a storage capacity of 4 Megabytes or greater, and includes a RAM 31 for data, to store text data and a video RAM (VRAM) 31 to store video data, as well as free space to use it as a workspace 35 between the data RAM 31 and VRAM 33, as shown in Figure 3. The microprocessor 22 organizes the data storage in the RAM 26 and can assign addresses for both the text data and the video data. However, the microprocessor 22 is relatively slow compared to the physical elements for video processing, for example, the PIG window generator 32 and the display generator 34. Accordingly, the microprocessor 22 generally processes only the addressing data and the text data, and not video data. The microprocessor is in two-way communication with the DMA 24. The microprocessor 22 communicates with the DMA 24 to access the RAM 26, both through the data bus and through the address bus. Preferably, there is only one RAM. Access to this RAM 26 is achieved by three different components: the microprocessor 22, the PIG window generator 32, and the display generator 34. This places a large access load in RAM since all three components can search access to RAM simultaneously. However, only a sample of many bits can have access per access cycle, for example 8 bits for a RAM of 516KX8 bits. A muliplexion device is necessary to resolve the arbitrage between the components. Accordingly, the microprocessor 22, the PIG window generator 32 and the visualization generator 34 each access the RAM through the DMA 24. The DMA 24 is a multiplexing and arbitration circuit that facilitates sharing RAM 26 through the switched access between the three components at the same time. The DMA 24 includes buffers for temporarily storing input data of components out of order, between access cycles. The DMA 24 stores text data and video data in the correct direction in RAM 26 and then retrieves the appropriate data from a selected address in a RAM, when necessary. As mentioned above, the RAM 26 preferably has a storage capacity of 4 Mbit or greater, and is subject to a large access load. A form of to accommodate the large access load and to transfer the data faster, is to select a RAM of 256KX16 bits, instead of a RAM of 512KX8 bits in order to allow the DMA 24 to sample more information, that is, 16 bits, per cycle of access, instead of 8 bits. The system receives a video signal from the tuner 50. The horizontal and vertical synchronization signals (h- and v-) are divided from the video signal and routed to the synchronization circuitry 28. The circuit set of synchronization includes an image element clock 28. The image element clock determines the x and y coordinates of each image element to be displayed on the screen. The y coordinate corresponds to the scan line number of the screen, and the x coordinate corresponds to the image element number in each scan line. The video portion of the input video from the tuner 50 is converted to an analog video signal Y U V, by the chrominance processor, on the television. This is a signal conversion intermediate commonly used in television systems between the input video and the RGV signal displayed on the cathode ray tube (CRT) 62. Figures 4A, 4B, and 4C illustrate the components Y _U V 54, 56, 58, respectively, of a video signal, in a standard color range. The component 54 is the luminance signal (Y) with a horizontal synchronization pulse 55. The component 56 is the chrominance signal (-V). Component 58 is the posterior plateau region of the chrominance signal (-U) for video fixation. Each component of the signal is converted into a digital form by the ADC 30 set-up circuitry, reducing distortion in the signal, due for example to low frequency noise and direct current bounce when the signal is interrupted. The PIG window generator 32 receives the video digital signals Y U V corresponding to the video image in full screen. The PIG window generator 32 reduces the overall image size, decimating the video data before sending them to the DMA 24 for storage in the VRAM. To decimate the video data, the PIG window generator 32, in cooperation with the synchronization circuits 28, selects for example, an output of every three image elements and one out of every three scanning lines, that is, a ratio of 1: 3, and then send this data to the DMA 24 for storage in the VRAM 33. Other decimation rates, for example, 1: 4, are also possible in order to generate PIG windows of different sizes. The correct address for storing the video data from the PIG window generator 32, in the VRAM 33, is determined by the set of circuits 40 for mapping the addresses, which is preferably incorporated in the DMA 24. Using the synchronization signal from the synchronization circuitry 28 and the image element clock 38, the address mapping delay circuitry 40 stores the video data corresponding to each image element in the cathode ray tube, in an appropriate address site in the VRAM for access later and its exhibition. This process is generally referred to as "bitmap mapping". The display generator 34 includes a graphics generator that formats the sources of the text to be presented, the icons, color and highlighting, and background graphics for the graphics portion 12 of the PIG display 10. The data The graphics are routed to the set of address mapping circuits 40 which, in cooperation with the DMA 24, stores the video data at address sites in the VRAM 33 corresponding to the coordinates of picture elements on the screen. The generation of the PIG display 10 (Fig. 1) in accordance with the preferred embodiment will now be explained. In response to an instruction device of the viewer 70, for example, an infrared remote control, for an EPG display in PIG format, the microprocessor 22 accesses the appropriate text data for that display of the unprocessed text data, in the Data RAM 31 The microprocessor 22 configures the text data for display and routes the text data, with appropriate addresses for text display, to the DMA 24, for storage in the VRAM 33. All the video data for generating the PIG display 10 , including the text and graphics of the graphics portion 12, and the video image of the PIG window 14, are stored in the VRAM 33 as described above. The display generator 34, in cooperation with the circuit set for the mapping of addresses 40 and the set of synchronization circuits 28, accesses the pre-organized content of the VRAM, to create an image to be displayed on the display of tubes of cathode rays 62. The data for each image element to be displayed on the screen is stored in the VRAM 33 with an address corresponding to an x and y coordinate of that image element on the screen. The display generator 34 accesses the appropriate data of the VRAM 33 for each image element in the sequence, as determined by the image element clock 38. using the synchronization signals from the synchronization circuitry 28. This synchronization signal is generated by the synchronization circuitry 28, from the synchronization signals h- and v- in the input video. Although it is preferable to store the entire field or frame of the screen, in VRAM 33, at the same time, in the form of bitmaps, less of the entire screen, that is only part of the screen, could be stored at the same time, and the display processing could actually be executed on image elements that are smaller than the entire screen. The display generator 34 converts the digital YUV signals for each picture element and outputs them to the DAC circuit set 36 in a continuous data stream in the appropriate data order, to produce a picture display in a guide, similar to the shown in Figure 1 on the cathode ray tube 62 screen. The DAC circuitry converts the data into YUV analog video signals. These YUV analog video signals are then converted into analog RGB signals by the set of RGB 60 conversion circuits in the television, before being displayed on the cathode ray tube screen 62. In an alternative embodiment of the invention, the RAM 30 is located "outside the the integrated circuit chip "where it is connected by a data bus to the DMA 24. The tuner 50, the chrominance processor 52, the RGB converter 60, the CRT 62, and the instructions of the viewer 70 are part of the apparatus of TV. In other words, these components serve the dual function of auxiliary in the visualization of the television signal, conventionally in a full-screen format, and to display the format of images in guide. The other components are unique to the guide image format. The design of the PIG circuitry, in accordance with the present invention, in a single IC chip 21, provides one more package economic, with a size and count of gates reduced. The invention reduces the overall gate count, by requiring only a single array of gates for each microprocessor 22, synchronization circuitry 28, DAC circuit set 36, and DNA 24 in place of two gate arrays for each of these components in my cr opl s of separate integrated PIP and EPG circuits, such as are used in known television systems, to generate a PIG display. It should also be noted that the vibration generator 34 feeds both image information and EPG information to the cathode ray tube 62 under the control of the pixel clock 38 and the synchronization circuitry 38 and the set synchronization circuits 28, in a continuous data stream. In this way, a video image (ie, a moving image) is created in an EPG display without a high-speed switch. The described embodiment of the invention is considered only preferred and illustrative of the inventive concept; the scope of invention will not be restricted to that modality. A person skilled in the art can contemplate numerous and several different arrangements, without departing from the spirit and scope of this invention. For example, several separate RAM could be used to store the EPG data, and the television signal reduced in size. In addition, the invention could be used in a digital television transmission system, as such, in which case the ADC, DAC and the VBI disconnector could be eliminated.

It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention, is that which is clear from the present description of the invention. Having described the invention as above, the content of the following is claimed as property.

Claims (10)

1. A guide image generator, characterized in that it comprises: an output adapted to drive a display monitor; a display generator, which feeds excitation signals to the output, in synchronization with the display monitor; an entrance adapted to receive a television signal; means connected to the input to extract information from the Electronic Program Guide (EPG) of the television signal; means for storing the EPG information, in the memory; means for reducing the size of the picture element, of the television signal; means for storing the television signal, with reduced image element size, in the memory; means for recovering the information of the EPG and of the television signal, of the memory; means for storing the information of the EPG, recovered, and the television signal, in the display generator; and means for feeding the information of the EPG, and the television signal, from the display generator, to the output, in a continuous stream of data, ordered, to produce a display of images in the guide, in the monitor.

2. The image generator in a guide, according to claim 1, and supplemented in a single chip of integrated circuits.

3. The guide image generator according to claim 2, characterized in that the extraction means consist of a vertical erase interval decoder (VBI).

4. The guide image generator, according to claim 3, characterized in that the memory comprises one or more RAM memories.

5. A guide image generator, characterized in that it comprises: a display controller, configured to receive a television signal and to reduce the size of picture elements of the television signal, and to extract information from the electronic program guide, of the television signal; the storage in memory of the information of the electronic program guide and of the television signal with reduced image element size; and the display generator that excites a display monitor and retrieves the electronic information of the program, and the television signal, to store them and supply them to the display monitor, in a continuous stream of data, arranged to produce an image display in a guide , on the display monitor.

6. The guide image generator, according to claim 5, characterized in that it also comprises a circuit for the mapping of addresses, configured to store the television signal, with reduced image element size, such as video data, such that the video data corresponds to an image element of the total screen field and that each image element is raised on a map to an address that represents a portion of the memory.

7. The guide image generator according to claim 5, characterized in that the memory is configured to store the television signal with reduced image element size, as groups of image elements that represent parts of a total screen field , in memory, at the time z.

8. A method for displaying a guide image, the method is characterized in that it comprises; receive a television signal; extract information from the electronic program guide, from the television signal; store in the memory, the information of the electronic program guide; reduce the size of picture elements of the television signal; store in the memory the television signal with reduced image element size; retrieve the information from the electronic program guide, and from the television signal, from the memory; store the information of the electronic program guide, and the television signal, recovered, in the display generator; and supplying the information of the electronic program guide, and the television signal, of the display generator, to an output adapted to excite a display monitor, in a continuous stream of data, arranged to produce a display of images in a guide, on the display monitor.

9. The method according to claim 8, characterized in that the storage of the television signal with image element size, reduced, in memory, includes storing each image element of a total screen field and lifting a map of each image element in a direction representing a specific portion in the memory

10. The method according to claim 8, characterized in that the storage of the television signal with reduced image element size in the memory includes grouping the television signal with reduced image element size into groups of elements of images that represent part of a total screen field, and store each of the groups of image elements, in memory, one at a time.