CN1299554A

CN1299554A - Picture-in-guide generator

Info

Publication number: CN1299554A
Application number: CN99803478A
Authority: CN
Inventors: 辛·K·唐; 丹·奥康诺尔; 亨利·C·恽
Original assignee: YINDEK SYSTEM CO
Current assignee: YINDEK SYSTEM CO
Priority date: 1998-01-26
Filing date: 1999-01-26
Publication date: 2001-06-13
Also published as: CA2318867C; CA2318867A1; AU2481099A; AU746029B2; BR9907745A; EP1062807A1; KR20010040419A; JP2002503898A; KR100376171B1; WO1999038322A1

Abstract

A picture-in-guide generator (21) has an output adapted to drive a display monitor (62) and an input adapted to receive a television signal. A display generator (34) feeds drive signals to the output in synchronism with the display monitor (62). EPG information is extracted from the television signal and stored in memory (26). The pixel size of the television signal is reduced. The reduced pixel size television signal is stored in memory (26). The EPG data and the television signal are retrieved from memory (26) and stored in the display generator (34). The EPG data and the television signal are fed from the display generator (34) to the output in a continuous data stream ordered to produce a picture-in-guide display (10) on the monitor (62). Preferably, the picture-in-guide generator (21) is implemented on a single integrated circuit chip.

Description

The Picture-in-guide maker

The U. S. application No.60/072 that the application's requirement was declared on January 26th, 1998,428 priority, all row are for referencial use at this for the content that this application disclosed.

Also all row are for referencial use: the application No.08/475 of newspaper in June 7 nineteen ninety-five, 395 at this for the content that following patent application disclosed; International application W096/07270; The application No.60/053 that on July 21st, 1997 declared, 330; The application No.60/061 that on October 6th, 1997 declared, 119; And on August 12nd, 1997 the application No.60/055 that declares, 237.Publication " CTC140 picture-in-picture system (CPIP) technical training handbook " (" The CTC 140 Picture inPicture System (CPIP) Technical Training Manual ", ThomsonConsumer Electronics, Inc.Indianapolis, IN) also be listed as for referencial use.

Electronic programming Leader (electronic program guide, i.e. EPG) is that the televiewer provides renewable television program schedule information with the form that screen graph shows.EPG can provide the information of the present and the future's programme time arrangement, and the summary of the content of TV program of some specific programs also is provided.

One especially easily the EPG form be that Picture-in-guide (picture-in-guide, i.e. PIG) shows.The PIG demonstration comprises the program Leader of a big figure and the real time video image of an interior TV programme of being watched that shows of a wicket therein.This PIG is shown as the spectator many selection schemes is provided.The spectator can simultaneously browse the TV schedule information in the Leader, and one side continues to watch the TV programme that he watches when advancing into the Leader.Perhaps, when spectator's cursor by in the Leader during program, the program that shows in the PIG window can be converted to corresponding selected channel in the Leader.The spectator also can show by scroll PIG, searches the information of more relevant his current programs of watching, and such as beginning/dwell time or program summary, continues to watch the program in embedding the PIG window simultaneously.

Usually, PIG EPG shows with an EPG maker generation, it comprises: a microprocessor, a vertical blanking interval (VBI) decoding/amplitude limiter, a screen display maker, a digital to analog converter (DAC), (synch) circuit synchronously, and one be configured in a memory on the chip, also comprises a picture-in-picture (PIP) maker that is configured on another chip, DAC, synchronous signal circuit and a Microprocessor Interface circuit.

The PIP maker makes the two-path video signal produce a big background frame and a little embedding picture respectively.This little picture is produced by extracting a sub-vision signal, for example, pixel of per three pixel decimations in the delegation of every triplex row extraction is write video memory.By normally scanning this big picture, and forward this little picture image of scanning to a high-speed switch during to the pip window district of display monitor screen, produce the synthetic demonstration of little picture with big picture background and embedding at scanner.Therefore this high-speed switch must operate at the line-scanning frequency of display monitor.

Yet, show for PIG, there is no need to provide the two-way real time video image, because the major part that shows comprises is text and graphical information, for example, program Leader, rather than real-time motion video image.The PIP high-speed switch is somewhat expensive.And EPG maker and PIP maker usefulness independently chip need more device, thereby are difficult to be integrated into household electrical appliance, for example, television receiver, VCR, satellite acceptor, or the like.

Therefore, desirable is to provide PIG to show that necessary device all is integrated in the monolithic.

The Picture-in-guide maker that the present invention proposes has one to be fit to drive the output of display monitor and the input of a suitable received television signal.Display generator is with drive signal and display monitor this output of synchronously feeding.EPG information is kept in the memory after extracting from TV signal.After dwindling, the pixel scale of TV signal is kept in the memory.EPG data and TV signal detect from memory, are kept in the display generator.EPG data and TV signal are fed to output so that continuous data is streamed from display generator, show to produce Picture-in-guide on monitor.Best, the Picture-in-guide maker is realized on the single integrated circuit sheet.

In the accompanying drawings illustration realize the specific embodiment of best mode of the present invention, wherein:

Fig. 1 illustration the program Leader of Picture-in-guide (PIG) form show;

Fig. 2 is the schematic diagram according to the PIG maker of one embodiment of the present of invention design;

Fig. 3 is the schematic diagram according to the RAM internal data structure of one embodiment of the present of invention design;

Fig. 4 is the schematic diagram of the YUV component of standard colour bar vision signal; And

Fig. 5 is according to the analog-to-digital conversion of one embodiment of the present of invention design and the schematic diagram of clamp circuit.

According to the present invention, draw (PIG) maker among the figure that is disposed and be used on video screen or computer monitor, producing the PIG demonstration.In the television system of using the PIG maker, there are two kinds of display types to use usually.First type is the realtime graphic of full screen display of broadcast TV programme.Second type, PIG shows, comprises the real time video image in background graphics and one of them little embedding window.

Fig. 1 illustration the PIG of an electronic programming Leader (EPG) show 10, comprise a visuals 12 and a picture window 14.Picture window 14 is hereinafter referred to as the PIG window, contains TV programme TV (image) image that a full screen video shows, but size dwindled, and all narrows down to 1/3rd usually on width and height, that is to say, is 1/9 of ins in full screen size.The another kind that the PIG system shows may screen be full screen graphical display.

The visuals 12 of PIG demonstration 10 is in occupation of the major part of screen.Visuals generally includes text, icon and the background graphics of some different colours.Figure can comprise that the text of screen or the high brightness of subregion show.In the EPG system, the spectator can browse different Leaders usually and not change the TV programme that shows in the PIG window 14.In some EPG systems, when the spectator is placed in vernier 16 on different channel identication 18 in the visuals or the program title 20, system just automatically with the tuning circuit 50 of association be tuned on the channel chosen, in PIG window 14, be presented at the program of broadcasting on this channel.

According to a preferred real examination example of the present invention, form PIG and show that 10 necessary parts all are configured on the single chip, so that incorporate television receiver, VCR, separate unit or satellite receiver etc. into.By all assemblies all are configured on the single chip, the size of whole sub-assembly can be dwindled, and the door number and the bus interface size of this chip can reduce.

Fig. 2 is the schematic diagram that is configured in some parts of the preferred real examination example of the present invention on the single chip 21. these parts comprise: microprocessor 22, storage control or direct memory access (DMA) (DMA) device 24, random-access memory (ram) 26, synchronizing regeneration (synchronizing signal) circuit 28, analog-to-digital conversion (ADC) and clamp circuit circuit 30, PIG window maker 32, display generator 34, and digital-to-analogue conversion (DAC) circuit 36.

Microprocessor 22 receives original text data from data source, and for example the EPG data write RAM 26.For example, the EPG data can be embedded in the vertical blanking interval of the TV signal that TV tuner 50 receives, are extracted by VBI decoding/amplitude limiter 37.Best, RAM 26 has 4M bit or bigger memory capacity, comprise the data RAM 31 of a storage text data and the video-ram (VRAM) 31 of stored video data, and the free zone as the service area between data RAM 31 and VRAM 33, as shown in Figure 3.Microprocessor 22 is organized the storage in the RAM 26, can be text data and video data assigned address.Yet, microprocessor 22 and Video processing hardware, for example PIG window maker 32 and display generator 34, it is slow comparing.Therefore, microprocessor 22 is only handled visit data and text data usually, rather than video data.Microprocessor and DMA 24 two-way communications.Microprocessor 22 is communicated by letter with DMA 24, by data/address bus and address bus visit RAM 26.

Preferable is to have only a RAM.This RAM 26 is by microprocessor 22, PIG window maker 32 and display generator 34 these three different component accesses.This makes RAM be subjected to highly visit, because three all assemblies may be competed the visit to RAM simultaneously.Yet each storage cycle has only the sample value of a so much bit (being 8 bits for 51 6KX8bit RAM for example) can access.For solving the arbitration between the assembly, multiplex adapter is essential.Therefore, microprocessor 22, PIG window maker 32 and display generator 34 are respectively by DMA24 visit RAM.DMA 24 is multiplexed and arbitration circuits, makes these three assemblies by access RAM Shared successively 26.DMA 24 comprises some buffer storage, is used for temporarily being stored in the data of never in-order assembly input between the storage cycle.DMA 24 is stored in text data and video data in the address correct among the RAM 26, retrieves correct data according to selected address from RAM in case of necessity then.

As mentioned above, RAM 26 preferably has 4M bit or bigger memory capacity, is added with the visit load of height.For adapting to this a kind of method of highly visiting load and accelerate transmitting data is to select 256KX1 6bit RAM rather than 51 2KX8bit RAM, so that make DMA 24 each storage cycle can the more information of access, that is to say, and be 16 bits rather than 8 bits.System is from tuning circuit 50 receiving video signals.Deliver to synchronous signal circuit 28 from level and vertical plane (h-and v-) synchronizing signal that vision signal is separated.Synchronous signal circuit comprises a pixel clock 28.Pixel clock determines x and the y coordinate that each pixel shows on screen.The y coordinate is corresponding to the capable number of screen scanning, and the x coordinate is corresponding to the pixel number in each scan line.

Be transformed to the YUV analog video signal from the video section of tuning circuit 50 inputs by the chroma processor in the television receiver 52.This is input video and the M signal conversion between the rgb signal that shows on the cathode ray tube (CRT) 62 that is generally used for television system.

Fig. 4 A, 4B and 4C respectively illustration the YUV component 54,56,58 of a standard vitta vision signal.Component 54 is with the brightness of horizontal synchronization pulse 55 (Y) signal.Component 56 is chrominance signal (V).Component 58 is Hou Yan districts of the carrier chrominance signal (U) that is used for the video clamp.Each component of signal is transformed to digital form by ADC/ clamp circuit 30 (seeing Fig. 5 for details).The clamp of ADC/ clamp circuit 30 has partly reduced in the signal distortion of beating and cause owing to for example low-frequency noise and the direct current when the switching signal.

PIG window maker 32 receives and full screen video image corresponding digital yuv video signal.PIG window maker sends to DMA24 by extracting after video data dwindles the whole image size, is stored in the VRAM.In order to extract video data, PIG window maker 32 is under synchronous signal circuit 28 cooperates, select a scan line to send to DMA 24 from this scan line pixels of per three pixel selection (that is to say 1/3) again from for example per three scan lines, be stored in the VRAM 33.Other decimation scale also are fine, and for example 1/4, so that form the PIG window of different size.

The correct address that the video data of PIG window maker 32 is deposited in VRAM 33 is by address translation circuit 40 decisions, and it preferably is incorporated in the DMA 24.Be used to the synchronizing signal of motor synchronizing signal circuit 28 and pixel clock 38, map addresses circuit 40 will be stored on the address correct in the VRAM with the corresponding video data of each pixel on the cathode ray tube, be used for display access after a while.This processing is commonly referred to " bit mapping ".

Display generator 34 comprises a graphic generator, is used for PIG is shown that 10 display text font, icon, color and high brightness demonstration, background graphics format.Graph data is delivered to map addresses circuit 40, it under DMA 24 cooperates, with video data be stored in the VRAM33 with pixel on the corresponding address of the coordinate on the screen.

To illustrate now according to this preferred embodiment and produce the situation that PIG shows 10 (Fig. 1).22 couples of spectators' of microprocessor command device 70, for example an Infrared remote controller responds, and shows that for given PIG EPG visit data RAM 31 reads the suitable text data that is used for this demonstration from original text data.The text data that microprocessor 22 configurations are used to show with the proper address that is used to show this text, sends to DMA 24, deposits VRAM 33 in.

All PIG that are used to form show 10 video data, comprise the text of visuals 12 and the vedio data of graph data and PIG window 14, all are kept in the VRAM 33, and are as described above.Display generator 34 reads the VRAM content of organizing in advance under the cooperation of map addresses circuit 40 and synchronous signal circuit 28, generate to be used for the image that shows on the screen of CRT 62.Need data in each pixel that shows on the screen all to be kept in the VRAM 33 with the x and the corresponding address of Y coordinate of this pixel on screen.The synchronizing signal that display generator 34 is used to motor synchronizing signal circuit 28 according to pixels clock 38 determined each pixel that are followed successively by from VRAM 33 reading corresponding data.Synchronizing signal is to be produced according to h in the input video and v synchronizing signal by synchronous signal circuit 28.

Though preferably once deposit the information sets or the frame of whole screen in VRAM 33 with the bit projected forms, but also can once store less than whole screen, that is to say and have only the part screen, and show that it is that unit carries out that processing is actually with the pixel groups less than whole screen.

Display generator 34 with the digital YUV signal conversion of each pixel after with the streamed DAC circuit 36 of exporting to successively of continuous data be similar to Picture-in-guide shown in Figure 1 and show so that on the screen of CRT 62, produce.The DAC circuit becomes simulation yuv video signal with data conversion.Simulation yuv video signal is transformed to the analog rgb signal by the RGB translation circuit 60 in the television receiver then, shows on the screen of CRT 62 again.

In another embodiment of the present invention, RAM 30 is arranged on outside the sheet, is connected to DMA 24 by data/address bus.

Tuning circuit 50, chroma processor 52, RGB converter 60, CRT 62 and spectator's command device 70 all are the parts of television receiver.In other words these parts have double action, both can be used for showing TV signal with full-screen format usually, also can be used for showing the Picture-in-guide form.Miscellaneous part has only the Picture-in-guide form just to have.

Thisly provide more economic assembly with the PIG circuit design on a monolithic 21 according to of the present invention, size is little and the door number is few.The present invention is owing to respectively only need single gate array for microprocessor 22, synchronous signal circuit 28, DAC circuit 36 and DMA 24, rather than resemble each two gate array of needs of these parts that are used for the television system that known generation PIG shows for being configured in respectively on the independently PIP and EPG sheet, therefore reduced a total number.Should also be noted that display generator 34 under 28 controls of pixel clock 38 and synchronous signal circuit with the form of continuous data stream with image information and the EPG information CRT 62 that all feeds.Therefore, just can in showing, EPG generate video (being moving frame) image without speed-sensitive switch.

Illustrated embodiments of the invention are the preferred embodiment and the illustrative embodiment of this inventive arrangements, and scope of the present invention has more than and is limited to such embodiment.Be proficient in the personnel of present technique as long as just can design various other configurations within the scope of the invention according to spirit of the present invention.For example, can store the TV signal that EPG data and picture have dwindled with RAM independently.In addition, the present invention also can be used for digital television transmission system, and in this case, ADC, DAC and VBI amplitude limiter can save.

Claims

1. Picture-in-guide maker comprises:

An output that is fit to drive a display monitor;

One with synchronously the feed display generator of described output of drive signal and display monitor;

The input of a suitable received television signal;

Be connected to described input, be used for from described TV signal extracting the device of EPG information;

Be used for the device of described EPG information stores in memory;

Be used for dwindling the device of the pixel scale of described TV signal;

Be used for the TV signal that pixel scale has been dwindled is stored in device in the memory;

Be used for going out the device of described EPG data and TV signal from memory search;

Being used for the EPG data that will be retrieved and TV signal is stored in device in the described display generator; And

Be used for EPG data and TV signal are fed to described output so that produce the Picture-in-guide device shown at described monitor so that continuous data is streamed from described display generator.

2. the Picture-in-guide maker of claim 1, described Picture-in-guide maker is realized with the form of single integrated circuit sheet.

3. the Picture-in-guide maker of claim 2, wherein said extraction element is a VBI decoder.

4. the Picture-in-guide maker of claim 3, wherein said memory comprises one or more RAM.