KR100367496B1 - Method for manufacturing contact hole in semiconductor device - Google Patents
Method for manufacturing contact hole in semiconductor device Download PDFInfo
- Publication number
- KR100367496B1 KR100367496B1 KR1019950050486A KR19950050486A KR100367496B1 KR 100367496 B1 KR100367496 B1 KR 100367496B1 KR 1019950050486 A KR1019950050486 A KR 1019950050486A KR 19950050486 A KR19950050486 A KR 19950050486A KR 100367496 B1 KR100367496 B1 KR 100367496B1
- Authority
- KR
- South Korea
- Prior art keywords
- contact hole
- semiconductor device
- etching
- interlayer insulating
- manufacturing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
Description
본 발명은 반도체 소자의 콘택홀 제조방법에 관한 것으로서, 특히 콘택홀 형성 시 평탄화막을 수직식각 및 경사식각으로 이단계 식각하여 콘택홀을 통하여 도전배선이 노출되는 것과 게이트 산화막의 손상 및 밀러(mirror) 효과 발생을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 콘택홀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact hole in a semiconductor device, and in particular, when a contact hole is formed, the planarization film is etched in two steps by vertical etching and inclined etching to expose conductive wiring through the contact hole and damage and mirror of the gate oxide film. The present invention relates to a method for manufacturing a contact hole of a semiconductor device which can prevent the occurrence of effects and improve process yield and device reliability.
최근 반도체 장치의 고집적화 추세는 미세 패턴 형성기술의 발전에 큰 영향을 받고 있다. 특히 감광막패턴은 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되고 있다.Recently, the trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology. In particular, the photoresist pattern is widely used as a mask such as an etching process or an ion implantation process in a semiconductor device manufacturing process.
따라서 반도체 소자의 고집적화를 위해서는 감광막 패턴의 미세화가 필수 요건인데, 상기 감광막패턴의 분해능은 축소노광장치의 광원의 파장 및 공정변수에 비례하고, 축소노광장치의 렌즈구경(numerical aperture; NA)에 반비례한다.Therefore, miniaturization of the photoresist pattern is essential for high integration of semiconductor devices. The resolution of the photoresist pattern is proportional to the wavelength and process variables of the light source of the reduction exposure apparatus, and inversely proportional to the numerical aperture (NA) of the reduction exposure apparatus. do.
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Is the limit.
따라서 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet), 예를 들어 파장이 248nm인 KrF 레이저나 193nm인 ArF 레이저를 광원으로 사용하는 축소노광장치를 이용한다.Therefore, a narrow exposure apparatus using a deep ultra violet, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, is used as a light source to form a fine pattern of 0.5 μm or less.
또한 상하의 도전배선을 연결하는 콘택 홀은 자체의 크기와 주변배선과의 간격이 감소되고, 콘택 홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다. 따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.In addition, the contact hole connecting the upper and lower conductive wiring is reduced in size and the distance between the peripheral wiring and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased. Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
상기 콘택 홀은 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalignment tolerance), 노광공정 시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다.The contact hole has misalignment tolerance during mask alignment, lens distortion during exposure process, critical dimension variation during mask fabrication and photolithography process, and between masks to maintain spacing. The mask is formed by considering factors such as registration.
또한 콘택홀 형성 시 리소그래피(Lithography) 공정의 한계를 극복하기 위하여 자기 정렬 방법으로 콘택홀을 형성하는 기술이 개발되었다. 자기 정렬 콘택홀 형성 방법 중 가장 유망한 것으로 질화막을 식각 방어막으로 사용하는 방법이 있다.In addition, in order to overcome the limitations of the lithography process in forming the contact holes, a technology for forming contact holes by a self-aligning method has been developed. The most promising method of forming a self-aligned contact hole is to use a nitride film as an etch barrier.
종래 반도체소자의 콘택홀 제조방법에 관하여 살펴보면 다음과 같다.A method of manufacturing a contact hole of a conventional semiconductor device is as follows.
먼저, 반도체기판 상에 게이트 산화막과 게이트전극, 엘.디.디(Lightly Doped Drain; 이하 LDD라 칭함) 구조의 소오스/드레인 접합, 산화막 스페이서 등으로 구성되는 모스 전계효과 트랜지스터를 형성하고, 상기 구조의 전 표면에 층간절연막을 형성한다.First, a MOS field effect transistor including a gate oxide film, a gate electrode, a source / drain junction having an L.D.D (lightly doped drain) structure, an oxide spacer, and the like is formed on a semiconductor substrate. An interlayer insulating film is formed on the entire surface of the film.
그 후, 상기 반도체기판에서 비트라인 또는 전하저장전극 콘택으로 예정되어 있는 부분 상의 층간절연막을 노출시키는 콘택홀 식각용 감광막패턴을 형성한 후, 상기 감광막패턴에 의해 노출되어 있는 층간절연막을 제거하여 반도체기판을 노출시키는 콘택홀을 형성한다.Thereafter, after forming the contact hole etching photoresist pattern exposing the interlayer insulating layer on the portion of the semiconductor substrate which is intended as the bit line or the charge storage electrode contact, the interlayer insulating layer exposed by the photoresist pattern is removed and the semiconductor is removed. A contact hole for exposing the substrate is formed.
상기와 같은 종래 기술에 따른 반도체소자의 콘택홀 제조방법은 콘택 식각시 수직 식각이나 경사 식각을 실시하는데, 초고집적 소자에서는 워드라인과 비트라인 등 다른 배선 간에 절연을 위한 공정여유가 없어 직접 적용이 어려운 문제점이 있다.In the method of manufacturing a contact hole of a semiconductor device according to the prior art as described above, a vertical etching or an inclined etching is performed at the time of contact etching. In an ultra-high density device, there is no process margin for insulation between other wirings such as word lines and bit lines, and thus it is directly applicable. There is a difficult problem.
또한, 식각 후 워드라인과 게이트 산화막이 드러나 누설전류가 증가되고, 밀러 효과 등이 발생하여 소자의 동작 특성을 떨어뜨리고, 수율을 감소시키는 다른 문제점이 있다.In addition, after etching, the word line and the gate oxide layer are exposed to increase the leakage current, and the Miller effect occurs to degrade the operation characteristics of the device and to reduce the yield.
본 발명은 위와 같이 콘택홀 식각 시 두 단계로 식각하여 콘택 윗쪽을 크게하고, 아래쪽의 콘택홀을 작게 함으로써 도전배선이나 게이트 산화막이 노출되는 것을 방지하여 게이트의 특성 저하나 배선간 단락을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 콘택홀 제조방법을 제공함에 있다.In the present invention, the contact hole is etched in two steps as described above to increase the contact upper part and to reduce the contact hole at the lower part, thereby preventing the conductive wiring or the gate oxide film from being exposed, thereby preventing the deterioration of the characteristics of the gate and the short circuit between the wires. The present invention provides a method for manufacturing a contact hole of a semiconductor device capable of improving yield and reliability of device operation.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 콘택홀 제조방법의 특징은,The characteristics of the contact hole manufacturing method of the semiconductor device according to the present invention for achieving the above object,
반도체기판 상에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the semiconductor substrate;
상기 층간절연막 상부에 콘택으로 예정되는 부분을 노출시키는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the interlayer insulating film to expose a portion to be contacted;
상기 감광막패턴을 식각마스크로 상기 층간절연막을 식각하여 콘택홀을 형성하되, 상기 층간절연막은 폴리머를 다량 유발시키는 식각가스를 사용하여 식각함으로써 상기 콘택홀의 상부는 수직의 프로파일을 갖고 콘택홀의 저부로 갈수록 측벽이 경사지는 프로파일을 갖는 콘택홀을 형성하는 공정을 구비함에 있다.The interlayer insulating layer is etched using the photoresist pattern as an etch mask to form a contact hole, and the interlayer insulating layer is etched using an etching gas that causes a large amount of polymer, so that the upper part of the contact hole has a vertical profile and gradually goes toward the bottom of the contact hole. A process of forming a contact hole having a profile in which sidewalls are inclined is provided.
이하, 본 발명에 따른 반도체소자의 콘택홀 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method for manufacturing a contact hole in a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 1 도는 본 발명에 따른 반도체소자의 콘택홀 제조방법을 설명하기 위한 개략도이다.1 is a schematic view for explaining a method for manufacturing a contact hole in a semiconductor device according to the present invention.
먼저, 반도체기판(1) 상에 소저의 하부 구조물, 예를 들어 게이트 산화막과, 다결정실리콘층 패턴으로 된 게이트전극과, 상기 게이트전극의 측벽에 형성되어 있는 산화막 스페이서와, 상기 게이트전극 양측의 반도체기판에 형성되어 있는 소오스/드레인 접합으로 구성되는 모스 전계효과 트랜지스터를 형성한다.First, a lower structure, for example, a gate oxide film, a gate electrode having a polysilicon layer pattern, an oxide spacer formed on sidewalls of the gate electrode, and semiconductors on both sides of the gate electrode are formed on the semiconductor substrate 1. A MOS field effect transistor formed of a source / drain junction formed on a substrate is formed.
그 다음, 상기 구조의 전 표면에 층간절연막(2)을 형성하고, 상기 반도체기판(1)에서 콘택으로 예정되어 있는 부분 상측의 층간절연막(2)을 노출시키는 콘택 마스크용 감광막패턴(3)을 형성한다.Then, the interlayer insulating film 2 is formed on the entire surface of the structure, and the photoresist film pattern 3 for contact mask exposing the interlayer insulating film 2 on the upper part of the semiconductor substrate 1, which is supposed to be a contact, is exposed. Form.
그 후, 상기 감광막패턴(3)에 의해 노출되어 있는 층간절연막(2)의 일부 두께, 예를 들어 40∼70% 정도 두께만을 소정의 식각 조건에서 일차 식각하여 수직한 측벽을 갖는 홈(4)을 형성하고, 다시 상기 홈(4) 저면의 나머지 층간절연막(2)을 소정의 식각 조건에서 이차로 경사 식각하여 경사진 측벽을 갖는 콘택홀(5)을 완성한다.Thereafter, only a part of the thickness of the interlayer insulating film 2 exposed by the photosensitive film pattern 3, for example, about 40 to 70% of the thickness is first etched under a predetermined etching condition to have a vertical sidewall 4 The remaining interlayer insulating film 2 on the bottom of the groove 4 is secondly inclinedly etched under a predetermined etching condition to complete the contact hole 5 having the inclined sidewall.
여기서, 상기 식각 공정 시의 두 단계의 식각은 콘택홀 윗 부분의 크기는 감광막패턴(3)이 노출시키는 크기와 같고, 일정 깊이 이하에서의 그 아래 부분의 크기는 감광막패턴(3)의 크기 보다 훨씬 작은 형상을 한다.Here, the etching of the two steps during the etching process, the size of the upper portion of the contact hole is equal to the size exposed by the photoresist pattern 3, and the size of the lower portion below a predetermined depth is smaller than the size of the photoresist pattern 3 It is much smaller.
이것은 다량의 C-F 또는 C-H계 폴리머를 유발하는 식각 가스인 C4F8/Ar, C4F8/CH3F/Ar, C3F8/CH3F/Ar 또는 C2F6/Ar/C2H2혼합가스 등과 같은 가스를 사용한 식각공정으로 형성된다.This is an etching gas that causes a large amount of CF or CH-based polymer, C 4 F 8 / Ar, C 4 F 8 / CH 3 F / Ar, C 3 F 8 / CH 3 F / Ar or C 2 F 6 / Ar / It is formed by an etching process using a gas such as C 2 H 2 mixed gas.
즉, 위와 같이 매우 많은 양의 폴리머를 유발하는 가스는 어느 일정 깊이에서부터 많은 폴리머가 증착되어 콘택홀의 크기를 작게 할뿐만 아니라, 이온들 중 입사각이 거의 수직인 이온들과 콘택 측벽과 충돌하는 이온들이 콘택홀 중앙부에 집중되어 콘택홀 중앙부위가 우선적으로 식각됨으로써 두 단계 형상을 형성하는 것으로 생각된다. 이는 콘택홀의 크기가 작아질 수록 두드러지는 현상이다.That is, the gas causing a very large amount of polymer as described above not only reduces the size of the contact hole by depositing a large amount of polymer from a certain depth, but also the ions colliding with the contact sidewalls and the ions having an almost incident angle among the ions. It is thought to form a two-step shape by focusing on the center of the contact hole and etching the center of the contact hole preferentially. This phenomenon is more prominent as the size of the contact hole becomes smaller.
이와 같은 형상을 형성할 수 있는 식각 조건은 아래와 같이 다량의 폴리머를 유발할 수 있는 식각 가스를 사용하여 다음과 같은 조건에서 식각을 실시하면 된다.Etching conditions capable of forming such a shape may be etched under the following conditions using an etching gas capable of causing a large amount of polymer as follows.
1. C4F85∼20sccm, Ar 50∼150sccm, power 1000∼2500W, 전극온도 -10∼15℃, 압력 3∼10mTorr,1.C 4 F 8 5 ~ 20sccm, Ar 50 ~ 150sccm, power 1000 ~ 2500W, electrode temperature -10 ~ 15 ℃, pressure 3 ~ 10mTorr,
2. C4F85∼15sccm, Ar 50∼150sccm, CH3F 1∼10sccm, 전극온도 -10∼15℃, 압력 3∼10mTorr, power 1000∼2500w,2. C 4 F 8 5-15 sccm, Ar 50-150 sccm, CH 3 F 1-10 sccm, electrode temperature -10-15 ° C., pressure 3-10 mTorr, power 1000-2500 w,
3. C3F85∼20sccm, Ar 50∼150sccm, CH3F 3∼15sccm, 전극온도 -10∼15℃, 압력 3∼10mT, power 1000∼2500w,3.C 3 F 8 5-20sccm, Ar 50-150sccm, CH 3 F 3-15sccm, electrode temperature -10-15 ℃, pressure 3-10mT, power 1000-2500w,
4. C2F610∼30sccm, Ar 50∼150sccm, C2H210∼40sccm, 전극온도 -10∼15℃, 압력 5∼15mTorr, power 1000∼2500w의 식각조건에 의해 층간절연막(2)을 식각하여 콘택홀을 형성한다.4. C 2 F 6 10 ~ 30sccm, Ar 50 ~ 150sccm, C 2 H 2 10 ~ 40sccm, electrode temperature -10 ~ 15 ℃, pressure 5 ~ 15mTorr, power 1000 ~ 2500w To form a contact hole.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 콘택홀 제조방법은, 콘택홀 식각 시 식각형상을 시직 식각 및 경사식각의 두 단계로 형성함으로써 워드라인이나 비트라인등의 도전배선이 드러나는 것을 방지하여 두 단계의 식각 형상은 콘택홀 윗 부분의 크기는 감광막 마스크의 크기와 같고, 일정 깊이 이하에서의 그 아래 부분의 크기는 마스크의 크기보다 훨씬 작은 형상이 되도록 다량의 폴리머를 유발하는 식각 가스들을 어느 일정 깊이에서부터 많은 폴리머가 증착되어 콘택홀의 크기를 작게 할뿐만 아니라 이온들 중 입사각이 거의 수직인 이온들과 콘택 측벽과 충돌하는 이온들이 콘택홀 중앙부에 집중되어 콘택홀 중앙부위가 우선적으로 식각됨으로써 두단계 형상으로 콘택홀을 형성하였으므로, 워드라인 절연을 위한 추가 공정이 필요없고, 워드라인이 드러남으로써 야기되는 게이트 산화막 손상이나 밀러 효과 등을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the method for manufacturing a contact hole of a semiconductor device according to the present invention prevents the conductive wiring such as a word line or a bit line from being exposed by forming an etch shape in two steps, a vertical etching and an inclined etching. The two-step etch shape is such that the top of the contact hole is the same size as the photoresist mask, and below a certain depth, the bottom is much smaller than the size of the mask. In addition to depositing a large amount of polymer from a certain depth to reduce the size of the contact hole, the ions colliding with the contact sidewalls are concentrated in the center of the contact hole with ions having an almost perpendicular angle of incidence among the ions. Since the contact hole is formed in a step shape, an additional process for word line insulation is necessary. There is an advantage in that it is possible to prevent the gate oxide damage or the Miller effect caused by the word line being exposed, thereby improving process yield and reliability of device operation.
제 1 도는 본 발명에 따른 반도체소자의 콘택홀 제조방법을 설명하기 위한 개략도.1 is a schematic view for explaining a method for manufacturing a contact hole in a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 : 층간절연막1: semiconductor substrate 2: interlayer insulating film
3 : 감광막패턴 4 : 홈3: photosensitive film pattern 4: groove
5 : 콘택홀5: contact hole
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050486A KR100367496B1 (en) | 1995-12-15 | 1995-12-15 | Method for manufacturing contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950050486A KR100367496B1 (en) | 1995-12-15 | 1995-12-15 | Method for manufacturing contact hole in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970052241A KR970052241A (en) | 1997-07-29 |
| KR100367496B1 true KR100367496B1 (en) | 2003-03-03 |
Family
ID=37491156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950050486A KR100367496B1 (en) | 1995-12-15 | 1995-12-15 | Method for manufacturing contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100367496B1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766185A (en) * | 1993-08-27 | 1995-03-10 | Nippondenso Co Ltd | Fabrication of semiconductor device |
| JPH07106277A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1995
- 1995-12-15 KR KR1019950050486A patent/KR100367496B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766185A (en) * | 1993-08-27 | 1995-03-10 | Nippondenso Co Ltd | Fabrication of semiconductor device |
| JPH07106277A (en) * | 1993-10-05 | 1995-04-21 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970052241A (en) | 1997-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100474546B1 (en) | Fabricating method for semiconductor device | |
| KR100465596B1 (en) | A manufacturing method for semiconductor device | |
| EP0859400A2 (en) | Improvements in or relating to integrated circuits | |
| KR100527577B1 (en) | Fabricating method for semiconductor device | |
| KR100367496B1 (en) | Method for manufacturing contact hole in semiconductor device | |
| KR100258365B1 (en) | Method for fabricating contact hole of semiconductor device | |
| KR100367493B1 (en) | Method for manufacturing semiconductor device | |
| KR100197655B1 (en) | Process for forming contact hole in semiconductor device | |
| KR100308500B1 (en) | Contact hole formation method of semiconductor device | |
| KR100369867B1 (en) | Method for manufacturing semiconductor device | |
| KR20010063763A (en) | Manufacturing method for semiconductor device | |
| KR100261682B1 (en) | Method for fabricating semiconductor device | |
| KR100333550B1 (en) | Fabricating method for semiconductor device | |
| KR20000045328A (en) | Method for manufacturing semiconductor device | |
| KR100323717B1 (en) | Method for manufacturing of semiconductor device | |
| KR100333542B1 (en) | Contact plug formation method of semiconductor device | |
| KR100465604B1 (en) | Manufacturing method of semiconductor device | |
| KR100367494B1 (en) | Method for manufacturing contact hole in semiconductor device | |
| KR100861188B1 (en) | Manufacturing method for semiconductor device | |
| KR100434961B1 (en) | Method of forming contact hole of semiconductor device using nitride pattern formed on only gate electrode as etch stop layer | |
| KR20000027790A (en) | Method of manufacturing a semiconductor device | |
| KR20000043225A (en) | Method for etching nitride layer of semiconductor device | |
| KR20000027639A (en) | Method for manufacturing contact plug of semiconductor devices | |
| KR20060114447A (en) | Manufacturing method for semiconductor device | |
| KR20000045450A (en) | Fabrication method of storage electrode for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101125 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |