KR100365053B1 - Semiconductor package and its manufacturing method - Google Patents

Abstract

The present invention relates to a semiconductor package and a method of manufacturing the same, and does not use a separate subsidiary material, for example, an expensive substrate, thereby reducing costs, improving heat dissipation performance and minimizing the effects of various moisture. A semiconductor chip having a plurality of input / output pads formed on an inner circumferential surface of the upper surface to complete all of the plurality of semiconductor packages at a wafer level; A plurality of circuit patterns having a bond finger and a ball land on an upper surface of the semiconductor chip which is inside the input / output pad; A cover coat coated on an upper surface of the semiconductor chip and the circuit pattern except for the input / output pad, bond finger, and borland; A plurality of electrical connection means for electrically connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit patterns; An encapsulation portion encapsulated in an input / output pad and an electrical connection means of the semiconductor chip; It characterized in that it comprises a plurality of conductive balls fused to the ball land exposed to the outside of the cover pattern of the circuit pattern.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a wafer scale chip size semiconductor package and a method for manufacturing the same.

In general, a chip size semiconductor package refers to a package having a size close to that of a semiconductor chip by using a thin layer structure and a ball array method. These chip-sized semiconductor packages operate at a high speed but require only a minimum area for mounting and meet the requirements of communication devices, cellular phones, laptops, wireless systems, etc., which must satisfy space and speed requirements. It is a trend that is being used rapidly in recent years.

Such a chip size semiconductor package 100 '(hereinafter, simply referred to as a semiconductor package 100') is shown in FIG. 1, and a conventional structure will be briefly described with reference to this.

First, a semiconductor chip 1 'having a plurality of input / output pads 1a' formed around the periphery of the upper surface. Such a semiconductor chip 1 'is also called an edge pad type semiconductor chip.

An adhesive means 2 'having a predetermined thickness is adhered to an upper surface of the semiconductor chip 1', that is, an input / output pad 1a ', and a normal substrate 10 is attached to the upper surface of the adhesive means 2'. ') Is glued. That is, a fine and complicated conductive circuit pattern 12 'is formed on the surface, and the circuit pattern 12' is coated by a cover coat 11 '. Here, the circuit pattern 12 ′ may be divided into a bond finger 13 ′ connected by a conductive wire 30 ′ to be described below, and a ball land 12 a ′ where the conductive ball 40 ′ to be welded is fused. . That is, a plurality of bond fingers 13 'are formed at the periphery of the semiconductor chip 1' toward the input / output pad 1a ', and the bond fingers 13' are formed on each of the ball lands 12a '. It is connected. In addition, the ball land 12a 'is opened by the cover coat 11'.

Meanwhile, as described above, the I / O pad 1a 'of the semiconductor chip 1' and the bond finger 13 'of the printed circuit board 10' are made of conductive wire 30 'such as gold wire or aluminum wire. Interconnected portions of the semiconductor chip 1 ', the predetermined region of the side and the upper surface, the conductive wire 30', the bond finger 13 'of the substrates 10', and the like are encapsulated with an encapsulant and fixed. A sealing portion 50 'is formed.

In addition, all of the conductive balls 40 'such as solder balls are fused to the ball lands 12a' of the substrates 10 ', so that they can be mounted on the motherboard later. Of course, when the motherboard is mounted on the motherboard, the semiconductor package shown in FIG. 1 is mounted upside down.

Accordingly, in the semiconductor package 100 ', the signal of the semiconductor chip 1' is connected to the input / output pad 1a ', the conductive wire 30', the bond finger 13 'and the borland of the circuit pattern 12'. 12a ', it is transmitted to the motherboard through the conductive ball 40', the electrical signal of the motherboard is transmitted to the reverse.

However, such a conventional semiconductor package must use an expensive substratum, which is a separate subsidiary material, so that the overall price of the semiconductor package becomes expensive. For reference, the cost of the substrate and the adhesive means for attaching the substrate to the surface of the semiconductor chip is approximately 50% or more of the total semiconductor package price.

In addition, by attaching the substrate to one surface of the semiconductor package by using the adhesive means, the heat dissipation performance of the side to which the substrate is attached is not only lowered, but also the hygroscopicity of the substrate and the adhesive means for attaching the substrate is high in a high temperature environment. There is a disadvantage that the interfacial peeling phenomenon occurs easily.

In addition, the resin layer among the components of the bonding means and the substrate has a predetermined elasticity, and this elasticity often occurs when one end of the conductive wire is not well bonded to the bond finger of the substrate.

In addition, the conventional semiconductor package is a problem that the workability is worse and the productivity is significantly reduced compared to the wafer-scale manufacturing process, since all the manufacturing process is carried out after each semiconductor chip is attached to a substrate or strip type matrix. There is.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, the object of the present invention is to reduce the cost and improve heat dissipation performance by not using a separate subsidiary material, for example, an expensive substrate At the same time to minimize the effects of various moisture, and to provide a semiconductor package that can minimize the wire bonding failure.

Another object of the present invention is to provide a method for manufacturing a semiconductor package that can maximize productivity by completing a plurality of semiconductor packages at the wafer level.

1 is a cross-sectional view showing a conventional semiconductor package.

2A and 2B are cross-sectional views showing a semiconductor package according to the present invention.

3A to 3J are sequential explanatory diagrams showing a method of manufacturing the semiconductor package shown in FIG. 2A.

4 is a partial plan view of FIG. 3F.

5A to 5H are sequential explanatory diagrams showing the manufacturing method of the semiconductor package shown in FIG. 2B.

-Description of the main symbols in the drawings-

11,12; Semiconductor package according to the present invention

One; Semiconductor chip 1a; I / O pad

2; Bonding means 3; Circuit pattern

3a; Bond Finger 3b; Ball Land

4; Cover coat 5; Conductive ball

6; Connection means 7; Encapsulation

w; Wafer cf; Copper thin film

f; film

In order to achieve the above object, the semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads formed on an inner circumferential edge of an upper surface thereof; A plurality of circuit patterns having a bond finger and a ball land on an upper surface of the semiconductor chip which is inside the input / output pad; A cover coat coated on an upper surface of the semiconductor chip and the circuit pattern except for the input / output pad, bond finger, and borland; A plurality of electrical connection means for electrically connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit patterns; An encapsulation portion encapsulated in an input / output pad and an electrical connection means of the semiconductor chip; It characterized in that it comprises a plurality of conductive balls fused to the ball land exposed to the outside of the cover pattern of the circuit pattern.

The side surfaces of the encapsulation portion and the semiconductor chip may be the same surface.

In addition, the electrical connection means may be formed by bonding the bond finger directly on the upper surface of the input and output pad of the circuit pattern.

In addition, an adhesive means may be further interposed between the circuit pattern and the semiconductor chip.

In addition, the method for manufacturing a semiconductor package according to the present invention in order to achieve the above object comprises the steps of preparing a wafer having a plurality of semiconductor chips having a plurality of input and output pads formed on the upper surface, and forming a copper thin film on the upper surface of the wafer; Forming a film having a circuit pattern on an upper surface of the copper thin film; Providing an etching solution to the wafer such that the copper thin film becomes a circuit pattern made of a bond finger and a ball land; Forming a cover coat on an upper surface of the circuit pattern excluding the bond finger and the borland and an input / output pad of each semiconductor chip; Connecting the bond fingers of the input / output pads and the circuit patterns of the semiconductor chips with electrical connection means; Forming an encapsulation part by filling an encapsulant in the input / output pad and the electrical connection means of each semiconductor chip; Fusing a conductive ball to a ball land of the circuit pattern; And singulating a single semiconductor chip from the wafer.

Here, the copper thin film may be attached to the upper surface of the wafer by the adhesive means.

In addition, the copper thin film may be formed by any one of vacuum evaporation, sputtering, or chemical vapor deposition (CVD).

In addition, the film may be formed by applying a photosensitive dry film in close contact with the surface of the copper thin film with heat and pressure and then irradiating light using a master film having a circuit pattern.

In addition, the film may be formed by printing only the circuit pattern portion on the surface of the copper thin film by the silk screen in which the circuit pattern appeared.

In addition, the electrical connection means may be formed by directly bonding the bond finger on the upper surface of the input / output pad of the semiconductor chip.

As described above, the semiconductor package and the method of manufacturing the same according to the present invention have the advantage that the price of the overall semiconductor package can be reduced by not adopting the expensive substrate as in the prior art.

In addition, since the heat of the semiconductor chip is directly transmitted to the metallic circuit pattern and released to the outside, the heat dissipation performance is significantly improved compared to the conventional one, and since there is no material (for example, a substrate) that absorbs moisture, There is an advantage that the adverse effect is eliminated.

In addition, since the bond finger of the circuit pattern is directly positioned on the upper surface of the semiconductor chip having a high hardness, vibration does not occur up and down during wire bonding using conductive wires, and thus the wire bonding defect rate is remarkably lowered.

In addition, the present invention has the advantage of excellent workability and high productivity since all the packaging processes are completed in the state where a plurality of semiconductor chips are formed.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

2A and 2B are cross-sectional views showing semiconductor packages 11 and 12 according to the present invention.

First, the semiconductor package 11 of FIG. 2A is referred to.

As illustrated, a semiconductor chip 1 having a plurality of input / output pads 1a formed on an inner circumferential surface of the upper surface is provided.

A plurality of circuit patterns 3 having a bond finger 3a and a ball land 3b are formed on an inner surface of the input / output pad 1a as an upper surface of the semiconductor chip 1. As is well known, the circuit pattern 3 may be formed on the upper surface of the semiconductor chip 1 by a method such as vacuum evaporation, sputtering, or chemical vapor deposition (CVD).

Here, the bond fingers 3a are all formed at positions adjacent to the input / output pads 1a, and the ball lands 3b are arrayed on the upper surface of the semiconductor chip 1 when connected thereto.

A cover made of an insulating resin on the upper surface of the semiconductor chip 1 and the circuit pattern 3 except for the bond finger 3a and the borland 3b of the input / output pad 1a and the circuit pattern 3 of the semiconductor chip 1. The coat 4 is coated. The cover coat 4 serves to protect the circuit pattern 3 from the external environment as is well known.

Subsequently, the bond fingers 3a of the input / output pads 1a and the circuit patterns 3 of the semiconductor chip 1 may be formed of conductive wires (for example, gold wires or aluminum wires). They are interconnected by the same electrical connecting means 6.

In addition, the input / output pad 1a and the electrical connection means 6 of the semiconductor chip 1 are encapsulated with an encapsulant such as an epoxy molding compound or a glove top, so that a certain encapsulation portion ( 7) It is located inside.

Here, the side surface of the encapsulation portion 7 and the side surface of the semiconductor chip 1 are coplanar. Of course, both the side and bottom surfaces of the semiconductor chip 1 are directly exposed to air.

Lastly, conductive balls 5 such as solder balls are fused to the ball lands 3b exposed to the outside of the cover coat 4 of the circuit pattern 3, so that they can later be mounted on a motherboard. In form.

Next, reference is made to the semiconductor package 12 of FIG. 2B. Here, since the semiconductor package 12 of FIG. 2B has a structure similar to that of the semiconductor package 11 of FIG. 2A, only the differences will be described.

As shown, an adhesive means 2 may be further interposed between the semiconductor chip 1 and the circuit pattern 3. That is, in the semiconductor package 11 of FIG. 2A, the circuit pattern 3 is directly formed by a method such as vacuum deposition, sputtering, or CVD on the upper surface of the semiconductor chip 1, but in the semiconductor package 12 of FIG. (2) The circuit pattern 3 is formed on the upper surface by a method such as vacuum deposition, sputtering, or CVD.

In addition, the bonder 3a extends to the upper surface of the input / output pad 1a of the semiconductor chip 1, and the extended bond finger 3a extends to the input / output pad 1a. It may be formed by direct lead bonding. That is, although the conductive package is used as the electrical connecting means 6 in the semiconductor package 11 of FIG. 2A, the bond finger 3a of the circuit pattern 3 is used as the electrical connecting means 6. ) Is used directly.

3A to 3J are explanatory views showing a method of manufacturing the semiconductor package 11 shown in FIG. 2A, FIG. 4 is a partial plan view of FIG. 3F, and FIGS. 5A to 5H are the semiconductor packages shown in FIG. It is explanatory drawing which showed the manufacturing method of 12).

Referring to this, the present invention will be described sequentially as follows.

1. As a copper thin film forming step, a circular wafer w having a plurality of semiconductor chips 1 having a plurality of input / output pads 1a formed thereon is prepared, and a copper thin film having a predetermined thickness on the upper surface of the wafer w. (cf) (see Figures 3a, 3b, 3c).

In this case, the copper thin film cf may be formed by any one of vacuum evaporation, sputtering, or chemical vapor deposition (CVD).

That is, a vacuum deposition method in which a material of a source (for example, copper (Cu)) is deposited on the upper surface of the wafer (when using E-Beam or filament deposition) using heat in a vacuum state is used. Alternatively, a sputtering method in which argon ions collide with copper (Cu) so that copper atoms are deposited on the surface of the wafer (w), or a gas containing copper atoms is reacted with another gas, and the copper obtained at this time is the wafer (w). A CVD method can be used to be deposited on.

On the other hand, in addition to the above-described method, the copper thin film cf may be attached to the surface of the wafer w with an adhesive means 2 interposed therebetween, and this method is advantageous in terms of cost.

2. As a film forming step, a film f in which a circuit pattern appears on the upper surface of the copper thin film cf is formed (see FIG. 3D and FIG. 5B).

That is, the film (f) is applied to the surface of the copper thin film (cf) by applying a photosensitive dry film in close contact with the heat and pressure, and then irradiated with light using a master film having a circuit pattern, and then developed a predetermined circuit pattern shape Film (f) can be formed.

In addition, the film f may use a method of printing only the circuit pattern portion on the surface of the copper thin film cf by the silk screen on which the circuit pattern appears.

3. A circuit patterning step of a copper thin film, wherein the copper thin film cf is partially etched by providing an etching solution to the wafer w, whereby a predetermined circuit pattern having a bond finger 3a and a ball land 3b ( 3) is formed (see FIG. 3E and FIG. 5C). After this process is completed, the film f is peeled off and removed.

4. A cover coat forming step, wherein the cover coat 4 is an insulating resin on the upper surface of the circuit pattern 3 except for the bond fingers 3a and the borland 3b and the input / output pads 1a of each semiconductor chip 1. (See FIGS. 3F and 5D) The state in which the cover coat 4 is coated as described above is shown in more detail in FIG. That is, an insulating cover coat 4 is coated on the region of the input / output pad 1a and the vicinity of the semiconductor chip 1 and the regions except for the bond fingers 3a and the ball lands 3b of the circuit pattern 3. .

5. In the electrical connection step, the input / output pads 1a of the semiconductor chips 1 and the bond fingers 3a of the circuit patterns 3 are electrically connected to each other using conductive wires (Fig. 3G).

In addition to the above method, the bond finger 3a may be extended to the upper surface of the input / output pad 1a of the semiconductor chip 1 and then directly bonded to the surface of the input / output pad 1a (see FIG. 5E).

6. In the step of forming the encapsulation part, the encapsulant is filled in the input / output pad 1a and the electrical connection means 6 of each semiconductor chip 1 so that the electrical connection means 6 and the like are protected from the external environment. (See Figures 3H and 5F)

7. Conductive ball fusion step, in which the conductive balls 5 such as solder balls are fused to the ball lands 3b of the circuit pattern 3 (see FIGS. 3i and 5g).

8. As a singulation step, by singulating each of the semiconductor chips 1 from the wafer w, individual semiconductor packages 11 and 12 are provided (see Figs. 3J and 5H).

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, there is an effect that the price of the overall semiconductor package can be lowered by not adopting the expensive substrate as in the prior art.

In addition, since the heat of the semiconductor chip is directly transmitted to the metallic circuit pattern and released to the outside, the heat dissipation performance is significantly improved compared to the conventional one, and since there is no material (for example, a substrate) that absorbs moisture, It also has the effect of eliminating adverse effects.

In addition, since the bond finger of the circuit pattern is directly positioned on the upper surface of the semiconductor chip having a high hardness, vibration does not occur up and down during wire bonding using conductive wires, thereby reducing the wire bonding defect rate.

In addition, according to the present invention, all the packaging processes are completed in a wafer state in which a plurality of semiconductor chips are formed, thereby providing excellent workability and high productivity.

Claims (10)

A semiconductor chip having a plurality of input / output pads formed on an inner circumference of an upper surface thereof; A plurality of circuit patterns having a bond finger and a ball land on an upper surface of the semiconductor chip which is inside the input / output pad; A cover coat coated on an upper surface of the semiconductor chip and the circuit pattern except for the input / output pad, bond finger, and borland; A plurality of electrical connection means for electrically connecting the input / output pads of the semiconductor chip and the bond fingers of the circuit patterns; An encapsulation portion encapsulated in an input / output pad and an electrical connection means of the semiconductor chip; A semiconductor package comprising a plurality of conductive balls fused to the ball land exposed to the outside of the cover coat of the circuit pattern. The semiconductor package according to claim 1, wherein the side surfaces of the encapsulation portion and the semiconductor chip are flush with each other. The semiconductor package according to claim 1, wherein the electrical connection means is formed by bonding a bond finger directly to an upper surface of an input / output pad in a circuit pattern. The semiconductor package according to claim 1, wherein an adhesion means is further interposed between the circuit pattern and the semiconductor chip. Preparing a wafer having a plurality of semiconductor chips having a plurality of input / output pads formed thereon, and forming a copper thin film on an upper surface of the wafer; Forming a film having a circuit pattern on an upper surface of the copper thin film; Providing an etching solution to the wafer such that the copper thin film becomes a circuit pattern made of a bond finger and a ball land; Forming a cover coat on an upper surface of the circuit pattern excluding the bond finger and the borland and an input / output pad of each semiconductor chip; Connecting the bond fingers of the input / output pads and the circuit patterns of the semiconductor chips with electrical connection means; Forming an encapsulation part by filling an encapsulant in the input / output pad and the electrical connection means of each semiconductor chip; Fusing a conductive ball to a ball land of the circuit pattern; A method of manufacturing a semiconductor package comprising the step of singulating into a single semiconductor chip from the wafer. The method of manufacturing a semiconductor package according to claim 5, wherein the copper thin film is attached to an upper surface of the wafer by an adhesive means. The method of claim 5, wherein the copper thin film is formed by any one of vacuum evaporation, sputtering, and chemical vapor deposition (CVD). The method of claim 5, wherein the film is formed by closely applying a photosensitive dry film to the surface of the copper thin film with heat and pressure, and then developing the film by irradiating light using a master film having a circuit pattern. . The method of manufacturing a semiconductor package according to claim 5, wherein the film is formed by printing only the circuit pattern portion on the surface of the copper thin film by the silk screen on which the circuit pattern appears. The method of claim 5, wherein the electrical connection means is formed by directly bonding the bond finger to an upper surface of the input / output pad of the semiconductor chip.