KR100355606B1 - Method For Forming The Contact Hole Of Semiconductor Device - Google Patents
Method For Forming The Contact Hole Of Semiconductor Device Download PDFInfo
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- KR100355606B1 KR100355606B1 KR1019990065199A KR19990065199A KR100355606B1 KR 100355606 B1 KR100355606 B1 KR 100355606B1 KR 1019990065199 A KR1019990065199 A KR 1019990065199A KR 19990065199 A KR19990065199 A KR 19990065199A KR 100355606 B1 KR100355606 B1 KR 100355606B1
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- contact hole
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- poly layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 230000000873 masking effect Effects 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은, 반도체소자의 콘택홀 형성방법에 관한 것으로서, 특히, 반도체기판에 게이트를 형성한 후, 층간절연막을 적층하고, 마스킹 식각으로 게이트의 마스크산화막을 식각하면서 캡폴리층을 노출시켜 콘택홀을 형성할 때, 펄스 모듈레이션 (Pulse Modulation)을 사용하여 콘택홀을 형성하므로 식각 선택비를 높일 수 있어서 캡폴리층에 손실이 발생되는 것을 방지하므로 콘택홀 내에 형성되는 콘택플러그의 콘택저항을 감소하도록 하는 매우 유용하고 효과적인 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, after forming a gate in a semiconductor substrate, stacking an interlayer insulating film, exposing a contact hole by exposing a cap poly layer while etching a mask oxide film of the gate by masking etching. When forming the contact hole, the contact hole is formed using pulse modulation to increase the etching selectivity, thereby preventing the loss of the cap poly layer, thereby reducing the contact resistance of the contact plug formed in the contact hole. To a very useful and effective invention.
Description
본 발명은 게이트로 연결되는 콘택홀을 형성하는 방법에 관한 것으로서, 특히, 반도체기판에 게이트를 형성한 후, 층간절연막을 적층하고, 마스킹식각으로 게이트의 마스크산화막을 식각하면서 캡폴리층을 노출시켜 콘택홀을 형성할 때, 펄스 모듈레이션(Pulse Modulation)을 사용하여 콘택홀을 형성하므로 식각 선택비를 높일 수 있어서 캡폴리층에 손실이 발생되는 것을 방지하도록 하는 반도체소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method of forming a contact hole connected to a gate. In particular, after forming a gate in a semiconductor substrate, an interlayer insulating film is laminated, and a cap poly layer is exposed by etching a mask oxide film of the gate by masking etching. When forming the contact hole, the contact hole is formed by using pulse modulation (Pulse Modulation) relates to a method for forming a contact hole of a semiconductor device to increase the etching selectivity to prevent the loss occurs in the cap poly layer .
일반적으로, 게이트에 연결되는 콘택 식각시, 텅스텐실리사이드와 폴리실리콘층으로 된 텅스텐폴리사이드구조의 게이트에 연결되는 콘택홀의 경우에는, 텅스텐실리사이드층과 비금속층(Non Metal)인 콘택폴리 플러그(Contact Poly Plug)가 연결되는 콘택인 쇼트키 콘택(Schottky Contact)과, 텅스텐실리사이드층과 금속층 (Metal)인 텅스텐 플러그(Tungsten Plug)가 연결되는 콘택인 오믹 콘택(Ohmic Contact)이 있다.In general, in the case of contact etching connected to the gate, in the case of the contact hole connected to the gate of the tungsten polyside structure of tungsten silicide and polysilicon layer, the contact poly plug, which is a tungsten silicide layer and a non-metal layer, is used. Schottky Contact, which is a contact to which a plug is connected, and Ohmic Contact, which is a contact to which a tungsten silicide layer and a tungsten plug, which is a metal layer, are connected.
상기한 쇼트키 콘택을 형성하기 위하여 콘택홀을 식각하는 경우, 게이트의 텅스텐실리사이드층과 콘택폴리 플러그가 직접적으로 연결되는 경우, 콘택 저항이 커지는 문제를 지닌다. 그래서 게이트의 텅스텐실리사이드층과 마스크 산화막 사이에 캡폴리층을 개재하여서 쇼트키 콘택을 형성하도록 한다.When the contact hole is etched to form the Schottky contact, when the tungsten silicide layer of the gate and the contact poly plug are directly connected, the contact resistance is increased. Thus, a Schottky contact is formed between the tungsten silicide layer of the gate and the mask oxide film via a cap poly layer.
그러나, 종래에는 콘택식각공정으로 쇼트키 콘택홀을 형성하는 경우, 식각 선택비가 좋지 않아서 캡폴리층을 잔류시키지 못하고 식각되므로 콘택홀이 텅스텐실리사이드층과 직접적으로 연결되어 폴리플러그가 형성되므로 콘택저항이 커지는 문제점을 지닌다.However, conventionally, when the Schottky contact hole is formed by a contact etching process, the etching selectivity is not good, so the cap poly layer is not etched and is etched. Therefore, the contact hole is directly connected to the tungsten silicide layer to form a poly plug so that contact resistance is increased. There is a growing problem.
이를 개선하기 위하여 콘택 식각 타겟을 줄이면, 반도체기판에 연결되는 콘택홀이 제대로 형성되지 못하는 문제를 지니고 있을 뿐만아니라 다른 해결방법으로, 캡폴리층의 두께를 높일 수 있으나, 이 방법은 이후 메탈 콘택인 오믹 콘택을 형성하는 경우, 저항을 개선하기 위하여 캡폴리층을 제거해야 하므로 콘택 식각시, 타겟을 높여야 하므로 반도체기판의 손실에 큰 영향을 미치는 문제점을 지닌다.In order to improve this, reducing the contact etch target not only has a problem that the contact holes connected to the semiconductor substrate are not formed properly, but as another solution, it is possible to increase the thickness of the cap poly layer. In the case of forming the ohmic contact, since the cap poly layer needs to be removed to improve the resistance, the target has to be increased during the etching of the contact.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판에 게이트를 형성한 후, 층간절연막을 적층하고, 마스킹식각으로 게이트의 마스크산화막을 식각하면서 캡폴리층을 노출시켜 콘택홀을 형성할 때, 펄스 모듈레이션(Pulse Modulation)을 사용하여 콘택홀을 형성하므로 식각 선택비를 높일 수 있어서 캡폴리층에 손실이 발생되는 것을 방지하는 것이 목적이다.The present invention has been made in view of the above, and when forming a contact hole by forming a gate on a semiconductor substrate and then stacking an interlayer insulating film and exposing a cap poly layer while etching a mask oxide film of the gate by masking etching, Since the contact hole is formed using pulse modulation, the etching selectivity can be increased, thereby preventing the loss of the cap poly layer.
도 1 내지 도 4는 본 발명에 따른 반도체소자의 콘택홀 형성방법을 순차적으로 보인 도면이다.1 to 4 are views sequentially showing a method for forming a contact hole in a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 게이트산화막10: semiconductor substrate 15: gate oxide film
20 : 도핑된 폴리실리콘층 25 : 텅스텐실리사이드층20 doped polysilicon layer 25 tungsten silicide layer
30 : 캡폴리층 35 : 마스크산화막30: cap poly layer 35: mask oxide film
40 : 스페이서막 45 : 층간절연막40 spacer film 45 interlayer insulating film
50 : 콘택마스크 55 : 콘택홀50: contact mask 55: contact hole
60 : 폴리실리콘층 A : 게이트60: polysilicon layer A: gate
이러한 목적은 반도체기판 상에 게이트산화막, 도핑된 폴리실리콘층, 텅스텐실리사이드층, 캡폴리층 및 마스크산화막을 적층하여 식각한 후, 측면에 스페이서막을 적층하여 게이트를 형성하는 단계와; 상기 결과물 상에 층간절연막을 적층하여 콘택홀이 형성될 부위를 개방하는 콘택마스크를 적층하는 단계와; 상기 단계 후에 CHF3/CF2혼합가스와 펄스 모듈레이션(Pulse Modulation)으로 플라즈마를 발생하여 게이트의 캡폴리층이 노출되도록 콘택홀을 식각하는 단계를 포함하여 이루어진반도체소자의 콘택홀 형성방법을 제공함으로써 달성된다.This object is achieved by laminating a gate oxide film, a doped polysilicon layer, a tungsten silicide layer, a cap poly layer, and a mask oxide film on a semiconductor substrate and etching the same, and then forming a gate by laminating a spacer film on a side surface thereof; Stacking a contact mask that opens an area where a contact hole is to be formed by stacking an interlayer insulating film on the resultant; By providing a method for forming a contact hole in a semiconductor device comprising the step of etching the contact hole so that the cap poly layer of the gate is exposed by generating a plasma by CHF 3 / CF 2 mixed gas and the pulse modulation after the step Is achieved.
그리고, 상기 캡폴리층의 두께는 200 ∼ 400Å인 것이 바람직 하다.And it is preferable that the thickness of the said cap poly layer is 200-400 Pa.
상기 펄스 모듈레이션으로 발생되는 프라즈마는 ICP/TCP 타입을 사용하도록 한다.The plasma generated by the pulse modulation is to use the ICP / TCP type.
상기 CHF3/CF2혼합가스의 비율은 50 : 50의 비율로 사용하는 것이 바람직 하다.The ratio of the CHF 3 / CF 2 mixed gas is preferably used in a ratio of 50:50.
상기 펄스 모듈레이션은, 500 ∼ 1000Watt의 소오스가스와, 50 ∼ 100㎲의 모듈레이션 주기와, 50%의 듀티 비율(Duty Ratio ; Defined as the ratio RF on time to modulation Period)로 진행하는 것이 바람직 하다.The pulse modulation preferably proceeds with a source gas of 500 to 1000 Watts, a modulation period of 50 to 100 Hz, and a Duty Ratio (Defined as the ratio RF on time to modulation Period) of 50%.
상기 콘택홀을 형성할 때, 갭폴리층과의 선택비가 40 ∼ 50 : 1 인 것이 바람직 하다.When forming the said contact hole, it is preferable that the selectivity with a gap poly layer is 40-50: 1.
상기 콘택홀의 형성시, CF 및 CF2등의 레디컬 밀도(Radical Density)를 증가시켜 선택비를 증대시키는 것이 바람직 하다.In the formation of the contact hole, it is preferable to increase the ratio by increasing the radical density of CF and CF 2 .
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1에 도시된 바와 같이, 반도체기판 (10)상에 게이트산화막(15), 도핑된 폴리실리콘층(20), 텅스텐실리사이드층(25), 캡폴리층(30) 및 마스크산화막(35)을 적층하여 식각한다, 그리고, 상기 결과물의 측면 부위에 산화막을 적층한 후, 블랭킷식각(Blancket Etch)으로 스페이서막(40)을 형성하여 게이트(A)를 형성하도록한다.As shown in FIG. 1, a gate oxide film 15, a doped polysilicon layer 20, a tungsten silicide layer 25, a cap poly layer 30, and a mask oxide film 35 are formed on a semiconductor substrate 10. After laminating and etching, the oxide film is laminated on the side surface of the resultant, and then the spacer film 40 is formed by blanket etching to form the gate A. FIG.
상기 캡폴리층(30)의 두께는 200 ∼ 400Å인 것이 바람직 하다.It is preferable that the thickness of the said cap poly layer 30 is 200-400 Pa.
도 2에 도시된 바와 같이, 상기 결과물 상에 층간절연막(45)을 적층하여 콘택홀이 형성될 부위를 개방하는 콘택마스크(50)를 적층하도록 한다.As shown in FIG. 2, an interlayer insulating layer 45 is stacked on the resultant to stack a contact mask 50 that opens a portion where a contact hole is to be formed.
도 3에 도시된 바와 같이, 상기 단계 후에 CHF3/CF2혼합가스와 펄스 모듈레이션으로 플라즈마를 발생하여 게이트(A)의 캡폴리층(30)이 노출되도록 콘택홀(55)을 식각하도록 한다.As shown in FIG. 3, after the step, plasma is generated by the CHF 3 / CF 2 mixed gas and pulse modulation to etch the contact hole 55 to expose the cap poly layer 30 of the gate A. Referring to FIG.
상기 펄스 모듈레이션으로 발생되는 프라즈마는 ICP/TCP 타입을 사용할 수 있다.The plasma generated by the pulse modulation may use an ICP / TCP type.
상기 CHF3/CF2혼합가스의 비율은 50 : 50의 비율로 사용하도록 한다.The ratio of the CHF 3 / CF 2 mixed gas is to be used in a ratio of 50:50.
상기 펄스 모듈레이션은, 500 ∼ 1000Watt의 소오스파워와, 50 ∼ 100㎲의 모듈레이션 주기와, 50%의 듀티 비율로 진행하는 것이 바람직 하다.It is preferable that the pulse modulation proceeds at a source power of 500 to 1000 Watts, a modulation period of 50 to 100 Hz, and a duty ratio of 50%.
상기 콘택홀(55)을 형성할 때, 갭폴리층(30)과의 선택비가 40 ∼ 50 : 1 인 것이 바람직 하다.When the contact hole 55 is formed, the selectivity with the gap poly layer 30 is preferably 40 to 50: 1.
상기 콘택홀(55)의 형성시, CF 및 CF2등의 레디컬 밀도를 증가시켜 선택비를 증대시키도록 한다.When the contact hole 55 is formed, radical density such as CF and CF 2 is increased to increase the selectivity.
도 4에 도시된 바와 같이, 상기 단계 후에 잔류된 콘택마스크(50)을 제거한 후, 콘택홀(55) 내에 폴리실리콘층(60)을 매립하도록 한다.As shown in FIG. 4, after removing the contact mask 50 remaining after the step, the polysilicon layer 60 is buried in the contact hole 55.
그리고, 후속 공정으로 상기 폴리실리콘층(60)의 불필요한 부분을 식각으로제거하여 플러그(Plug)를 형성하도록 한다.Subsequently, an unnecessary portion of the polysilicon layer 60 is removed by etching to form a plug.
상기한 바와 같이, 본 발명에 따른 반도체소자의 콘택홀 형성방법을 이용하게 되면, 반도체기판에 게이트를 형성한 후, 층간절연막을 적층하고, 마스킹식각으로 게이트의 마스크산화막을 식각하면서 캡폴리층을 노출시켜 콘택홀을 형성할 때, 펄스 모듈레이션(Pulse Modulation)을 사용하여 콘택홀을 형성하므로 식각 선택비를 높일 수 있어서 캡폴리층에 손실이 발생되는 것을 방지하므로 콘택홀 내에 형성되는 콘택플러그의 콘택저항(Contact Resistance)을 감소하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the method for forming a contact hole in a semiconductor device according to the present invention is used, after forming a gate on a semiconductor substrate, an interlayer insulating film is laminated, and a cap poly layer is formed by etching a mask oxide film of the gate by masking etching. When forming a contact hole by exposing it, a contact hole is formed using pulse modulation to increase the etch selectivity, thereby preventing the loss of the cap poly layer, thereby forming a contact plug contact formed in the contact hole. It is a very useful and effective invention for reducing the resistance (Contact Resistance).
Claims (7)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990065199A KR100355606B1 (en) | 1999-12-29 | 1999-12-29 | Method For Forming The Contact Hole Of Semiconductor Device |
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| KR1019990065199A KR100355606B1 (en) | 1999-12-29 | 1999-12-29 | Method For Forming The Contact Hole Of Semiconductor Device |
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