KR20020046041A - Method for forming a contact hole of a semiconductor device - Google Patents
Method for forming a contact hole of a semiconductor device Download PDFInfo
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- KR20020046041A KR20020046041A KR1020000075533A KR20000075533A KR20020046041A KR 20020046041 A KR20020046041 A KR 20020046041A KR 1020000075533 A KR1020000075533 A KR 1020000075533A KR 20000075533 A KR20000075533 A KR 20000075533A KR 20020046041 A KR20020046041 A KR 20020046041A
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- forming
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- insulating film
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- hard mask
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 77
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 4
- 229910019044 CoSix Inorganic materials 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910008486 TiSix Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- Microelectronics & Electronic Packaging (AREA)
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- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 비트 라인을 포함한 전면에 질화막을 형성한 후 층간 산화막을 형성하여 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device in which a nitride film is formed on an entire surface including a bit line and an interlayer oxide film is formed to improve the yield and reliability of the device.
종래의 반도체 소자의 콘택홀 형성 방법은 도 1a에서와 같이, 절연막(12)에 의해 절연된 하부 구조물(11)상에 텅스텐(W)층(13a), 하드 마스크(Hard mask)층(14) 및 제 1 감광막(15)을 순차적으로 형성한다.In the conventional method of forming a contact hole in a semiconductor device, as illustrated in FIG. 1A, a tungsten (W) layer 13a and a hard mask layer 14 are disposed on a lower structure 11 insulated by an insulating layer 12. And the first photosensitive film 15 are sequentially formed.
그리고, 제 1 감광막(15)을 비트 라인이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.Then, the first photosensitive film 15 is selectively exposed and developed so as to remain only at the portion where the bit line is to be formed.
도 1b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(15)을 마스크로 상기 하드 마스크층(14)과 텅스텐층(13a)을 선택 식각한 후, 상기 제 1 감광막(15)을 제거한다.As shown in FIG. 1B, the hard mask layer 14 and the tungsten layer 13a are selectively etched using the selectively exposed and developed first photosensitive layer 15 as a mask, and then the first photosensitive layer 15 is removed. do.
여기서, 상기 텅스텐층(13a)의 선택 식각 공정으로 다수개의 비트 라인(13)들을 형성한다.Here, a plurality of bit lines 13 are formed by a selective etching process of the tungsten layer 13a.
도 1c에서와 같이, 상기 비트 라인(13)들을 포함한 전면에 층간 산화막(16)을 형성한다.As shown in FIG. 1C, an interlayer oxide layer 16 is formed on the entire surface including the bit lines 13.
여기서, 상기 층간 산화막(16)을 에이치디피(High Density Plasma: HDP) 산화막으로 형성한다.The interlayer oxide layer 16 is formed of an HDP oxide layer.
도 1d에서와 같이, 상기 층간 산화막(16)상에 제 2 감광막(17)을 도포한 다음, 상기 제 2 감광막(17)을 캐패시터의 하부전극 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 1D, a second photoresist layer 17 is applied onto the interlayer oxide layer 16, and then the second photoresist layer 17 is selectively exposed and developed to remove only the portion where the lower electrode contact of the capacitor is to be formed. do.
여기서, 상기 선택적으로 노광 및 현상된 제 2 감광막(17)은 라안 타입(Line type) 자기정렬 콘택 마스크(Mask) 역할을 한다.Here, the selectively exposed and developed second photoresist layer 17 serves as a Raan type self-aligned contact mask.
도 1e에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(17)을 마스크로 상기 층간 산화막(16)과 절연막(12)을 선택 식각하여 다수개의 라인(Line) 형태의 콘택홀들을 형성한 후, 상기 제 2 감광막(17)을 제거한다.As shown in FIG. 1E, the interlayer oxide layer 16 and the insulating layer 12 are selectively etched using the selectively exposed and developed second photoresist layer 17 to form a plurality of line-type contact holes. After that, the second photosensitive film 17 is removed.
도 1f에서와 같이, 상기 콘택홀들을 포함한 전면에 산화막을 형성하고, 에치백(Etch-back) 공정을 진행하여 상기 하드 마스크층(14)을 포함한 비트 라인(13) 양측의 하부 구조물(11)상에 산화막 스페이서(18)를 형성한다.As shown in FIG. 1F, an oxide film is formed on the entire surface including the contact holes, and an etch-back process is performed to form the lower structures 11 on both sides of the bit line 13 including the hard mask layer 14. An oxide film spacer 18 is formed on the substrate.
그러나 종래의 반도체 소자의 콘택홀 형성 방법은 비트 라인을 포함한 전면에 층간 산화막을 형성하기 때문에 다음과 같은 이유에 의해 소자의 수율 및 신뢰성을 향상시키는 문제점이 있었다.However, in the conventional method of forming a contact hole in a semiconductor device, since the interlayer oxide film is formed on the entire surface including the bit line, there is a problem of improving the yield and reliability of the device for the following reasons.
첫째, 후속 공정 중 열처리 공정시 상기 비트 라인과 층간 산화막간의 반응을 일으켜 전도물질의 특성이 변하거나 텅스텐 산화막이 발생하는 등 전기적 페일(Fail)이 발생한다.First, during a heat treatment process in a subsequent process, a reaction occurs between the bit line and the interlayer oxide film, so that an electrical fail occurs, such as a change in the properties of the conductive material or a tungsten oxide film.
둘째, 자기정렬 콘택 공정시 상기 비트 라인의 하드 마스크층이 제거된다.Second, the hard mask layer of the bit line is removed during the self-aligned contact process.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 비트 라인을 포함한 전면에 질화막을 형성한 후 층간 산화막을 형성하여 후속 공정 중 열처리 공정시 상기 비트 라인과 층간 산화막간의 반응을 억제하고 자기정렬 콘택 공정시 상기 비트 라인의 하드 마스크층이 제거되는 것을 방지하는 반도체 소자의 콘택홀 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems to form a nitride film on the entire surface including the bit line and then to form an interlayer oxide film to suppress the reaction between the bit line and the interlayer oxide film during the heat treatment step of the subsequent process and self-aligned contact process An object of the present invention is to provide a method for forming a contact hole in a semiconductor device to prevent the hard mask layer of the bit line from being removed.
도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 콘택홀 형성 방법을 나타낸 공정 사시도1A to 1F are process perspective views illustrating a method for forming a contact hole in a semiconductor device according to the prior art;
도 2a 내지 도 2g는 본 발명의 실시 예에 따른 반도체 소자의 콘택홀 형성 방법을 나타낸 공정 사시도2A to 2G are process perspective views illustrating a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 31: 하부 구조물12, 32: 절연막11, 31: substructure 12, 32: insulating film
13, 33: 비트 라인 14, 34: 하드 마스크층13, 33: bit lines 14, 34: hard mask layer
15, 35: 제 1 감광막36: 제 2 질화막15, 35: first photosensitive film 36: second nitride film
16, 37: 층간 산화막 17, 38: 제 2 감광막16, 37: interlayer oxide film 17, 38: second photosensitive film
18, 39: 산화막 스페이서18, 39: oxide spacer
본 발명의 반도체 소자의 콘택홀 형성 방법은 하부 구조물이 구비되는 제 1 절연막 상에 하드 마스크층이 구비되는 도전 배선을 형성하는 단계, 상기 도전 배선을 포함한 전면에 제 2 절연막을 형성하는 단계, 상기 제 2 절연막 상에 상기 제 2 절연막과 식각 선택비를 갖는 층간 절연막을 형성하는 단계, 상기 층간 절연막, 제 2 절연막 및 제 1 절연막을 상기 도전 배선에 직교방향으로 자기정렬 콘택 식각하여 다수개의 라인 형태의 콘택홀을 형성하는 단계 및 상기 하드 마스크층을 포함한 도전 배선 양측의 하부 구조물상에 상기 제 2 절연막과 식각 선택비를 갖는 제 3 절연막 스페이서를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a contact hole in a semiconductor device according to the present invention may include forming a conductive wiring having a hard mask layer on a first insulating film having a lower structure, forming a second insulating film on the entire surface including the conductive wiring. Forming an interlayer insulating layer having an etch selectivity with the second insulating layer on the second insulating layer; And forming a contact hole of the third insulating film spacer having an etch selectivity with the second insulating film on the lower structures on both sides of the conductive wiring including the hard mask layer.
상기와 같은 본 발명에 따른 반도체 소자의 콘택홀 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method for forming a contact hole in a semiconductor device according to the present invention as described above will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시 예에 따른 반도체 소자의 콘택홀 형성 방법을 나타낸 공정 사시도이다.2A to 2G are process perspective views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
본 발명의 실시 예에 따른 반도체 소자의 콘택홀 형성 방법은 도 1a에서와 같이, 절연막(32)에 의해 절연된 하부 구조물(31)상에 텅스텐층(33a), 하드 마스크층(34) 및 제 1 감광막(35)을 순차적으로 형성한다.In the method of forming a contact hole in a semiconductor device according to an embodiment of the present invention, a tungsten layer 33a, a hard mask layer 34, and a second layer may be formed on a lower structure 31 insulated from an insulating layer 32, as shown in FIG. 1A. 1 Photosensitive film 35 is formed sequentially.
그리고, 제 1 감광막(35)을 비트 라인이 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.Then, the first photosensitive film 35 is selectively exposed and developed so as to remain only at the portion where the bit line is to be formed.
여기서, 상기 텅스텐층(33a) 대신에 WSix층, TiSix층, CoSix층, 알루미늄(Al)층 및 구리(Cu)층 등으로 형성할 수 있다.Here, the tungsten layer 33a may be formed of a WSix layer, a TiSix layer, a CoSix layer, an aluminum (Al) layer, a copper (Cu) layer, or the like.
상기 하드 마스크층(34)을 500 ∼ 5000Å의 두께로 형성한다.The hard mask layer 34 is formed to a thickness of 500 to 5000 kPa.
도 2b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(35)을 마스크로 상기 하드 마스크층(34)과 텅스텐층(33a)을 선택 식각한 후, 상기 제 1 감광막(35)을 제거한다.As shown in FIG. 2B, the hard mask layer 34 and the tungsten layer 33a are selectively etched using the selectively exposed and developed first photosensitive layer 35 as a mask, and then the first photosensitive layer 35 is removed. do.
여기서, 상기 텅스텐층(33a)의 선택 식각 공정으로 다수개의 비트 라인(33)들을 형성한다.Here, a plurality of bit lines 33 are formed by a selective etching process of the tungsten layer 33a.
도 2c에서와 같이, 상기 비트 라인(33)들을 포함한 전면에 50 ∼ 300Å두께의 제 2 질화막(36)을 형성한다.As shown in FIG. 2C, a second nitride film 36 having a thickness of 50 to 300 μs is formed on the entire surface including the bit lines 33.
여기서, 상기 제 2 질화막(36) 대신에 SiON 또는 알루미나층으로 형성할 수 있다.In this case, the SiN or alumina layer may be formed instead of the second nitride layer 36.
도 2d에서와 같이, 상기 제 2 질화막(36)상에 층간 산화막(37)을 형성한다.As shown in FIG. 2D, an interlayer oxide film 37 is formed on the second nitride film 36.
여기서, 상기 층간 산화막(37)을 500 ∼ 10000Å의 두께로 형성한다.Here, the interlayer oxide film 37 is formed to a thickness of 500 to 10000 kPa.
도 2e에서와 같이, 상기 층간 산화막(37)상에 제 2 감광막(38)을 도포한 다음, 상기 제 2 감광막(38)을 상기 비트 라인(33)에 직교 방향인 캐패시터의 하부전극 콘택이 형성될 부위에만 제거되도록 선택적으로 노광 및 현상한다.As shown in FIG. 2E, a second photosensitive film 38 is applied on the interlayer oxide film 37, and then the second electrode photosensitive film 38 is formed with a lower electrode contact of a capacitor orthogonal to the bit line 33. It is selectively exposed and developed to be removed only in the area to be removed.
여기서, 상기 선택적으로 노광 및 현상된 제 2 감광막(38)은 라인 타입 자기정렬 콘택 마스크 또는 T 타입 자기정렬 콘택 마스크 및 I 타입 자기정렬 콘택 마스크 중 하나의 마스크 역할을 한다.Here, the selectively exposed and developed second photosensitive film 38 serves as a mask of one of a line type self-aligned contact mask or a T type self-aligned contact mask and an I type self-aligned contact mask.
도 2f에서와 같이, 상기 선택적으로 노광 및 현상된 제 2 감광막(38)을 마스크로 상기 층간 산화막(37), 제 2 질화막(36) 및 절연막(32)을 자기정렬 콘택 공정으로 선택 식각하여 다수개의 라인 형태의 콘택홀들을 형성한 후, 상기 제 2 감광막(38)을 제거한다.As shown in FIG. 2F, the interlayer oxide film 37, the second nitride film 36, and the insulating film 32 are selectively etched by using the selectively exposed and developed second photoresist film 38 by a self-aligned contact process. After forming two line contact holes, the second photoresist layer 38 is removed.
여기서, 상기 자기정렬 콘택 공정은 에이치디피(High Density Plasma: HDP) 식각 반응기 또는 엠디피(Middle Density Plasma: MDP) 식각 반응기를 사용하여 1 ∼ 100mT 압력으로 진행한다.Here, the self-aligned contact process may be performed at a pressure of 1 to 100 mT using a High Density Plasma (HDP) etching reactor or a Middle Density Plasma (MDP) etching reactor.
그리고, 상기 자기정렬 콘택 공정은 상기 하드 마스크층(34)을 질화막 계열의 절연막으로 형성하고 상기 층간 산화막(37)을 HDP 산화막과 같은 산화막 계열의 절연막으로 형성할 경우 Ar/C4F8/CH2F2/, Ar/C4F8/O2, Ar/C4F8/CH3F, Ar/C4F8/CHF3및 Ar/C5F8/O2중 하나의 가스 화합물과 상기 가스 화합물의 다른 조합으로 식각한다.In the self-aligned contact process, when the hard mask layer 34 is formed of an nitride film-based insulating film, and the interlayer oxide film 37 is formed of an oxide film-based insulating film such as an HDP oxide film, Ar / C 4 F 8 / CH Gas compound of one of 2 F 2 /, Ar / C 4 F 8 / O 2 , Ar / C 4 F 8 / CH 3 F, Ar / C 4 F 8 / CHF 3 and Ar / C 5 F 8 / O 2 And other combinations of the gas compounds.
또한, 상기 자기정렬 콘택 공정은 상기 하드 마스크층(34)을 산화막 계열의 절연막으로 형성하고 상기 층간 산화막(37)을 폴리머(Polymer) 계열의 절연막으로 형성할 경우 Ar/O2/N2/H2/CH4/C2H4/CxFy가스 화합물의 조합으로 식각한다.In the self-aligning contact process, when the hard mask layer 34 is formed of an oxide film-based insulating film and the interlayer oxide film 37 is formed of a polymer-based insulating film, Ar / O 2 / N 2 / H Etch with a combination of 2 / CH 4 / C 2 H 4 / C x F y gas compounds.
도 2g에서와 같이, 상기 콘택홀들을 포함한 전면에 산화막을 형성하고, 에치백 공정을 진행하여 상기 하드 마스크층(34)을 포함한 비트 라인(33) 양측의 하부 구조물(31)상에 산화막 스페이서(39)를 형성한다.As shown in FIG. 2G, an oxide film is formed on the entire surface including the contact holes, and an etch back process is performed to form an oxide spacer on the lower structure 31 on both sides of the bit line 33 including the hard mask layer 34. 39).
여기서, 상기 산화막 대신에 유전 상수가 낮은 절연막으로 형성할 수 있으며, 상기 산화막 스페이서(39)를 50 ∼ 500Å의 두께로 형성한다.Here, instead of the oxide film, an insulating film having a low dielectric constant can be formed, and the oxide film spacer 39 is formed to a thickness of 50 to 500 kV.
상기 산화막 스페이서(39) 형성 공정 대신에 상기 자기정렬 콘택 공정시 상기 비트 라인(33) 측면으로 슬로프(Slope)가 발생하도록 하여 상기 비트 라인(33) 측면으로 자연적인 산화막 스페이서를 형성할 수 있다.Instead of forming the oxide spacer 39, a slope may be generated at the side of the bit line 33 during the self-aligned contact process to form a natural oxide spacer at the side of the bit line 33.
본 발명의 반도체 소자의 콘택홀 형성 방법은 비트 라인을 포함한 전면에 질화막을 형성한 후 층간 산화막을 형성하므로, 후속 공정 중 열처리 공정시 상기 비트 라인과 층간 산화막간의 반응을 억제하여 전기적 페일(Fail) 발생을 방지하고 자기정렬 콘택 공정시 상기 비트 라인의 하드 마스크층이 제거되는 것을 방지하여 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the method for forming a contact hole in the semiconductor device of the present invention, since an interlayer oxide film is formed after a nitride film is formed on the entire surface including the bit line, an electrical fail is prevented by suppressing a reaction between the bit line and the interlayer oxide film during a heat treatment process in a subsequent process. There is an effect of preventing the occurrence and the removal of the hard mask layer of the bit line during the self-aligned contact process to improve the yield and reliability of the device.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100866123B1 (en) * | 2002-07-15 | 2008-10-31 | 주식회사 하이닉스반도체 | Bit line forming method of semiconductor device |
| KR100925026B1 (en) * | 2002-12-11 | 2009-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR101016334B1 (en) * | 2003-07-18 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of forming gate electrode in semiconductor device |
| CN111293075A (en) * | 2018-12-06 | 2020-06-16 | 南亚科技股份有限公司 | Method for forming precision interconnection of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100518527B1 (en) * | 1999-03-24 | 2005-10-04 | 삼성전자주식회사 | Manufacturing method of semiconductor device having low resistance gate electrode |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100866123B1 (en) * | 2002-07-15 | 2008-10-31 | 주식회사 하이닉스반도체 | Bit line forming method of semiconductor device |
| KR100925026B1 (en) * | 2002-12-11 | 2009-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| KR101016334B1 (en) * | 2003-07-18 | 2011-02-22 | 매그나칩 반도체 유한회사 | Method of forming gate electrode in semiconductor device |
| CN111293075A (en) * | 2018-12-06 | 2020-06-16 | 南亚科技股份有限公司 | Method for forming precision interconnection of semiconductor device |
| CN111293075B (en) * | 2018-12-06 | 2022-07-12 | 南亚科技股份有限公司 | Method for forming precision interconnection of semiconductor device |
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