KR100340899B1 - Method of forming a silicide layer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicide layer, and in particular, by further doping a silicide layer formed on a polysilicon layer with impurity ions to reduce the resistivity of the silicide layer itself, A method of forming a silicide layer having a polyside structure of a semiconductor device in which a top surface and a bottom surface of each silicide layer is doped with impurity ions to reduce contact resistance between the first polyside and the second polyside. The silicide layer forming method according to the present invention comprises forming a polysilicon layer doped with an impurity on a substrate, and forming SiH ₂ Cl ₂ gas and PH ₃ gas by pyrolysing at high temperature on the polysilicon layer to form silicon and phosphorus. A first step of forming a gas atmosphere comprising a second step of forming a first silicide layer doped with phosphorus and enriched with silicon on the polysilicon layer under the gas atmosphere at a first thickness, and the first silicide A third step of forming a second silicide layer on the layer to a second thickness, a fourth step of bringing the surface of the second silicide layer into the phosphorus-doped and silicon-rich state, the polysilicon layer, the And heat-treating the first and second silicide layers.

Description

Silicide layer formation method {METHOD OF FORMING A SILICIDE LAYER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicide layer, and in particular, by further doping a silicide layer formed on a polysilicon layer with impurity ions to reduce the resistivity of the silicide layer itself, A method of forming a silicide layer having a polyside structure of a semiconductor device in which a top surface and a bottom surface of each silicide layer is doped with impurity ions to reduce contact resistance between the first polyside and the second polyside.

As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance of a gate.

Therefore, when the wirings of the elements in the semiconductor device are formed of a low resistance material such as aluminum alloy and tungsten, or when the gate electrode is formed of polysilicon, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polycrystalline silicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.

As described above, as the design rule of the semiconductor device becomes more strict, the high resistance at the gate becomes a major cause of lowering the operation speed of the device. Therefore, fabrication of the low resistance gate electrode is essential for improving the device operation speed. In order to improve the resistance, a gate electrode having a silicide (refractory metal silicide) formed of a heat resistant metal having a low specific resistance is manufactured. The gate electrode having such a structure is called a polycide (silicide on doped polycrystalline silicon) gate electrode.

The most widely used for the formation of polyside structures is WSi ₂ . As the integration of devices increases and the area occupied by unit devices decreases, formation of silicides having lower resistance values is required. At this time, the specific resistance value of WSi2 is 60-200 micrometer-cm.

The method of forming a polyside structure can be broadly divided into two methods.

First, a metal layer is deposited on a conductive doped polysilicon layer and then heat-treated to form silicide by reaction of metal and silicon. However, the silicide of the metal-silicon formed at this time is difficult to form a silicide layer having a thick and uniform thickness.

Second, there is a method of depositing a silicide material directly on a conductive doped polysilicon layer instead of a thermal process. In general, a silicide layer is directly formed on a polysilicon layer doped by a sputtering method using a silicide composite target.

WSi _x silicide using SiH ₂ Cl ₂ according to the prior art is formed by chemical vapor deposition using SiH ₂ Cl ₂ and WF ₆ , wherein the chemical reaction takes place as follows.

SiH ₂ Cl ₂ + WF ₆ → WSi _x + HF + by-product

In order to proceed with this chemical reaction, the SiH ₂ Cl ₂ gas amount is increased on the polysilicon layer doped with impurity ions, and the WF ₆ gas amount is reduced to allow silicon-rich nucleation, and then the appropriate amount of SiH ₂ Cl ₂ and WF ₆ are introduced into the chamber to form the main WSi _x layer, the silicide layer.

In addition, only SiH ₂ Cl ₂ gas flows on the main WSi _x layer to enrich the silicon of the film surface, while some Si atoms penetrate the WSi _x layer to reduce the high stress generated during film deposition.

1A to 1E are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the prior art, wherein the silicide layers formed are part of a first polyside structure and a second polyside structure, respectively.

Referring to FIG. 1A, a field oxide film (not shown) is formed on a predetermined portion of a silicon substrate 10, which is a semiconductor substrate on which an interlayer insulating layer is formed, by a device isolation method such as a local oxide of silicon (LOCOS) method. A region and an element isolation region are formed.

The surface of the semiconductor substrate 10 is thermally oxidized to form a gate oxide film (not shown) as the gate insulating film.

Then, an impurity doped first polysilicon layer 11 is formed by chemical vapor deposition on the gate oxide layer to form a word line including the gate electrode, or a non-doped poly The undoped polycrystalline silicon is deposited by chemical vapor deposition and then doped by ion implantation. The polysilicon layer 11 formed as described above is patterned in a subsequent process to form a lower structure of the gate electrode and the word line.

Then, the first poly sheds the SiH ₂ Cl ₂ gas at a high temperature in the silicon layer (11). At this time, the SiH ₂ Cl ₂ gas pyrolyzed at high temperature forms a Si atmosphere on the substrate.

Then, these gases were reacted under conditions of increasing the SiH ₂ Cl ₂ amount and decreasing the WF ₆ amount under the Si atmosphere, which was formed in the already formed Si atmosphere, thereby increasing the amount of silicon-rich on the first polysilicon layer 11 ( Si rich) A seed layer (not shown) to be a WSix nucleus is formed.

Then, the SiH ₂ Cl ₂ gas and the WF ₆ gas are mixed at a predetermined ratio to form a main WSi _x (12) layer, which is the first silicide layer 12.

In addition, only SiH ₂ Cl ₂ gas flows on the first silicide layer 12 to make the surface of the first silicide layer 12 rich in silicon, thereby reducing stress generated during film formation. At this time, silicon atoms penetrate the first silicide layer 12 made of WSi _x .

The WSi _x layer thus formed is used as a material for gate lines and bit lines in devices such as DRAMs.

Referring to FIG. 1B, heat treatment such as annealing is performed on the first silicide layer and the first polysilicon layer doped with impurities such as phosphorus (P). Therefore, the phosphorus component included in the doped first polysilicon layer is diffused into the first silicide layer by the concentration difference from WSix.

As a result, the doping concentration of the first polysilicon layer 110 decreases, and the first polyside structure in which the specific resistance of the first polysilicon layer 110 is increased by including impurities such as phosphorus in the first silicide layer 120. 110 and 120 are formed.

Next, the first silicide layer 120 and the first polysilicon layer 110 are patterned by photolithography to form a gate line.

The interlayer insulating layer 13 is formed by depositing an oxide film or the like on the first silicide layer 120 having impurity ions diffused therein, and then removing a predetermined portion by photolithography to form the patterned first silicide layer 120. The opening which exposes a predetermined site | part is formed. Subsequently, a second polyside structure, which is used as a bit line in the peripheral circuit portion, is formed in a subsequent process through an opening exposing a predetermined portion of the first polyside structure, which is a gate line.

Referring to FIG. 1C, a second doped with an impurity ion such as phosphorus (P) having a predetermined doping concentration on an interlayer insulating layer 13 including a surface of the first silicide layer 120 exposed by an opening. The polysilicon layer 14 is formed by vapor deposition by a method such as chemical vapor deposition.

Referring to FIG. 1D, SiH ₂ Cl ₂ gas is flowed on the second polysilicon layer 14 at a high temperature. At this time, the SiH ₂ Cl ₂ gas pyrolyzed at high temperature forms a Si atmosphere on the substrate.

Under the Si atmosphere already formed, these gases were reacted under conditions in which the amount of SiH ₂ Cl ₂ was increased and the amount of WF ₆ was reduced as compared with the formation of the main silicide layer, so that silicon was deposited on the second polysilicon layer 14. Si rich WSix nucleus to form a seed layer (not shown).

Next, the SiH ₂ Cl ₂ gas and the WF ₆ gas are mixed at a predetermined ratio to form a main WSi _x (15) layer, which is the second silicide layer 15.

Then, only SiH ₂ Cl ₂ gas flows on the second silicide layer 15 to make the surface of the second silicide layer 15 rich in silicon, thereby reducing stress generated during film formation. At this time, the silicon atoms penetrate into the second silicide layer 15 made of WSi _x .

The WSi _x layer thus formed is used as a material for bit lines in devices such as DRAMs.

Referring to FIG. 1E, heat treatment such as annealing is performed on the second silicide layer and the second polysilicon layer doped with impurities such as phosphorus (P). Therefore, the phosphorus component included in the doped second polysilicon layer is diffused into the first silicide layer 121 disposed under the second silicide layer and the second polysilicon layer by the concentration difference with WSix. In this case, the diffusion degree is larger than that of the first silicide layer 120 to the second silicide layer 150.

As a result, the doping concentration of the second polysilicon layer 140 is greatly reduced, and the second polysilicon in which the resistivity of the second polysilicon layer 140 is greatly increased by including impurities such as phosphorus in the second silicide layer 150. Side structures 150 and 140 are formed.

The second silicide layer 150 and the second polysilicon layer 140 are then patterned by photolithography to form bit lines.

The method of forming a polyside structure according to the prior art is used as a wiring material suitable for the trend of high integration of devices due to the low resistivity and strong thermal resistance of the WSi _x layer, compared to a structure made of only polysilicon.

However, in the device structure in which the stress of the WSi _x film produced according to the prior art is high and the contact between the first polyside and the second polyside is required, the contact resistance therebetween increases, which may cause device defects.

That is, the prior art has a problem in that the impurity doping concentration reduction of the first polysilicon layer and the second polysilicon layer increases the energy barrier level for moving electrons, thereby increasing the contact resistance.

Accordingly, an object of the present invention is to provide a silicide layer forming method having a polyside structure of a semiconductor device which further reduces the resistivity of the silicide layer itself by further doping the silicide layer formed on the polysilicon layer with impurity ions.

Another object of the present invention is to reduce the contact resistance of the first polyside and the second polyside by doping the upper surface and the lower surface of each silicide layer of the first polyside structure and the second polyside structure with impurity ions. A silicide layer forming method having a polyside structure of a semiconductor device is provided.

According to one or more exemplary embodiments, a method of forming a silicide layer may include forming a polysilicon layer doped with an impurity on a substrate, and forming a gas atmosphere made of silicon and phosphorus on the polysilicon layer. A first step, a second step of forming a silicon-rich first silicide layer having a first thickness on the polysilicon layer under the gas atmosphere, and a second silicide layer on the first silicide layer; A third step of forming a second thickness, a fourth step of making the surface of the second silicide layer doped with phosphorus and rich in silicon, the polysilicon layer, the first and second silicide layers It includes the step of performing a heat treatment.

According to another aspect of the present invention, a method of forming a silicide layer may include forming a first polysilicon layer doped with an impurity on a substrate, and doping the silicon with the impurity on the first polysilicon layer. Forming a first metal-silicide layer in this rich state, forming a second metal-silicide layer of the metal on the first metal-silicide layer, and a surface of the second metal-silicide layer Making an impurity and the silicon-rich state, annealing the first polysilicon layer, the first and second metal-silicide layers, and the first and second metal-silicide layers; Patterning the first polysilicon layer to form a first pattern, and depositing a predetermined portion of the first pattern on the substrate including the first pattern Forming an interlayer insulating layer having openings to be ejected, forming a second polysilicon layer doped with the impurity on the interlayer insulating layer including the exposed surface of the first pattern, and the second layer Forming a third metal-silicide layer doped with the impurity and enriched in silicon on the polysilicon layer, and forming a fourth metal-silicide layer made of the metal on the third metal-silicide layer Making the surface of the fourth metal-silicide layer rich in the impurities and the silicon, annealing the second polysilicon layer, the third and fourth metal-silicide layers, Patterning the third and fourth metal-silicide layers and the second polysilicon layer to form a second pattern.

1A to 1E are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the related art.

2A through 2E are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the present invention.

As devices of semiconductor devices require high integration, polysilicon structures including doped polysilicon and silicide in polysilicon doped with gate and bit line materials are used in devices such as DRAMs.

The present invention forms WSi _x based on SiH ₂ Cl ₂ to reduce the stress and contact resistance of the first and second polysides while taking advantage of the low resistivity and thermal resistance of conventional tungsten silicides. PH3 gas is used to add phosphorus into the WSix membrane.

That is, in the present invention, when the WSi _x layer, which is a silicide layer, is formed by chemical vapor deposition based on SiH ₂ Cl ₂ and WF ₆ , phosphorus is added to reduce the specific resistance and stress of the silicide layer, and 2, poly-silicon contact prevents out-diffusion of the phosphorus ion, which is a doping impurity of the polysilicon layer, into the WSi _x layer, thereby preventing an increase in contact resistance.

The present invention changes the WSi _x formation method of polysides to solve the problems of the prior art. That is, the PH ₃ gas before and after the formation over a WSi _x layer because WSi _x layer flowing on standing thereby artificially injecting the WSi _x layer on the upper surface and the lower surface.

In this case, there is also a method of forming the entire WSi _x layer of the first polyside in a silicon-rich state to facilitate diffusion of phosphorus during heat treatment in advance to lower the diffusion from the polysilicon layer of the second polyside. The method of lowering the contact resistance can be achieved only by forming the entire film quality of the polyside in the presence of abundant silicon.

The configuration and operation of the present invention has the following characteristics as compared to the deposition process of the prior art.

In a first step (SiH ₂ Cl ₂ & PH ₃ pre-flowing), SiH ₂ Cl ₂ gas and PH ₃ gas are pre-flowed onto the doped polysilicon layer. At this time, SiH ₂ Cl ₂ gas and PH ₃ gas pyrolyzed at high temperature provide a 'Si + P' atmosphere on the substrate.

In the second nucleation, a seed layer rich in phosphorus ions is formed to form WSi _x in order to grow WSi _x on the surface of the doped polysilicon layer under a 'Si + P' atmosphere. In this case, compared to the formation of the main WSi _x layer, the addition of PH ₃ gas, increasing the SiH ₂ Cl ₂ flow rate and WF ₆ flow rate is reduced to form a P-doped WSi _x film quality to a predetermined thickness.

Claim to a step _{3 (forming main WSi x layer)} , and the SiH ₂ Cl ₂ gas and WF ₆ gas at a predetermined ratio to form a main WSi _x layer. In this case, the chemical reaction is <SiH ₂ Cl ₂ + WF ₆ → WSi _x + HF + by-products>, and the WSi _x formation of the first polyside is formed to be rich in silicon to facilitate doping of phosphorus.

In the fourth step (SiH ₂ Cl ₂ & PH ₃ post-flowing), SiH ₂ Cl ₂ gas and PH ₃ gas are flowed onto the main WSi _x layer, making the surface of the main WSi _x layer phosphorus doped and silicon rich. . At this time, some silicon atoms and phosphorus atoms penetrate into the WSi _x layer and lower the stress generated during film formation.

The WSi _x layer formed by the above-described steps has the same properties as silicon-rich in the upper and lower portions of the WSi _x layer in contrast to the film quality prepared by the prior art, but the characteristics of this region are different because the state containing phosphorus is different. This phosphor has a structure similar to polysilicon doped with phosphorus.

In addition, some of the atoms is an amount of phosphorus contained in the WSi _x layer when the WSi _x layer is included in the inside, a first poly-SiH ₂ Cl ₂ / WF ₆ ratio the film quality of the WSi _x layer side formed so as to silicon is dominant Will increase.

In a semiconductor device such as a DRAM, when the first polyside structure is used as the gate line forming material and the second polyside structure is used as the bit line forming material, these lines are electrically insulated from each other in the memory cell portion, but the peripheral circuit portion In electrical contact with each other.

The principle that the contact resistance is lowered by the present invention when the two polycide structures overlap and contact is as follows.

In the structures of the doped first polysilicon layer and the first tungsten-silicide layer of the first polyside, both upper and lower surfaces of the first tungsten-silicide layer are doped with phosphorus through a heat treatment process, so that phosphorus atoms of the first polysilicon are diffused. This decreases.

Also in the second polyside structure, diffusion of doped phosphorus ions of the second polysilicon layer also occurs during the heat treatment, but the diffusion degree is greatly reduced for the same reasons as described above. In this case, when the first tungsten-silicide layer is adjusted to the SiH ₂ Cl ₂ / WF ₆ ratio to make the silicon predominate, such an effect becomes larger, thereby lowering the contact resistance between the first polyside and the second polyside. Can be.

This can lower the contact resistance between polysides by significantly lowering the energy barrier level for moving electrons compared to the prior art.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the present invention, in which a contact portion between a first polyside used as a gate line in a DRAM and a second polyside used as a bit line is closed. -The drawing is upset.

Referring to FIG. 2A, a field oxide film (not shown) is formed on a predetermined portion of a silicon substrate 20, which is a semiconductor substrate on which an interlayer insulating layer is formed, by a device isolation method such as a local oxide of silicon (LOCOS) method. A region and an element isolation region are formed.

The surface of the semiconductor substrate 20 is thermally oxidized to form a gate oxide film (not shown) as the gate insulating film.

Subsequently, in order to form a gate line including a gate electrode, a first polysilicon layer 21 doped with an impurity such as phosphorus on the gate oxide layer 21 is chemical vapor deposition (CVD). It is formed by evaporation or doped by depositing an undoped polycrystalline silicon layer by chemical vapor deposition and then ion implantation. The first polysilicon layer 21 formed as described above is patterned in a subsequent process to form a lower structure of the gate electrode and the word line of the first polyside structure.

Then, the first poly sheds the SiH ₂ Cl ₂ gas and PH ₃ gas at a high temperature in the silicon layer 21. At this time, the SiH ₂ Cl ₂ gas and the PH ₃ gas pyrolyzed at high temperature form a 'Si + P' atmosphere on the substrate.

And, under the 'Si + P' atmosphere already formed, these gases are reacted under the condition of adding a PH ₃ gas, increasing the amount of SiH ₂ Cl ₂ and decreasing the amount of WF ₆ as compared with the formation of the main silicide layer to be formed later. To form a silicon-rich lower WSi _x film (a1 portion) on the first polysilicon layer 21.

Then, the SiH ₂ Cl ₂ gas and the WF ₆ gas are mixed at a ratio to flow on the substrate to form a main WSi _x layer (part between a1 and a2). At this time, the chemical reaction is <SiH ₂ Cl ₂ + WF ₆ → WSi _x + HF + by-products>, and the WSi _x formation of the first polyside may be formed to be rich in silicon to facilitate doping of phosphorus. In addition, the electrical conductivity of the overall WSi _x layer is improved because of the phosphorus doped in the main WSi _x layer.

The SiH ₂ Cl ₂ gas and the PH ₃ gas are then flowed onto the main WSi _x layer to form an upper WSi _x film a2 having a phosphorus doped and silicon rich state. At this time, some silicon atoms and phosphorus atoms penetrate into the main WSi _x layer and lower the stress generated during film formation.

Thus, a first WSi _x layer 22 is formed, which is a first silicide layer 22 composed of a lower WSix film / main WSix layer / upper WSix film and mainly doped with phosphorus at its upper and lower surfaces.

The WSi _x layer thus formed is used as a gate line material in devices such as DRAM.

Referring to FIG. 2B, annealing or the like is performed on the first silicide layer and the first polysilicon layer doped with impurities such as phosphorus (P). Therefore, due to phosphorus ions doped on the upper and lower surfaces of the first silicide layer, the phosphorus component included in the first polysilicon layer is hardly diffused into the first silicide layer since the concentration difference with WSix is small.

As a result, since the doping concentration of the first polysilicon layer 210 after the heat treatment is almost maintained, the increase in specific resistance is prevented, and impurities such as phosphorus are included in the first silicide layer 220, so that the electrical conductivity of the first silicide layer is increased. Is increased to form the first polyside structures 210 and 220 with lower overall resistance.

Next, the first silicide layer 220 and the first polysilicon layer 210 are patterned by photolithography to form a gate line.

An interlayer insulating layer 23 is formed by depositing an oxide film or the like on the first silicide layer 220, and then removing a predetermined portion by photolithography to expose a predetermined portion of the patterned first silicide layer 220. Form an opening. Subsequently, a second polyside structure, which is used as a bit line in the peripheral circuit portion, is formed in a subsequent process through an opening exposing a predetermined portion of the first polyside structure, which is a gate line.

Referring to FIG. 2C, a second doped with impurity ions such as phosphorous (P) having a predetermined doping concentration on the interlayer insulating layer 23 including the surface of the first silicide layer 220 exposed by the opening. The polysilicon layer 24 is formed by evaporation by chemical vapor deposition or the like.

Then, the second poly sheds the SiH ₂ Cl ₂ gas and PH ₃ gas at a high temperature in the silicon layer 24. At this time, the thermal decomposition at high temperatures, SiH ₂ Cl ₂ gas and PH ₃ gas are 'Si + P on the substrate Reshaping the atmosphere.

And, under the 'Si + P' atmosphere already formed, these gases are reacted under the condition of adding a PH ₃ gas, increasing the amount of SiH ₂ Cl ₂ and decreasing the amount of WF ₆ as compared with the formation of the main silicide layer to be formed later. To form a silicon rich lower WSi _x film (a3 portion) on the second polysilicon layer 24.

Then, the SiH ₂ Cl ₂ gas and the WF ₆ gas are mixed at a ratio to flow on the substrate to form a main WSi _x layer (part between a3 and a4). At this time, the chemical reaction is <SiH ₂ Cl ₂ + WF ₆ → WSi _x + HF + by-products>, and the WSi _x formation of the second polyside may be formed to be rich in silicon to facilitate doping of phosphorus. In addition, the electrical conductivity of the overall WSi _x layer is improved because of the phosphorus doped in the main WSi _x layer.

Then, SiH ₂ Cl ₂ gas and PH ₃ gas are flowed on the main WSi _x layer to make a part of the main WSix layer into the upper WSi _x film a4 having a phosphorus doped and silicon rich state. At this time, some silicon atoms and phosphorus atoms penetrate into the main WSi _x layer and lower the stress generated during film formation.

Thus, a second WSi _x layer 25 is formed, which is a second silicide layer 25 composed of a lower WSix film / main WSix layer / upper WSix film and mainly doped with phosphorus at its upper and lower surfaces.

The WSi _x layer thus formed is used as a material for bit lines in devices such as DRAMs.

Referring to FIG. 2D, heat treatment such as annealing is performed on the second silicide layer and the second polysilicon layer doped with impurities such as phosphorus (P). Therefore, the phosphorus component included in the second polysilicon layer 25 may have a concentration of WSi _x due to the phosphorus ion doped on the upper surface of the first silicide layer 220 and the phosphorus ion doped on the lower surface of the second silicide layer 250. Since the difference is small, it is hardly diffused into the first and second silicide layers 221 and 250.

As a result, the doping concentrations of the first and second polysilicon layers 240 and 210 after the heat treatment are maintained almost intact, so that an increase in specific resistance is prevented, and the first and second silicide layers 221 and 250 contain impurities such as phosphorus and are electrically The conductivity increases, and the contact resistance between the first silicide layer 221 and the second polysilicon layer 240 decreases, thereby forming second polyside structures 250 and 240 having low overall resistance.

The second silicide layer 250 and the second polysilicon layer 240 are then patterned by photolithography to form bit lines.

Therefore, the present invention can lower the specific resistance of the silicide since the silicide itself is doped with phosphorus. In other words, since the specific resistance of the silicide is lowered, the formation thickness of the same device can be retained, which has many advantages in the manufacturing process.

In addition, the present invention has the advantage of significantly lowering the contact resistance between the first polyside and the second polyside because the energy barrier level for moving electrons in the contact portion of the gate line and the bit line is lowered.

Claims (9)

Forming a polysilicon layer doped with an impurity on the substrate, Forming a gas atmosphere made of silicon and phosphorus by thermally decomposing SiH ₂ Cl ₂ gas and PH ₃ gas at high temperature on the polysilicon layer; Forming a first silicide layer doped with phosphorus and enriched with silicon on the polysilicon layer under the gas atmosphere to a first thickness; Forming a second silicide layer in a second thickness on the first silicide layer; A fourth step of bringing the surface of the second silicide layer into the phosphorus-doped and silicon-rich state, And heat-treating the polysilicon layer and the first and second silicide layers. delete The method according to claim 1, The first silicide layer is a method of forming a silicide layer, characterized in that the addition of PH ₃ gas, increase the SiH ₂ Cl ₂ flow rate and reduce the WF ₆ flow rate to form the WSi _x film quality doped with phosphorus. The method according to claim 1, And the second silicide layer forms a main WSi _x layer using a SiH ₂ Cl ₂ gas and a WF ₆ gas at a predetermined ratio. The method according to claim 1, In the fourth step, the SiH ₂ Cl ₂ gas and the PH ₃ gas are flowed on the main WSi _x layer to form a surface of the main WSi _x layer in the phosphorus-doped and silicon-rich state. . Forming a first polysilicon layer doped with an impurity on the substrate, Forming a first metal-silicide layer doped with the impurity and rich in silicon on the first polysilicon layer; Forming a second metal-silicide layer made of the metal on the first metal-silicide layer; Making the surface of the second metal-silicide layer rich in the impurities and the silicon; Annealing the first polysilicon layer and the first and second metal-silicide layers; Patterning the first and second metal-silicide layers and the first polysilicon layer to form a first pattern; Forming an interlayer insulating layer having an opening for exposing a predetermined portion of the first pattern on the substrate including the first pattern; Forming a second polysilicon layer doped with the impurity on the interlayer insulating layer including the exposed surface of the first pattern; Forming a third metal-silicide layer doped with the impurity and rich in silicon on the second polysilicon layer; Forming a fourth metal-silicide layer made of the metal on the third metal-silicide layer, Making the surface of the fourth metal-silicide layer rich in the impurities and the silicon; Annealing the second polysilicon layer, the third and fourth metal-silicide layers; And patterning the third and fourth metal-silicide layers and the second polysilicon layer to form a second pattern. The method according to claim 6, And said metal is tungsten and said metal-silicide layer is formed of a tungsten-silicide layer. The method according to claim 6, And the impurity is phosphorus (P). The method according to claim 6, And wherein the first pattern is a gate line of a DRAM memory device and the second pattern is a bit line of the DRAM memory device.