KR100336758B1 - Micro ball grid array package and manufacturing method thereof - Google Patents
Micro ball grid array package and manufacturing method thereof Download PDFInfo
- Publication number
- KR100336758B1 KR100336758B1 KR1019990039589A KR19990039589A KR100336758B1 KR 100336758 B1 KR100336758 B1 KR 100336758B1 KR 1019990039589 A KR1019990039589 A KR 1019990039589A KR 19990039589 A KR19990039589 A KR 19990039589A KR 100336758 B1 KR100336758 B1 KR 100336758B1
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- South Korea
- Prior art keywords
- package
- film
- chip
- copper
- insulating film
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000011806 microball Substances 0.000 title 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052802 copper Inorganic materials 0.000 claims abstract description 32
- 239000010949 copper Substances 0.000 claims abstract description 32
- 229910000679 solder Inorganic materials 0.000 claims abstract description 18
- 238000000465 moulding Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000004593 Epoxy Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 229920001971 elastomer Polymers 0.000 abstract description 9
- 239000000806 elastomer Substances 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000007613 environmental effect Effects 0.000 abstract description 4
- 238000005476 soldering Methods 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000035939 shock Effects 0.000 abstract 1
- 239000011805 ball Substances 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 마이크로 비지에이 패키지 및 제조방법에 관한 것으로서, 종래의 마이크로 비지에이 패키지는 반도체칩과 서브스트레이트의 열팽창계수에 차이가 있으며, 상기 패키지를 피시비기판에 실장시 발생되는 솔더링의 신뢰성 저하를 방지하기 위하여 상기 엘라스트머를 개재하여 완충시키는 바, 패키지의 제조원가가 상승되며, 반도체칩의 대부분이 외부에 노출되는 구조이므로 외부의 충격과 환경변화에 대하여 취약한 문제점이 있었으나, 본 발명에 의한 마이크로 비지에이 패키지는 절연필름에 부착된 구리필름에 회로를 형성하여 다수개의 솔더볼을 부착하고, 상기 구성요소 및 반조체칩을 완전히 감싸도록 몰딩부를 형성함으로써, 외부의 충격과 환경변화로부터 신뢰성을 확보할 수 있으며, 엘라스트머의 사용을 배제하여 제조원가를 저감시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microvisual package and a manufacturing method, which has a difference in coefficient of thermal expansion of a semiconductor chip and a substrate, and prevents the deterioration of soldering reliability generated when the package is mounted on a PCB. In order to buffer the elastomer through the elastomer, the manufacturing cost of the package is increased, and since most of the semiconductor chips are exposed to the outside, there is a problem that is vulnerable to external shocks and environmental changes. A package attaches a plurality of solder balls by forming a circuit on a copper film attached to an insulating film, and forms a molding part to completely enclose the component and the semi-manufactured chip, thereby securing reliability from external impact and environmental changes. Reduces manufacturing costs by eliminating the use of elastomers Kiel can.
Description
본 발명은 마이크로 비지에이 패키지 및 제조방법에 관한 것으로서, 보다 상세하게는 패키지의 몸체를 에폭시로 감싸도록 형성함으로써, 외부의 충격과 환경변화로부터 신뢰성을 확보할 수 있는 마이크로 비지에이 패키지 및 제조방법에 관한 것이다.The present invention relates to a microvisual package and a manufacturing method, and more particularly, to a microvisual package and a manufacturing method which can ensure reliability from external impact and environmental change by forming the body of the package to be wrapped with epoxy. It is about.
일반적으로 칩의 크기와 유사한 크기의 패키지를 제조하는 기술의 일환으로 개발된 패키지가 CSP(CHIP SIZE PACKAGE)이며, 이와 같은 CSP의 일종으로 마이크로 비지에이 패키지가 적용되는 바, 이를 설명하면 다음과 같다.In general, a package developed as part of a technology for manufacturing a package having a size similar to that of a chip is a CSP (CHIP SIZE PACKAGE), and a microvisi package is applied as a kind of such a CSP. .
도 1은 종래의 마이크로 비지에이 패키지의 구조를 나타내 보인 단면도로서, 도시된 바와 같이, 반도체칩(1)과, 상기 칩(1)의 상면에 접착제로 부착되어 있는 엘라스트머(2)와, 상기 엘라스트머(2)의 상면에 부착되는 테이프 형태의 서브스트레이트(3)와, 상기 서브스트레이트(3)의 상면에 패터닝되어 있으며, 그 일단부가 칩(1)의 칩패드(1a)들에 각각 연결되어 있는 리드패턴(4)과, 상기 리드패턴(4)의 상면에서 부착되는 솔더마스크(5)와, 상기 리드패턴(4)에 형성된 랜드(4a)에 부착되는 솔더볼(6)과, 상기 칩패드(1a)에 부착되는 리드패턴(4)을 감싸도록 형성되는 인캡슐런트(7)로 구성된다.1 is a cross-sectional view showing the structure of a conventional microvisi package, as shown, the semiconductor chip 1, the elastomer 2 attached to the upper surface of the chip 1 with an adhesive, The tape-shaped substrate 3 attached to the upper surface of the elastomer 2 and the upper surface of the substrate 3 are patterned, and one end thereof is formed on the chip pads 1a of the chip 1. A lead pattern 4 connected to each other, a solder mask 5 attached on an upper surface of the lead pattern 4, a solder ball 6 attached to a land 4a formed on the lead pattern 4, The encapsulant 7 is formed to surround the lead pattern 4 attached to the chip pad 1a.
상기와 같은 구성을 갖는 종래 마이크로 비지에이 패키지의 제조공정을 순차적으로 설명하면 다음과 같다.The manufacturing process of the conventional microvisi package having the above configuration will be described as follows.
먼저, 도 2a에 도시된 바와 같이, 하면에 엘라스트머(2)가 부착되어 있고, 상면에 리드패턴(4)들이 형성되어 있는 서브스트레이트(3)를 칩(1)의 상측에 위치시키고, 접착제(미도시)를 이용하여 엘라스트머(2)의 하측에 칩을 고정부착한다.First, as shown in FIG. 2A, the substrate 3 having the elastomer 2 attached to the lower surface and the lead patterns 4 formed on the upper surface thereof is positioned above the chip 1. A chip is fixedly attached to the lower side of the elastomer 2 using an adhesive (not shown).
다음, 도 2b와 같이, 상기 리드패턴(4)의 일정 부분에 본딩툴(8)을 위치시키고, 아래로 강압하여 리드패턴(4)을 절단하여 칩패드(1a)에 부착시킨다.Next, as illustrated in FIG. 2B, the bonding tool 8 is positioned at a predetermined portion of the lead pattern 4, and the lead tool 4 is cut down to cut the lead pattern 4 and attached to the chip pad 1a.
그런 다음, 도 2c와 같이, 솔더마스크(5)를 상기 리드패턴(4)의 상면에 부착하고, 상기 리드패턴(4)의 주변에 인캡슐런트(7)를 포팅한 후 경화시킨다.Then, as shown in FIG. 2C, the solder mask 5 is attached to the upper surface of the lead pattern 4, the encapsulant 7 is potted around the lead pattern 4, and then cured.
그런 다음, 도 2d와 같이, 상기 서브스트레이트(3)의 상면에 솔더볼(6)을 고정부착하고, 상기 서브스트레이트(3)의 외측 부분을 일정 크기로 절단하여 마이크로 비지에이 패키지를 완성한다.Then, as shown in FIG. 2D, the solder ball 6 is fixedly attached to the upper surface of the substrate 3, and the outer portion of the substrate 3 is cut to a predetermined size to complete the microvisual package.
그러나, 종래의 마이크로 비지에이 패키지는 반도체칩(1)과 서브스트레이트(3)의 열팽창계수에 차이가 있는 바, 이로 인하여 피시비기판에 실장시 발생되는 솔더링의 신뢰성 저하를 방지하기 위하여 상기 엘라스트머(2)를 개재하여 완충시키므로 패키지의 제조원가가 상승되는 한편, 반도체칩(1)의 대부분이 외부에 노출되는 구조이므로 외부의 충격과 환경변화에 대하여 취약한 문제점이 있었다.However, in the conventional microvisi package, the thermal expansion coefficients of the semiconductor chip 1 and the substrate 3 are different. Therefore, the elastomer is prevented from deteriorating the reliability of soldering generated when the PCB is mounted on the PCB. Since the manufacturing cost of the package is increased due to the buffering through (2), most of the semiconductor chips 1 are exposed to the outside.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 엘라스트머의 사용을 배제하여 제조원가를 저감시키는 한편, 반도체칩의 외부 노출을 감소시켜 신뢰성을 향상시킬 수 있는 마이크로 비지에이 패키지 및 제조방법을 제공하는 데 있다.The present invention has been made to solve the above problems of the prior art, an object of the present invention to reduce the manufacturing cost by eliminating the use of the elastomer, while reducing the external exposure of the semiconductor chip to improve the reliability The present invention provides a package and a manufacturing method.
도 1은 종래의 마이크로 비지에이 패키지의 구조를 나타내 보인 단면도.1 is a cross-sectional view showing the structure of a conventional microvisi package.
도 2a 내지 도 2d는 종래의 마이크로 비지에이 패키지의 제조공정을 순차적으로 나타내 보인 단면도.2A to 2D are cross-sectional views sequentially illustrating a manufacturing process of a conventional microvisi package.
도 3은 본 발명에 따른 마이크로 비지에이 패키지의 구조를 나타내 보인 단면도.Figure 3 is a cross-sectional view showing the structure of a microvisiage package according to the present invention.
도 4a 내지 도 4l은 본 발명에 따른 마이크로 비지에이 패키지의 제조공정을 순차적으로 나타내 보인 단면도.4A to 4L are cross-sectional views sequentially illustrating a manufacturing process of the microvisual package according to the present invention.
〈 도면의 주요부분에 대한 부호설명〉<Code Description of Major Parts of Drawings>
11 : 칩 12 : 절연필름11 chip 12 insulation film
12a: 중앙홈 12b: 요입홈12a: center groove 12b: recessed groove
13 : 구리필름 13a: 랜드13: copper film 13a: land
14 : 감광성필름 15 : 금속와이어14 photosensitive film 15 metal wire
16 : 솔더볼 17 : 몰딩부16 solder ball 17 molding part
상기 목적을 달성하기 위하여, 본 발명인 마이크로 비지에이 패키지는 반도체칩과, 상기 칩의 하면에 부착되는 테이프 형태의 절연필름과, 상기 절연필름의 하면에서 양각으로 부착되어 회로를 형성하며 랜드를 가지는 다수개의 구리필름과, 상기 각 구리필름과 상기 반도체칩을 전기적으로 연결하는 다수개의 금속와이어와, 상기 각 구리필름의 일측에 형성된 랜드에 부착되는 다수개의 솔더볼과, 상기 솔더볼의 일부만 하측으로 돌출되도록 전체를 감싸는 몰딩부로 구성된다.In order to achieve the above object, the present invention micro-visi package is a semiconductor chip, an insulating film in the form of a tape attached to the lower surface of the chip, and a plurality of lands are formed by embossing on the lower surface of the insulating film to form a circuit Copper films, a plurality of metal wires electrically connecting the copper films and the semiconductor chip, a plurality of solder balls attached to lands formed on one side of each copper film, and a portion of the solder balls so that only a part of the solder balls protrude downward Consists of a molding unit surrounding the.
그리고, 상기 마이크로 비지에이 패키지의 제조방법은 절연필름과 접착되어 있는 구리필름을 식각하여 회로를 형성함과 아울러 원형 랜드를 형성하는 단계와; 상기 회로가 형성된 구리필름의 저면부 전체에 감광성필름을 부착한 후, 상기 구리필름의 원형 랜드에 부착된 감광성필름 만을 남기고 나머지 부분을 식각공정으로 제거하는 단계와; 상기 절연필름의 중앙부에 금속와이어가 결합되기 위한 중앙홈을 형성하고, 좌우측부에 에폭시가 주입되기 위한 요입홈을 형성하는 단계와; 상기 절연필름의 상측에 칩을 부착하고, 상기 칩의 하면과 상기 구리필름의 일측을 금속와이어로 전기적으로 연결하는 단계와; 몰딩금형을 장착하여 내측의 공동부 및 중앙홈과 요입홈에 에폭시를 주입하여 몰딩부를 형성하는 단계와; 상기 구리필름의 원형 랜드에 부착된 감광성필름을 식각공정으로 제거하여 랜드를 노출시키는 단계와; 상기 구리필름의 랜드 하면에 솔더볼을 고정 부착한 후, 상기 몰딩부의 외측 부분을 절단하여 패키지를 완성하는 단계의 순서로 제조되는 것을 특징으로 한다.In addition, the manufacturing method of the micro visual package may include forming a circuit by etching a copper film adhered to an insulating film and forming a circular land; Attaching the photosensitive film to the entire bottom portion of the copper film on which the circuit is formed, leaving only the photosensitive film attached to the circular land of the copper film and removing the remaining portion by an etching process; Forming a central groove for coupling metal wires to a central portion of the insulating film, and forming a recess groove for injecting epoxy into left and right sides; Attaching a chip to an upper side of the insulating film, and electrically connecting a lower surface of the chip and one side of the copper film with a metal wire; Mounting a molding mold to inject epoxy into the inner cavity and the central groove and the recess groove to form a molding part; Removing the photosensitive film attached to the circular land of the copper film by an etching process to expose the land; After fixing the solder ball to the land lower surface of the copper film, it is characterized in that the manufacturing process in the step of completing the package by cutting the outer portion of the molding.
이하 본 발명의 바람직한 일실시례를 첨부 도면에 의거하여 상세히 설명하면 다음과 같다.BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 마이크로 비지에이 패키지를 나타내 보인 단면도로서, 도시된 바와 같이, 반도체칩(11)과, 상기 칩의 하면에 부착되는 테이프 형태의 절연필름(12)과, 상기 절연필름(12)의 하면에서 양각으로 부착되는 다수개의 구리필름(13)과, 상기 각 구리필름(13)과 상기 칩(11)을 전기적으로 연결하는 다수개의 금속와이어(15)와, 상기 각 구리필름(13)의 일측에 형성된 랜드(13a)에 부착되는 다수개의 솔더볼(16)과, 상기 솔더볼(16)의 일부만 하측으로 돌출되도록 전체를 감싸는 몰딩부(17)로 구성된다.3 is a cross-sectional view showing a micro-visage package according to the present invention, as shown, a semiconductor chip 11, an insulating film 12 in the form of a tape attached to the lower surface of the chip, and the insulating film ( 12, a plurality of copper films 13 embossed on the bottom surface, a plurality of metal wires 15 electrically connecting the copper films 13 and the chips 11, and the respective copper films ( 13 is composed of a plurality of solder balls 16 attached to the land (13a) formed on one side, and a molding portion (17) surrounding the whole so that only a part of the solder ball 16 protrudes to the lower side.
이하, 상기와 같이 구성된 본 발명에 따른 마이크로 비지에이 패키지의 제조방법을 설명하면 다음과 같다.Hereinafter, the manufacturing method of the micro-visie package according to the present invention configured as described above are as follows.
상기와 같은 구성을 갖는 본 발명에 따른 마이크로 비지에이 패키지의 제조공정을 순차적으로 설명하면 다음과 같다.Referring to the manufacturing process of the micro-visie package according to the present invention having the above configuration in order as follows.
먼저, 도 4a에 도시된 바와 같이, 상기 절연필름(12)과 접착되어 있는 구리필름(13)을 식각시킨다. 도 4b는 상기 식각된 절연필름(12)과 구리필름(13)의 저면도로서, 도시된 바와 같이, 저면부에 좁은 사각봉의 형상으로 양각으로 돌출되어 있으며, 그 일측에는 솔더볼(16)이 접합되는 랜드(13a)가 형성된다.First, as shown in FIG. 4A, the copper film 13 adhered to the insulating film 12 is etched. Figure 4b is a bottom view of the etched insulating film 12 and the copper film 13, as shown, protruding embossed in the shape of a narrow rectangular bar on the bottom portion, the solder ball 16 is bonded to one side Lands 13a are formed.
다음, 도 4c와 같이, 상기 회로가 형성된 구리필름(13)의 저면부 전체에 감광성필름(14)을 부착한 후, 도 4d와 같이, 상기 구리필름(13)의 원형 랜드(13a)에 부착된 감광성필름(14) 만을 남기고 나머지 부분을 제1식각공정으로 제거한다. 도4e는 상기 제 1식각공정에 의하여 형성된 패키지의 저면도이다.Next, as illustrated in FIG. 4C, the photosensitive film 14 is attached to the entire bottom portion of the copper film 13 on which the circuit is formed, and then attached to the circular land 13a of the copper film 13 as shown in FIG. 4D. Leaving only the photosensitive film 14, the remaining portion is removed by the first etching process. 4E is a bottom view of a package formed by the first etching process.
그런 다음, 도 4f와 같이, 상기 절연필름(12)의 중앙부에 금속와이어(15)가 결합되기 위한 중앙홈(12a)을 형성하고, 좌우측부에 에폭시가 주입되기 위한 요입홈(12b)을 형성한다. 도 4f는 상기 중앙홈(12a)과 요입홈(12b)이 형성된 절연필름(12)과 구리필름(13)의 저면도이다.Then, as shown in Figure 4f, the center groove 12a for coupling the metal wire 15 to the center portion of the insulating film 12 is formed, and the recessed groove 12b for injecting epoxy to the left and right sides are formed. do. 4F is a bottom view of the insulating film 12 and the copper film 13 in which the center groove 12a and the recess groove 12b are formed.
그런 다음, 도 4h와 같이, 상기 절연필름(12)의 상측에 칩(11)을 부착하고, 상기 칩(11)의 하면과 상기 구리필름(13)의 일측을 금속와이어(15)로 전기적으로 연결한다.Then, as shown in FIG. 4H, the chip 11 is attached to the upper side of the insulating film 12, and the lower surface of the chip 11 and one side of the copper film 13 are electrically connected to the metal wire 15. Connect.
그런 다음, 도 4i와 같이, 몰딩금형(18)을 장착하여 내측의 공동부 및 중앙홈(12a)과 요입홈(12b)에 에폭시를 주입하여 경화시킨 후, 도 4j와 같이, 몰딩금형(18)을 탈거하여 몰딩부(17)를 형성한다.Then, as shown in FIG. 4I, the molding die 18 is mounted to cure epoxy by injecting epoxy into the inner cavity, the central groove 12a and the recessed groove 12b, and as shown in FIG. 4J, the molding die 18 ) Is removed to form the molding part 17.
그런 다음, 도 4k와 같이, 상기 구리필름(13)의 원형 랜드(13a)에 부착된 감광성필름(14)을 제2식각공정으로 제거하여 랜드(13a)를 노출시킨다.Then, as shown in Figure 4k, the photosensitive film 14 attached to the circular land (13a) of the copper film 13 is removed by a second etching process to expose the land (13a).
그런 다음, 도 4l과 같이, 상기 구리필름(13)의 랜드(13a) 하면에 솔더볼(16)을 고정 부착한 후, 상기 몰딩부(17)의 외측 부분을 절단하여 도 3과 같이, 마이크로 비지에이 패키지를 완성한다.Then, as shown in FIG. 4L, the solder ball 16 is fixedly attached to the lower surface of the land 13a of the copper film 13, and then the outer portion of the molding part 17 is cut and micro busy as shown in FIG. 3. Complete this package.
이상에서 설명한 바와 같이, 본 발명에 의한 마이크로 비지에이 패키지는As described above, the microvisual package according to the present invention
절연필름에 부착된 구리필름에 회로를 형성하여 다수개의 솔더볼을 부착하고, 상기 구성요소 및 반조체칩을 완전히 감싸도록 몰딩부를 형성함으로써, 외부의충격과 환경변화로부터 신뢰성을 확보할 수 있으며, 엘라스트머의 사용을 배제하여 제조원가를 저감시킬 수 있는 효과가 있다.By forming a circuit on the copper film attached to the insulating film to attach a plurality of solder balls, and forming a molding portion to completely wrap the component and the semi-assembling chip, it is possible to secure reliability from external impact and environmental changes, elast It is possible to reduce the manufacturing cost by eliminating the use of the mer.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990039589A KR100336758B1 (en) | 1999-09-15 | 1999-09-15 | Micro ball grid array package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990039589A KR100336758B1 (en) | 1999-09-15 | 1999-09-15 | Micro ball grid array package and manufacturing method thereof |
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| KR20010027708A KR20010027708A (en) | 2001-04-06 |
| KR100336758B1 true KR100336758B1 (en) | 2002-05-16 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964080A (en) * | 1995-08-28 | 1997-03-07 | Hitachi Ltd | Semiconductor device and method of manufacturing it |
| KR970077557A (en) * | 1996-05-17 | 1997-12-12 | 문정환 | Chip size package and method of making the same |
| KR980013236A (en) * | 1996-07-31 | 1998-04-30 | 김광호 | Facsimile speed dialing method |
| KR19990055277A (en) * | 1997-12-27 | 1999-07-15 | 윤종용 | Chip scale package |
-
1999
- 1999-09-15 KR KR1019990039589A patent/KR100336758B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0964080A (en) * | 1995-08-28 | 1997-03-07 | Hitachi Ltd | Semiconductor device and method of manufacturing it |
| KR970077557A (en) * | 1996-05-17 | 1997-12-12 | 문정환 | Chip size package and method of making the same |
| KR980013236A (en) * | 1996-07-31 | 1998-04-30 | 김광호 | Facsimile speed dialing method |
| KR19990055277A (en) * | 1997-12-27 | 1999-07-15 | 윤종용 | Chip scale package |
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