KR100324632B1 - 2층구조의 스루홀을 갖는 반도체 장치 - Google Patents
2층구조의 스루홀을 갖는 반도체 장치 Download PDFInfo
- Publication number
- KR100324632B1 KR100324632B1 KR1019980004831A KR19980004831A KR100324632B1 KR 100324632 B1 KR100324632 B1 KR 100324632B1 KR 1019980004831 A KR1019980004831 A KR 1019980004831A KR 19980004831 A KR19980004831 A KR 19980004831A KR 100324632 B1 KR100324632 B1 KR 100324632B1
- Authority
- KR
- South Korea
- Prior art keywords
- hole
- film
- semiconductor device
- conductive layer
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000003990 capacitor Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 21
- 239000005380 borophosphosilicate glass Substances 0.000 description 18
- 229910004298 SiO 2 Inorganic materials 0.000 description 17
- 238000005530 etching Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (9)
- 반도체장치에 있어서,반도체기판;상기 반도체기판상에 놓이거나 상기 반도체기판 속에 형성된 제1 도전층;상기 제1 도전층상에 놓이고 상기 제1 도전층의 일부를 노출시키기 위한 스루홀을 자신의 내부에 가지는 절연막;상기 제1 도전층의 상기 일부와 접촉된 상태로 배열되고 상기 스루홀의 하측 일부를 채우는 도전플러그;상기 스루홀의 잔여부분의 내측벽상에 형성된 측벽절연막; 및상기 도전플러그를 통하여 상기 제1 도전층과 연결되도록 상기 도전플러그 및 상기 측벽절연막에 의해 한정되는 스루홀 부분을 단독으로 채우며 상기 절연막상에 형성되는 제2 도전층을 포함하는 것을 특징으로 하는 반도체장치.
- 제 1항에 있어서, 상기 제1 도전층은 상기 반도체기판의 확산영역인 것을 특징으로 하는 반도체장치.
- 제 2항에 있어서, 상기 절연막은 복수의 층들을 포함하는 것을 특징으로 하는 반도체장치.
- 제 3항에 있어서, 상기 제2 도전층은 커패시터의 기부전극인 것을 특징으로 하는 반도체장치.
- 제 1항에 있어서, 상기 도전플러그는 도핑된 실리콘층인 것을 특징으로 하는 반도체장치.
- 제 5항에 있어서, 상기 도핑된 실리콘층은 비정질실리콘으로 제조되는 것을 특징으로 하는 반도체장치.
- 제 5항에 있어서, 상기 도핑된 실리콘층은 다결정실리콘으로 제조되는 것을 특징으로 하는 반도체장치.
- 제 1항에 있어서, 상기 스루홀의 상기 하측일부는 상기 스루홀의 상기 잔여부분보다 더 큰 높이를 갖는 것을 특징으로 하는 반도체장치.
- 제 1항에 있어서, 상기 스루홀은 실질적으로 직선인 것을 특징으로 하는 반도체장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9-034919 | 1997-02-19 | ||
JP9034919A JP2943914B2 (ja) | 1997-02-19 | 1997-02-19 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19980071428A KR19980071428A (ko) | 1998-10-26 |
KR100324632B1 true KR100324632B1 (ko) | 2002-06-27 |
Family
ID=12427632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019980004831A KR100324632B1 (ko) | 1997-02-19 | 1998-02-17 | 2층구조의 스루홀을 갖는 반도체 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6246085B1 (ko) |
JP (1) | JP2943914B2 (ko) |
KR (1) | KR100324632B1 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100504949B1 (ko) * | 2000-12-29 | 2005-08-04 | 주식회사 하이닉스반도체 | 커패시터의 저장 전극 형성 방법 |
JP3875568B2 (ja) * | 2002-02-05 | 2007-01-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100524801B1 (ko) * | 2002-10-05 | 2005-11-02 | 주식회사 하이닉스반도체 | 이중 도핑 프로파일을 갖는 반도체 소자의 콘택플러그형성 방법 |
KR100522427B1 (ko) * | 2002-12-30 | 2005-10-20 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 제조방법 |
KR100532437B1 (ko) | 2003-05-26 | 2005-11-30 | 삼성전자주식회사 | 반도체 메모리 소자 및 그 제조 방법 |
JP2005050903A (ja) * | 2003-07-30 | 2005-02-24 | Toshiba Corp | 半導体装置およびその製造方法 |
US7888798B2 (en) * | 2007-05-16 | 2011-02-15 | Samsung Electronics Co., Ltd. | Semiconductor devices including interlayer conductive contacts and methods of forming the same |
JP2009152361A (ja) * | 2007-12-20 | 2009-07-09 | Toshiba Corp | 半導体装置およびその製造方法 |
US11903218B2 (en) * | 2020-06-26 | 2024-02-13 | Sandisk Technologies Llc | Bonded memory devices and methods of making the same |
US11538817B2 (en) | 2020-06-26 | 2022-12-27 | Sandisk Technologies Llc | Bonded memory devices and methods of making the same |
CN114256133A (zh) * | 2020-09-21 | 2022-03-29 | 长鑫存储技术有限公司 | 半导体器件、半导体结构及其制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63278363A (ja) * | 1987-05-11 | 1988-11-16 | Hitachi Ltd | 半導体記憶装置 |
JPH0730077A (ja) * | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08274278A (ja) * | 1995-01-31 | 1996-10-18 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02170561A (ja) | 1988-12-23 | 1990-07-02 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP3199717B2 (ja) | 1989-09-08 | 2001-08-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPH0689941A (ja) | 1991-02-18 | 1994-03-29 | Sharp Corp | 半導体装置及びその製造方法 |
JP2827728B2 (ja) * | 1992-08-03 | 1998-11-25 | 日本電気株式会社 | 半導体記憶装置およびその製造方法 |
KR950014980A (ko) * | 1993-11-19 | 1995-06-16 | 김주용 | 반도체 소자의 캐패시터 형성방법 |
JPH07235612A (ja) * | 1994-02-23 | 1995-09-05 | Mitsubishi Electric Corp | 半導体装置のメモリセル構造 |
US5627094A (en) * | 1995-12-04 | 1997-05-06 | Chartered Semiconductor Manufacturing Pte, Ltd. | Stacked container capacitor using chemical mechanical polishing |
US5633781A (en) * | 1995-12-22 | 1997-05-27 | International Business Machines Corporation | Isolated sidewall capacitor having a compound plate electrode |
JP3689963B2 (ja) * | 1996-02-02 | 2005-08-31 | ソニー株式会社 | 半導体素子の接続孔及びその形成方法、並びに半導体素子の配線構造及び半導体素子 |
US5789030A (en) * | 1996-03-18 | 1998-08-04 | Micron Technology, Inc. | Method for depositing doped amorphous or polycrystalline silicon on a substrate |
US5918122A (en) * | 1997-02-11 | 1999-06-29 | Micron Technology, Inc. | Methods of forming integrated circuitry, DRAM cells and capacitors |
-
1997
- 1997-02-19 JP JP9034919A patent/JP2943914B2/ja not_active Expired - Lifetime
-
1998
- 1998-02-06 US US09/019,707 patent/US6246085B1/en not_active Expired - Lifetime
- 1998-02-17 KR KR1019980004831A patent/KR100324632B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63278363A (ja) * | 1987-05-11 | 1988-11-16 | Hitachi Ltd | 半導体記憶装置 |
JPH0730077A (ja) * | 1993-06-23 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08274278A (ja) * | 1995-01-31 | 1996-10-18 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US6246085B1 (en) | 2001-06-12 |
KR19980071428A (ko) | 1998-10-26 |
JP2943914B2 (ja) | 1999-08-30 |
JPH10233445A (ja) | 1998-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5990021A (en) | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture | |
US5571730A (en) | Semiconductor device having vertical metal oxide semiconductors and a method for manufacturing the same | |
US6074918A (en) | Methods of fabrication DRAM transistor cells with a self-aligned storage electrode contact | |
KR100315324B1 (ko) | 반도체장치및그제조방법 | |
US5321306A (en) | Method for manufacturing a semiconductor device | |
US6498375B2 (en) | Integrated circuitry | |
JP3532325B2 (ja) | 半導体記憶装置 | |
US5378908A (en) | Stack capacitor DRAM cell having increased capacitor area | |
US6573551B1 (en) | Semiconductor memory device having self-aligned contact and fabricating method thereof | |
KR100327123B1 (ko) | 디램셀캐패시터의제조방법 | |
US6861313B2 (en) | Semiconductor memory device and fabrication method thereof using damascene bitline process | |
US5902126A (en) | Methods for forming integrated circuit capacitor electrodes including surrounding insulating sidewalls and spacers | |
KR100324632B1 (ko) | 2층구조의 스루홀을 갖는 반도체 장치 | |
US5930621A (en) | Methods for forming vertical electrode structures and related structures | |
US5470778A (en) | Method of manufacturing a semiconductor device | |
US6369423B2 (en) | Semiconductor device with a thin gate stack having a plurality of insulating layers | |
US6323558B1 (en) | Method for fabricating a contact of a semiconductor device | |
US7034368B2 (en) | Semiconductor memory device and fabrication method thereof using damascene gate and epitaxial growth | |
KR100416607B1 (ko) | 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법 | |
GB2400237A (en) | Sidewall spacer structure for self-aligned contact | |
US6849889B2 (en) | Semiconductor device having storage node contact plug of DRAM (dynamic random access memory) | |
US20040038491A1 (en) | Capacitor for semiconductor device and method for manufacturing the same | |
US6080622A (en) | Method for fabricating a DRAM cell capacitor including forming a conductive storage node by depositing and etching an insulative layer, filling with conductive material, and removing the insulative layer | |
US6114202A (en) | Method of fabricating dynamic random access memory | |
KR20230078196A (ko) | 반도체 장치 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130118 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20140117 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20150119 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20160129 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20170120 Year of fee payment: 16 |
|
FPAY | Annual fee payment |
Payment date: 20180119 Year of fee payment: 17 |