KR100318535B1 - Thin film transistor substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

First, a gate wiring including a horizontal gate line and a gate electrode is formed on an insulating substrate, and a common wiring including a common signal line, a common signal line connection part, and a common electrode in a horizontal direction. Next, an amorphous silicon layer and an aluminum-based metal film are sequentially stacked on the gate insulating film, and the amorphous silicon layer and the metal film are patterned once to form a main data line defining a gate line and a unit pixel and a semiconductor layer below it in a similar shape. Here, in order to delay or prevent corrosion of the aluminum series, a method such as O ₂ plasma or CF ₄ plasma may be used or organic cleaning may be performed, and vacuum may be maintained. Next, a data line including a sub data line covering the main data line, a source electrode, and a drain electrode, and a pixel signal line extending vertically and overlapping with the common signal line to form a storage capacitor, are formed of a chromium film having excellent contact characteristics with ITO. Next, the main data line and the doped amorphous silicon layer, which are not covered by the data line or the pixel signal line, are etched to expose the semiconductor layer over the gate electrode. In this way, the main data line is formed of an aluminum-based metal, which is a low resistance metal, and is formed together with the semiconductor layer, thereby reducing the number of masks and forming a data line having excellent contact characteristics with ITO. Next, a pixel electrode connected to the pixel signal line and formed of ITO is formed on the passivation layer.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly to a thin film transistor substrate for a liquid crystal display device having an electrode formed on the same substrate for applying a horizontal electric field to liquid crystal molecules and a thin film transistor which is an electric field application means The manufacturing method is related.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, in order to improve the viewing angle, a common electrode and a pixel electrode, which are two electrodes for driving liquid crystal molecules, are formed on one substrate, and a liquid crystal by a horizontal electric field having a thin film transistor for switching a voltage applied to the electrodes. A driving type liquid crystal display device has been developed.

In order to improve the characteristics of the liquid crystal display, a signal line to which an image signal or a scan signal is transmitted is formed of a low resistance aluminum-based metal, and a common electrode or a pixel electrode is formed of ITO (transparent conductive film) to improve the aperture ratio of the pixel. indium tin oxide).

However, when the data line for transmitting the image signal is formed of an aluminum-based metal and the pixel electrode connected to the data line is formed of ITO, the aluminum-based metal and ITO have poor contact characteristics, so that the aluminum-based metal and ITO are poor. Since a buffer metal needs to be inserted in between, an additional manufacturing mask is generated, which increases manufacturing costs.

An object of the present invention is to form wirings of a horizontal electric field drive type liquid crystal display device with a low resistance metal and to minimize manufacturing costs.

1 is a layout view illustrating a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a cross-sectional view taken along the line II-II 'of FIG.

3A to 6B are views illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

In order to solve the above technical problem, in the present invention, the main data line formed of the semiconductor layer of the thin film transistor and the low resistance aluminum-based metal is patterned together with one mask, and the data wire covering the main data line has contact characteristics with ITO. It is formed of an excellent metal. The data line may be formed of chromium or molybdenum-based metal.

More specifically, the method for manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention, first, includes a gate line including a gate line and a gate electrode that is part of the gate line on the insulating substrate, and a common electrode connected to the common signal line and the common signal line. The common wiring is formed, and a gate insulating film is formed over the gate wiring and the common wiring. Next, a first conductive layer including a semiconductor material and an aluminum-based metal is sequentially stacked on the gate insulating layer and patterned at a time to form a semiconductor layer and a main data line. Subsequently, the second conductive layer includes a data line including a sub data line covering the main data line, a source electrode connected to the sub data line, a drain electrode facing the source electrode around the gate electrode, and a pixel signal line connected to the drain electrode. Form. Subsequently, a semiconductor layer over the gate electrode is exposed, a passivation layer covering the data line, the pixel signal line and the semiconductor layer is formed, and the passivation layer is patterned to form a contact hole exposing the pixel signal line. Finally, the pixel electrode connected to the pixel signal line through the contact hole on the passivation layer is formed of ITO, which is a transparent conductive material.

Here, the gate wiring, the common wiring, and the main data line may be formed of an aluminum based metal as an upper layer, and the lower layer or the second conductive layer may be formed of a chromium or molybdenum based metal. In addition, when forming the pixel electrode, redundant data wirings connected to the data wirings may be further formed through the contact holes of the protective film.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

In the liquid crystal display according to the present invention, the common signal line connection part is formed in the long direction of the pixel along with the data line, and the liquid crystal molecules are initially oriented perpendicularly to them, while the common electrode is formed in the short direction of the pixel.

First, the structure of a thin film transistor substrate for a liquid crystal display device according to the present invention will be described in detail with reference to FIGS. 1 and 2. 1 is a layout view briefly illustrating a configuration of a unit pixel in a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1.

1 and 2, the gate line 20 is formed in the horizontal direction on the transparent insulating substrate 100, and a part of the gate line 20 becomes the gate electrode 21. A common signal line 24 is formed above and below the pixel in parallel with the gate line 20, and a common signal line connection part 26 connecting the common signal line 24 is disposed in the vertical direction at the left and right edges of the pixel. Formed. In addition, on the substrate 100, a plurality of common electrodes 28, which are branches of the common signal line connection part 26 and extend in the horizontal direction of the pixel and receive common signals from the common signal line 24, are parallel to each other. It is formed in the direction and arranged in the long direction of a pixel. Here, the common electrode 28 may be formed at an angle with respect to the gate line 20. Here, the gate wirings 20 and 21 and the common wirings 24, 26 and 28 are formed of the lower chromium films 201 and 211: 241, 261 and 281 and the upper aluminum-neodium alloy films 202, 212 and 242. , 262, 282).

The gate wirings 20 and 21 and the common wirings 24, 26 and 28 are covered with a gate insulating film 30 made of silicon nitride or the like.

On the gate insulating film 30, the semiconductor layer 40 of the thin film transistor made of amorphous silicon, which is a semiconductor, and the main data line 60 defining the pixel by crossing the resistance contact layers 51 and 52 and the gate line 20 are mutually intersected. It is formed in a similar shape. Here, the ohmic contacts 51 and 52 and the main data line 60 are formed by being separated from the gate electrode 21, and the main data line 60 is formed of the chromium layer 601 and the low resistance of the lower portion. The branch is made of an aluminum based metal film 602.

An upper portion of the main data line 60 is connected to the sub data line 70 and the sub data line 70 made of chromium or molybdenum-based metal having excellent contact characteristics with ITO, which is a transparent conductive film, and extends toward the gate electrode 21. Data lines consisting of a drain electrode 72 facing the source electrode 71 centering on the source electrode 61 and the gate electrode 21, which are connected to the drain electrode 72, extend in the horizontal direction, and extend in the horizontal direction. The pixel signal line 74 which forms the storage capacitor which overlaps with () is formed.

The gate electrode 21, the gate insulating film 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 71 and 72 form a thin film transistor.

A protective film 80 made of an insulating material such as silicon nitride is formed on the data lines 70, 71, 72, the pixel signal lines 74, and the semiconductor layer 40 not covered by the data lines.

A pixel wiring formed of indium tin oxide (ITO), which is a transparent conductive material, and connected to the pixel signal line 74 through the contact hole 81 of the passivation layer 80 is formed on the passivation layer 80. Here, the pixel wirings extend in the branches of the pixel signal line connecting portion 94 and the pixel signal line connecting portion 94 overlapping the common signal line 24 and the common signal line connecting portion 26 and are common to the common electrode 28 in the horizontal direction. The pixel electrode 98 is formed between the electrodes 28. Here, the pixel signal line connection unit 94 has a function of securing a storage capacitance through overlapping with the common signal line 24 and the common signal line connection unit 26.

Here, the protective film 70 may be an organic film having a good planarization.

In the liquid crystal display according to the exemplary embodiment of the present invention, the common signal line connection part 26 is formed in the long direction of the pixel parallel to the main and sub data lines 60 and 70, and the common electrode 28 and the pixel electrode ( 98 is formed in the short direction of the pixel and arranged in the long direction of the pixel.

Here, the common wirings 24, 26, 28 are formed on the same layer as the gate wirings 20, 21, but may be formed on different layers, and the liquid crystal molecules are preferably rubbed perpendicularly to the data lines.

Now, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention will be described. 3A to 6B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate for a liquid crystal display as shown in FIGS. 1 and 2.

First, as shown in FIGS. 3A to 3B, a chromium (Cr) film and a aluminum-neodium (Al-Nd) alloy film are formed on a transparent insulating substrate 100 such as glass with a thickness of about 500 kPa and about 2,500 kPa. Deposition in turn and patterning using the first mask to form a gate wiring consisting of the gate line 20 and the gate electrode 21, the common in the vertical direction extending to the branch of the common signal line 24, the common signal line 24 in the horizontal direction A common wiring made up of the common electrode 28 connecting the signal line connecting portion 26 and the common signal line connecting portion 26 is formed. In this case, various conductive materials may be used as the gate wiring metal, and the gate wiring may be formed using a single film made of chromium, aluminum, an aluminum alloy, molybdenum, molybdenum alloy, or the like, or a double film combining these metals. Here, the gate wiring 21 and the common wiring 24, 26, 28 are the lower films 211: 241, 261, 281 of chromium and the upper films 212: 242, 262, 282 of aluminum-neodium alloy. It is a case of a double film formed. Although not shown in cross section, the gate line is formed of a double layer.

Next, as shown in FIGS. 4A and 4B, an insulating gate insulating film 30, such as silicon nitride or an organic insulating film, is formed on the entire surface of the substrate 100 to a thickness of 3,000 to 5,000 GPa, and the amorphous is about 500 to 2,000 GPa thick. The silicon layer 40 and the amorphous silicon layer 50 heavily doped with impurities such as phosphorous having a thickness of about 500 GPa are sequentially deposited. Next, a conductive layer made of a chromium (Cr) film 601 having a thickness of about 500 GPa and an aluminum-neodium (Al-Nd) alloy film 602 which is an aluminum-based metal having a low resistance of about 2,500 GPa ( 60) are sequentially deposited, and the conductive layer 60, the doped amorphous silicon layer 50, and the amorphous silicon layer 40 are patterned together by a second process using a second mask to cross the gate line 20 to unit pixel. The main data line 60 and the lower portion of the ohmic contact layer 50 and the semiconductor layer 40 are formed in the same shape. At this time, a part of the main data line 60 extends in a branch, passes over the gate electrode 21, and overlaps a part of the common signal line 24.

Here, the main data line 60 is patterned without removing the photoresist pattern used as a mask for forming the main data line 60 in the photolithography process, and the continuously doped amorphous silicon layer 50 and the amorphous silicon layer are 40 may be patterned, or the photosensitive film pattern may be removed, and the amorphous silicon layer 50 and the amorphous silicon layer 40 doped with the main data line 60 as a mask may be patterned. In this case, a chlorine-based gas is used as a dry etching gas for etching amorphous silicon. When the main data line 60 is used as a mask, aluminum-based metal may be exposed to chlorine-based gas to corrode. . That is, when all of the chlorine-based gas is not volatilized and remains on the aluminum-based metal surface, which is the main data line 60, the chlorine-based gas is exposed to the atmosphere to react with moisture to generate hydrochloric acid, and hydrochloric acid is aluminum. Corrosive to metals.

To prevent this, after the doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned, a method such as O ₂ plasma or CF ₄ plasma is used before the main data line 60 is exposed to the atmosphere. It is preferable to form a thin protective film. In addition, after the doped amorphous silicon layer 50 and the amorphous silicon layer 40 are patterned, the organic cleaning may be performed to prevent corrosion, and the corrosion may be delayed when the vacuum state is sufficiently maintained.

As described above, the main data line 60 is formed of an aluminum-based metal having low resistance, and the semiconductor layer 40 is formed as one mask to reduce manufacturing cost.

Next, as shown in FIGS. 5A and 5B, a chromium film having excellent contact characteristics with an indium tin oxide (ITO), which is a transparent conductive material, is laminated to a thickness of about 500 GPa and patterned by a photo process using a third mask to form a main data line (60). ), The data including a sub data line 70 covering the (), a source electrode 71 extending in the direction of the gate electrode 21, and a drain electrode 72 facing the source electrode 71 around the gate electrode 21. A pixel signal line 74 connected to the wiring and drain electrode 72 and extending in the vertical direction and covering a part of the main data line 60 overlapping the common signal line 24 is formed. Here, the main data line 60 covering the pixel signal line 74 and the pixel signal line 74 and the common signal line 24 overlapping them form a storage capacitor. Next, the main data line 60 and the doped amorphous silicon layer 50 which are not covered by the source electrode 71 and the drain electrode 72 are etched to etch the main data line 60 and the doped amorphous silicon layer 50. The resistive contact layers 51 and 52 are completed by separating the gate electrodes 21 on both sides, and the semiconductor layer 40 on the gate electrode 21 is exposed.

The data lines 70, 71, 72, and the pixel signal lines 74 may be formed of a material having excellent contact characteristics with ITO, which is a transparent conductive material, and may be formed of a chromium or molybdenum-based metal.

In this manner, the data lines 70, 71, 72 and the pixel signal lines 74 which form the main data line 60 with the aluminum series metal, which is a low resistance metal, and cover the main data line 60 without increasing the number of masks, are increased. ) May be formed of a material having excellent contact characteristics with ITO, thereby improving contact characteristics between the pixel wirings formed thereafter and the pixel signal lines 74, and avoiding contact between the aluminum-based main data lines 60 and ITO. .

Here, the chromium film of the data wirings 70, 71, 72 and the pixel signal line 74 is etched by wet etching without removing the photoresist pattern used in the photographing process in order to prevent under cut. The aluminum-neodium alloy film 602, which is the upper layer of the main data line 60, is etched by dry etching, and the chromium layer 601, which is the lower layer of the main data line 60, is etched by wet etching. Do. Next, the photoresist pattern used in the photographing process is removed, and then the ohmic contact layers 51 and 52 are separated.

Next, as shown in FIGS. 6A and 6B, a protective film 80 having a thickness of 1,500 to 2,500 Å is formed on the entire surface of the substrate 100 using silicon nitride or an organic insulating film, and the protective film is formed by a patterning process using a fourth mask. The 80 is etched to form a contact hole 84 exposing the pixel signal line 74. In this case, in order to form a redundant data line, a contact hole exposing a part of the sub data line 70 may be formed.

Finally, as shown in FIGS. 1 and 2, ITO, a transparent conductive material, is laminated and patterned by a photolithography process using a fifth mask, and connected to the pixel signal line 74 through the contact hole 84. The pixel electrode 98 parallel to the common electrode 28 between the pixel signal line connecting portion 94 and the common electrode 28 overlapping the common signal line 24 in the direction and overlapping the common signal line connecting portion 26 in the vertical direction. Pixel wirings are formed.

Thus, when the pixel wirings 94 and 98 are formed of a transparent conductive material, the aperture ratio of the pixel can be improved.

In this case, when the contact hole exposing the sub data line 70 is formed in the passivation layer 80, the redundant data line is disposed on the same layer as the pixel wirings 94 and 98 in parallel with the main and sub data lines 60 and 70. In this case, disconnection of the primary and secondary data lines 60 and 70 can be reinforced.

Thereafter, an alignment layer is formed on the surface of the substrate and subjected to a process such as rubbing to give the orientation of the liquid crystal material. The alignment direction may be oriented perpendicular to the data line 60 and the common signal line connector 26.

In addition, as in the present exemplary embodiment, the common signal line connection part 26 is formed in the long direction of the pixel in parallel with the data line 60, and the liquid crystal molecules are vertically aligned and parallel to the gate line 20 to perform initial data. The side crosstalk occurring at the part adjacent to the line can be eliminated. As such, crosstalk can be eliminated without overlapping the data line 60 and the common signal line 24 adjacent thereto, thereby minimizing parasitic capacitance generated therebetween. The common electrode 28 and the pixel electrode 98 may be formed to be inclined at an arbitrary angle with respect to the gate line 20.

As in the embodiment of the present invention, the data wiring and the aluminum wire having a low resistance to form the main data line and the semiconductor layer as a mask and to cover the main data line with a material having excellent contact characteristics with the ITO of the pixel electrode; By forming the pixel signal line, the number of masks can be reduced to reduce manufacturing cost, and the contact between ITO and aluminum-based metal can be avoided, thereby improving product characteristics.

Claims (12)

(Correction) a gate wiring including a gate line formed on a substrate in a horizontal direction and a gate electrode which is a part of the gate line, A common wiring formed on the substrate, the common wiring including a common signal line formed in a horizontal direction and a common electrode branched from the common signal line and formed in a horizontal direction ; A gate insulating film covering the common wiring and the gate wiring; A main data line formed in the vertical direction on the gate insulating layer and defining a pixel area crossing the gate line, the main data line being made of an aluminum-based metal; A data line including a sub data line covering the main data line, a source electrode connected to the sub data line and extending toward the gate electrode, and a drain electrode facing the source electrode with respect to the gate electrode; A pixel signal line connected to the drain electrode and overlapping the common signal line; A protective film covering the data line and the pixel signal line and having a contact hole exposing the pixel signal line; A pixel wiring line including a pixel signal line connection part connected to the pixel signal line through the contact hole and a pixel electrode connected to the pixel signal line connection part and formed in parallel with the common electrode; Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The gate line is a thin film transistor substrate for a liquid crystal display device including an aluminum-based metal. In claim 2, The data line and the pixel signal line include a chromium or molybdenum-based metal. In claim 3, And the pixel wirings include ITO. Stacking and patterning a conductive material on the (correction) insulating substrate to form a gate line including a gate line and a gate electrode that is part of the gate line, and forming a common line including a common signal line and a common electrode connected to the common signal line, Forming a gate insulating film on the substrate to cover the gate wiring and the common wiring; Stacking a first conductive layer including a semiconductor material layer and an aluminum-based metal on the gate insulating layer in order, and then forming a semiconductor layer and a main data line by a patterning process using one mask ; A second conductive layer stacked and patterned to be connected to a data line and a drain electrode including a sub data line covering the main data line, a source electrode connected to the sub data line, and a drain electrode facing the source electrode centered on the gate electrode; Forming a pixel signal line, Removing the portion of the main data line that is not covered by the source electrode and the drain electrode to expose the semiconductor layer on the gate electrode; Forming a passivation layer having a contact hole exposing the pixel signal line; Forming a pixel electrode connected to the pixel signal line through the contact hole on the passivation layer; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 5, And the pixel electrode is formed of ITO, which is a transparent conductive material. In claim 6, And the main data line includes the aluminum based metal as an upper layer, and the lower layer is formed of a chromium or molybdenum based metal. In claim 7, And the second conductive layer is formed of chromium or molybdenum-based metal. In claim 8, In the forming of the data line and the pixel signal line, the second conductive layer is etched by wet etching, and in the step of exposing the semiconductor layer, the upper layer is etched by dry etching and the lower layer is etched by wet etching. Method of manufacturing a thin film transistor substrate. In claim 9, The data line and the pixel signal line forming step are performed by a photo process using a photoresist pattern, and the photoresist pattern is removed after the lower layer wet etching step. In claim 5, And performing an O ₂ plasma or CF ₄ plasma after the main data line and the semiconductor layer forming step. In claim 5, And performing organic cleaning after the main data line and the semiconductor layer forming step.