KR100289662B1 - Overlay Measurement Patterns of Semiconductor Devices - Google Patents

Overlay Measurement Patterns of Semiconductor Devices Download PDF

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KR100289662B1
KR100289662B1 KR1019980059950A KR19980059950A KR100289662B1 KR 100289662 B1 KR100289662 B1 KR 100289662B1 KR 1019980059950 A KR1019980059950 A KR 1019980059950A KR 19980059950 A KR19980059950 A KR 19980059950A KR 100289662 B1 KR100289662 B1 KR 100289662B1
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pattern
vernier
overlay measurement
overlay
buffer space
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KR1019980059950A
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Korean (ko)
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KR20000043552A (en
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김광철
양성우
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박종섭
현대전자산업주식회사
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/70683—Mark designs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 열적 스트레스에 의한 모버니어와 자버니의 측면변형을 방지하여 오버레이 정확도를 향상시킬 수 있는 반도체 소자의 오버레이 측정패턴을 제공한다.The present invention provides an overlay measurement pattern of a semiconductor device that can improve the overlay accuracy by preventing the side deformation of the vernier and Zaberny due to thermal stress.

본 발명에 따른 반도체 소자의 오버레이 측정패턴은 다이와 다이사이를 분할하는 스크라이브 라인을 구비한 반도체 기판과, 스크라이브 라인 상에 전스텝에서 형성되고 일정간격의 버퍼공간을 두고 이격된 오픈된 사각패턴의 내부패턴 및 외부패턴으로 이루어진 모버니어와, 모버니어의 내부패턴 내부에 형성된 사각패턴의 자버니어를 포함한다. 여기서, 버퍼공간은 상기 모버니어의 열적 스트레스로 인한 변형을 방지하고, 모버니어의 내부패턴과 외부패턴 사이에 단차가 발생된 경우 내부패턴 사이에 에치스톱층을 더 구비한다.The overlay measurement pattern of the semiconductor device according to the present invention includes a semiconductor substrate having a scribe line dividing the die and the die, and an open rectangular pattern formed at all steps on the scribe line and spaced apart from each other with a predetermined interval of buffer space. It includes a vernier consisting of a pattern and an outer pattern, and a vernier of a square pattern formed inside the inner pattern of the vernier. Here, the buffer space prevents deformation due to the thermal stress of the vernier, and further includes an etch stop layer between the inner pattern when a step is generated between the inner pattern and the outer pattern of the vernier.

Description

반도체 소자의 오버레이 측정패턴Overlay Measurement Patterns of Semiconductor Devices

본 발명은 반도체 소자의 오버레이 측정패턴에 관한 것으로, 특히 오버레이 정확도(overlay accuracy)를 향상시킬 수 있는 반도체 소자의 오버레이 측정패턴에 관한 것이다.The present invention relates to an overlay measurement pattern of a semiconductor device, and more particularly, to an overlay measurement pattern of a semiconductor device capable of improving overlay accuracy.

오버레이 정확도란 디바이스의 프로세스 스텝의 진행시 전스텝과 후스텝간의 정렬상태를 나타내는 지수로서 마스크 제작시 발생하는 에러와 디바이스의 프로세스 및 시스템 에러에 의해 영향을 받는다. 이러한 오버레이 정확도를 측정하기 위하여, 다이(die)와 다이 사이를 분할하는 스크라이브 라인(scribe line) 내에 오버레이 측정패턴을 형성한다. 일반적으로 오버레이 측정패턴은 전스텝에서 형성된 모버니어(vernier)와 후스텝에서 형성된 자버니어로 이루어지고, 오버레이 측정장비를 이용하여 오버레이 측정패턴을 신호처리하여 오버레이를 측정한다.The overlay accuracy is an index indicating the alignment state between the prestep and the poststep during the process step of the device, and is affected by the error that occurs during mask fabrication and the process and system errors of the device. To measure this overlay accuracy, an overlay measurement pattern is formed in a scribe line that divides between the die and the die. In general, the overlay measurement pattern is composed of a vernier (vernier) formed in the previous step and the vernier formed in the next step, and the overlay measurement pattern is signal-processed using the overlay measurement equipment to measure the overlay.

도 1은 종래의 오버레이 측정패턴을 나타낸 단면도로서, 도 1에 도시된 바와 같이, 오버레이 측정패턴은 반도체 기판(10)의 스크라이브 라인 상에 전스텝에서 형성된 패턴형상, 예컨대 오픈된 사각패턴의 모버니어(20)와, 모버니어(20)의 박스내부에 후스텝에서 형성된 사각 패턴의 자버니어(30)로 이루어진다.1 is a cross-sectional view illustrating a conventional overlay measurement pattern. As shown in FIG. 1, the overlay measurement pattern is a pattern formed in all steps on a scribe line of the semiconductor substrate 10, for example, a vernier of an open square pattern. (20) and a box-shaped vernier (30) formed in a post step inside the box of the vernier (20).

그러나, 상기한 바와 같은 종래의 오버레이 측정패턴에서는, 자버니어의 형성전까지의 열적 스트레스(thermal stress)에 의해 모버니어의 측면이 변형되어, 자버니어의 측면변형을 유발할 뿐만 아니라, 이러한 자버니어와 모버니어의 측면변형은 오버레이 측정장비의 신호처리에 영향을 미치게 된다. 이에 따라, 도 2에 도시된 바와 같이, 모버니어와 자버니어의 측면부분(A, B)의 신호가 오버레이 측정패턴(도 1 참조)과 다른형태로 발생되어, 오버레이 측정 오차가 발생되어 오버레이 정확도가 저하된다.However, in the conventional overlay measurement pattern as described above, the side of the movernier is deformed by the thermal stress until the formation of the vernier, which causes not only the side deformation of the vernier but also such a vernier and the mother. The lateral deformation of the vernier affects the signal processing of the overlay measuring device. Accordingly, as shown in FIG. 2, the signals of the side portions A and B of the movernier and the javernier are generated in a different form from the overlay measurement pattern (see FIG. 1), so that an overlay measurement error is generated and thus the overlay accuracy. Is lowered.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 열적 스트레스에 의한 모버니어와 자버니의 측면변형을 방지하여 오버레이 정확도를 향상시킬 수 있는 반도체 소자의 오버레이 측정패턴을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide an overlay measurement pattern of a semiconductor device capable of improving the overlay accuracy by preventing side deformation of the movernier and zabuni due to thermal stress. have.

도 1은 종래의 반도체 소자의 오버레이 측정패턴을 나타낸 단면도.1 is a cross-sectional view showing an overlay measurement pattern of a conventional semiconductor device.

도 2는 도 1의 신호처리결과를 나타낸 도면.2 is a diagram illustrating a signal processing result of FIG. 1.

도 3은 본 발명의 일 실시예에 따른 반도체 소자의 오버레이 측정패턴을 나타낸 평면도.3 is a plan view showing an overlay measurement pattern of a semiconductor device according to an embodiment of the present invention.

도 4는 도 3의 Ⅳ-Ⅳ'선에 따른 단면도.4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3.

도 5는 본 발명의 다른 실시예에 따른 반도체 소자의 오버레이 측정패턴을 나타낸 단면도.5 is a cross-sectional view illustrating an overlay measurement pattern of a semiconductor device in accordance with another embodiment of the present invention.

도 6은 도 5의 신호처리결과를 나타낸 도면.6 is a diagram illustrating a signal processing result of FIG. 5;

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

100 : 반도체 기판 110 : 모버니어100 semiconductor substrate 110 vernier

110A, 110C : 내부패턴 110B : 외부패턴110A, 110C: Internal pattern 110B: External pattern

120 : 자버니어 200 : 버퍼공간120: Zavernier 200: buffer space

300 : 에치스톱층300: etch stop layer

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 오버레이 측정패턴은 다이와 다이사이를 분할하는 스크라이브 라인을 구비한 반도체 기판과, 스크라이브 라인 상에 전스텝에서 형성되고 일정간격의 버퍼공간을 두고 이격된 오픈된 사각패턴의 내부패턴 및 외부패턴으로 이루어진 모버니어와, 모버니어의 내부패턴 내부에 형성된 사각패턴의 자버니어를 포함한다.The overlay measurement pattern of the semiconductor device according to the present invention for achieving the above object is a semiconductor substrate having a scribe line for dividing between the die and the die, and formed on the scribe line in all steps and spaced apart with a certain space buffer space It includes a vernier consisting of the inner pattern and the outer pattern of the open rectangular pattern, and the vernier of the rectangular pattern formed inside the inner pattern of the vernier.

여기서, 버퍼공간은 상기 모버니어의 열적 스트레스로 인한 변형을 방지하고, 모버니어의 내부패턴과 외부패턴 사이에 단차가 발생된 경우 내부패턴 사이에 에치스톱층을 더 구비한다.Here, the buffer space prevents deformation due to the thermal stress of the vernier, and further includes an etch stop layer between the inner pattern when a step is generated between the inner pattern and the outer pattern of the vernier.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 3은 본 발명의 일 실시예에 따른 반도체 소자의 오버레이 측정패턴을 나타낸 평면도이고, 도 4는 도 3의 Ⅳ-Ⅳ' 선에 따른 단면도로서, 볼록형의 오버레이 측정패턴을 나타낸다.3 is a plan view illustrating an overlay measurement pattern of a semiconductor device according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3, and shows a convex overlay measurement pattern.

도 3 및 도 4에 도시된 바와 같이, 본 발명에 따른 반도체 소자의 오버레이 측정패턴은 반도체 기판(100)의 스크라이브 라인 상에 전스텝에서 형성된 오픈된 사각패턴, 예컨대 일정 간격의 버퍼공간(200)을 두고 이격된 사각틀 형상의 내부패턴(110A) 및 외부패턴(110B)으로 이루어진 모버니어(110)와, 모버니어(110)의 내부 패턴(110B)의 내부에 후스텝에서 형성된 사각 패턴의 자버니어(120)로 이루어진다.3 and 4, the overlay measurement pattern of the semiconductor device according to the present invention is an open rectangular pattern formed in all steps on the scribe line of the semiconductor substrate 100, for example, a buffer space 200 of a predetermined interval The vernier 110 formed of the inner pattern 110A and the outer pattern 110B having a rectangular frame shape spaced apart from each other, and the vernier of the square pattern formed in a post step inside the inner pattern 110B of the vernier 110. Consists of 120.

즉, 모버니어(110)가 버퍼공간(200)을 두고 이격된 내부 및 외부 패턴(110A, 110B)으로 이루어짐에 따라, 자버니어(120)의 형성전에 열적 스트레스로 인한 모버니어(110)의 변형이 버퍼공간(200)에 의해 방지된다.That is, as the movernier 110 is formed of the inner and outer patterns 110A and 110B spaced apart from the buffer space 200, the deformation of the movernier 110 due to the thermal stress before the formation of the zavernier 120. This is prevented by the buffer space 200.

한편, 본 실시예에서는 볼록형의 오버레이 측정패턴의 단면만을 나타냈지만, 오목형의 오버레이 측정패턴에도 적용할 수 있다.On the other hand, in this embodiment, only the cross section of the convex overlay measurement pattern is shown, but it is also applicable to the concave overlay measurement pattern.

도 5는 본 발명의 다른 실시예에 따른 캐패시터의 형성시 오버레이 측정패턴을 나타낸 단면도로서, 본 실시예에서는 모버니어(110)의 오픈된 내부패턴(110C) 및 외부패턴(110B)은, 일 실시예에서와 마찬가지로 외부패턴(110B)과 내부패턴(110C)이 일정간격의 버퍼공간(200)을 두고 이격된다. 또한, 본 실시예에서는 외부패턴(110B)과 내부패턴(110C) 사이의 단차가 발생된 경우, 이를 최소화하기 위하여, 내부패턴(110C) 하부에 에치스톱층(300)을 적용하였다.FIG. 5 is a cross-sectional view illustrating an overlay measurement pattern when a capacitor is formed according to another embodiment of the present invention. In this embodiment, the opened inner pattern 110C and the outer pattern 110B of the Movernier 110 are implemented. As in the example, the outer pattern 110B and the inner pattern 110C are spaced apart from each other by the buffer space 200 at a predetermined interval. In addition, in the present embodiment, when a step between the outer pattern 110B and the inner pattern 110C occurs, an etch stop layer 300 is applied to the lower portion of the inner pattern 110C to minimize the difference.

도 6은 오버레이 장비를 이용하여 도 5의 오버레이 패턴을 신호처리한 결과를 나타낸 도면으로서, 도 6에 도시된 바와 같이, 모버니어와 자버니어의 측면부분(A, B)과 버퍼공간(C)의 신호를 도 5에서와 거의 유사한 패턴 형상으로 얻을 수 있다.FIG. 6 is a diagram illustrating a result of signal processing of the overlay pattern of FIG. 5 by using an overlay device. As shown in FIG. 6, side portions A and B and buffer spaces C of the vernier and zavernier are shown. Can be obtained in a pattern shape almost similar to that in FIG.

상기한 본 발명에 의하면, 모버니어를 일정간격의 버퍼공간을 두고 이격된 사각틀 형상의 외부패턴과 내부패턴으로 이루어지도록 형성함으로써, 자버니어의 형성전에 열적 스트레스로 인한 모버니어의 변형이 버퍼공간에 의해 방지된다. 이에 따라, 오버레이 장비를 이용한 신호처리후 오버레이 측정패턴과 거의 유사한 패턴의 신호를 얻을 수 있으므로, 오버레이 측정오차가 최소화됨으로써, 오버레이 정확도가 향상된다.According to the present invention described above, by forming the vernier to the outer pattern and the inner pattern of the rectangular frame shape spaced apart from the buffer space of a predetermined interval, deformation of the vernier due to thermal stress before the formation of the vernier in the buffer space Is prevented by Accordingly, since a signal having a pattern almost similar to that of the overlay measurement pattern can be obtained after signal processing using the overlay equipment, the overlay measurement error is minimized, thereby improving the overlay accuracy.

또한, 모버니어의 외부 및 내부패턴 사이에 단차가 발생되는 경우에는 내부패턴 하부에 에치스톱층을 적용하여 단차를 방지함으로써, 오버레이 정확도를 더욱더 향상시킬 수 있다.In addition, when a step is generated between the outer and inner patterns of the vernier, an etch stop layer may be applied to the lower part of the inner pattern to prevent the step, thereby further improving the overlay accuracy.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (3)

다이와 다이 사이를 분할하는 스크라이브 라인을 구비한 반도체 기판과,A semiconductor substrate having a scribe line that divides the die and the die; 상기 스크라이브 라인 상에 전스텝에서 형성되고 일정간격의 버퍼공간을 두고 이격된 오픈된 사각패턴의 내부패턴 및 외부패턴으로 이루어진 모버니어와,A vernier formed on the scribe line and formed of an inner pattern and an outer pattern of an open square pattern spaced at a predetermined interval and spaced apart from each other by a buffer space; 상기 모버니어의 내부패턴 내부에 형성된 사각패턴의 자버니어를 포함하는 것을 특징으로 하는 반도체 소자의 오버레이 측정패턴.Overlay measurement pattern of the semiconductor device, characterized in that it comprises a square pattern of the vernier formed in the inner pattern of the movernier. 제 1 항에 있어서, 상기 버퍼공간은 상기 모버니어의 열적 스트레스로 인한 변형을 방지하는 것을 특징으로 하는 반도체 소자의 오버레이 측정패턴.The overlay measurement pattern of claim 1, wherein the buffer space prevents deformation due to thermal stress of the vernier. 제 1 항에 있어서, 상기 모버니어의 내부패턴과 외부패턴 사이에 단차가 발생된 경우 상기 내부패턴 사이에 에치스톱층을 더 구비하는 것을 특징으로 하는 반도체 소자의 오버레이 측정패턴.The overlay measurement pattern of claim 1, further comprising an etch stop layer between the internal patterns when a step is generated between the internal patterns and the external patterns of the vernier.
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