KR100281128B1 - Mask of semiconductor device and manufacturing method thereof - Google Patents

Abstract

In order to provide a mask of a semiconductor device for improving flatness and preventing damage to an active region, and to provide a method of fabricating the same, a mask of a semiconductor device for achieving the above object includes real active regions and peripherals of the real active regions. A plurality of dummy active pattern regions formed in an isolation region formed in the plurality of regions, the plurality of dummy active pattern regions formed in the isolation region around the real active regions, and gate regions extending in one direction, and the portions corresponding to the gate regions are excluded. It is characterized by consisting of active pattern regions.

Description

Mask of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a mask of a semiconductor device and a manufacturing method thereof.

Hereinafter, a mask of a conventional semiconductor device will be described with reference to the accompanying drawings.

FIG. 1A is a plan view combining a first mask defining an isolation region and an active region and a mask defining a gate line, and FIG. 1B is a cross-sectional view of the semiconductor device along the line I-I of FIG. 1A. FIG. 2 is a plan view combining a mask defining a gate line and a mask defining a conventional isolation region and an active region.

The prior art is directed to a mask defining an isolation region and an active region that are used to isolate a device by shallow trench isolation.

The conventional first mask shown in FIG. 1A defines an active region. The active region may include a dense region in which a plurality of memory cells or cell regions are formed, and relatively peripheral circuit regions (for example, input / output circuits) or core regions. It contains sparse regions.

As shown in Fig. 1A, the dense real active area is located to the left of the sparse real active area. Areas other than the active area are defined as areas in which an isolation area is to be formed. In the first mask, the (dense) cell region is patterned to have a narrow real active region, whereas the (coarse) peripheral region or core region is patterned to have a wide real active region. The isolation region of the cell region is defined to have a narrow width, while the isolation region between the cell region and the peripheral region (or core region) is defined to have a wide width. The gate line pattern for forming the gate line is defined to cross a predetermined region above the isolation region.

A method and a structure of a device having a trench isolation region using the conventional first mask as described above will be described with reference to FIGS. 1A and 1B.

First, an initial oxide film and a buffer nitride film are deposited on the semiconductor substrate 1, and the semiconductor substrate 1 on which the isolation region is to be formed is exposed by anisotropically etching the buffer nitride film and the initial oxide film using a conventional first mask.

Thereafter, the semiconductor substrate 1 is etched to a predetermined depth to form a trench. After the insulating material 2 is deposited to fill the trench, the trench is annealed at 1000 ° C. or more to be about the same as the wet etching rate of the insulating material 2 formed by thermal oxidation. In order to improve planarization, a nitride layer or a polysilicon layer is deposited to form a dummy layer. Thereafter, after the photoresist film is applied onto the dummy layer, the photoresist film is selectively patterned by an exposure and development process. The dummy layer is anisotropically etched using the photosensitive film patterned to open the active region as a mask, and the photosensitive film on the isolation region is left.

Alternatively, the dummy layer on the active region may be removed by grinding the insulating material by Chemical Mechanical Polishing (CMP).

The nitride film is removed and ions are implanted into the semiconductor substrate 1 to form a well region in the active region. Then, the oxide film and the polysilicon layer are sequentially deposited on the front surface, and the oxide film and the polysilicon layer are anisotropically etched by using a gate line forming mask defined to cross the active region and the isolation region. ).

In this case, since the insulating material 2 is not completely filled in the wide region of the isolation region, it is difficult to achieve a flat surface in a subsequent process.

In addition, since the insulating material 2 of the large isolation region is removed by chemical mechanical polishing method more than the insulating material 2 of the narrow isolation region, a dishing effect appears.

Next, the conventional second mask illustrated in FIG. 2 further defines a dummy active region in addition to an isolation region between the cell region and the peripheral region (or core region) of the conventional first mask. That is, the dummy active pattern region is a mask pattern region defined to have a predetermined distance from the isolation region.

If the above-described conventional second mask is applied to the element formation, the element can be formed by the same method as the method using the conventional first mask shown in Figs. 1A and 1B. Trench regions are formed at regular intervals. In the conventional second mask, since the trench regions have a predetermined interval, the trench regions may be formed flat without dishing. A plurality of gate lines are formed in one direction to intersect the real active region, the peripheral region, and the dummy active pattern region of the cell region.

As described above, a mask of a conventional semiconductor device and a semiconductor device manufactured using the same have the following problems.

First, when the trench region of the device is formed by using the first mask, a micro-loading effect occurs in which the trench depth and the trench angle are changed due to the difference in the trench width.

Second, when the trench region is formed by using the first mask, when the chemical mechanical polishing method is used, dishing occurs in the isolation region having a wide width, thus making it difficult to form a subsequent process flatly.

Third, when the trench isolation region is planarized using an etch back using a first mask, it is difficult to overcome the steps of the trench isolation region having a narrow width and a wide width.

Fourth, when the device is formed using the second mask, there is a problem in that parasitic capacitance is generated between the gate line and the dummy active region.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a mask of a semiconductor device and a method of manufacturing the same for improving flatness and preventing damage to an active region.

1A is a plan view combining a first mask defining a conventional isolation region and an active region and a mask defining a gate line;

FIG. 1B is a cross-sectional view of the semiconductor device along the line I-I of FIG. 1A

2 is a plan view combining a mask defining a gate line and a mask defining a conventional isolation region and an active region;

3 is a plan view combining a mask defining an isolation region and an active region according to a first embodiment of the present invention, and a mask defining a gate line;

4A to 4E illustrate, in stages, a mechanism for manufacturing a mask of a semiconductor device according to a first embodiment of the present invention.

FIG. 5 is a plan view illustrating a combination of a mask defining an isolation region and an active region, and a mask defining a gate line according to a second embodiment of the present disclosure

Explanation of symbols for the main parts of the drawings

21: Real active pattern area 22: Isolation area

23: first pattern region 24: second pattern region

25: first dummy pattern area 26: third pattern area

27: fourth pattern region 28: second dummy pattern region

29: gate line pattern area 30, 60: dummy active pattern area

50: first dummy active pattern 52: second dummy active pattern

55: edge area of N well

The mask of the semiconductor device according to the present invention for achieving the above object is a plurality of dummy active pattern regions formed in the real active regions, the isolation region formed around the real active regions, the isolation region around the real active regions The plurality of dummy active pattern regions may include gate regions extending in one direction and exclude portions corresponding to the gate regions.

The method of fabricating a mask of a semiconductor device configured as described above comprises the steps of forming real active regions, defining the real active pattern regions having a current pattern, and increasing the area of the current pattern by a first prescribed amount to increase the current. Forming a first pattern region at each periphery of the pattern, defining a second pattern region at each periphery of the current pattern by increasing the area of the current pattern by a second prescribed amount less than the first prescribed amount Removing the second pattern region from the first pattern region to form a dummy pattern region, defining a dummy pattern region having the current pattern, and forming the first pattern region from the third step. Repeatedly forming the pattern region to form a plurality of dummy pattern regions, and forming the plurality of dummy pattern regions. Defining a gate line pattern region in an area intersecting the real active regions, removing the dummy pattern regions located in the gate line pattern regions from the combined dummy pattern regions to form a set of dummy active pattern regions. And forming a mask of the semiconductor device by synthesizing the real active pattern regions and the set of dummy active pattern regions.

Referring to the accompanying drawings, a mask and a method of manufacturing the semiconductor device of the present invention will be described.

3 is a plan view combining a mask defining an isolation region and an active region and a mask defining a gate line according to a first embodiment of the present invention.

4A to 4E are diagrams illustrating, in stages, a mechanism for manufacturing a mask of a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a plan view illustrating a combination of a mask defining an isolation region and an active region and a mask defining a gate line according to a second embodiment of the present invention.

As shown in FIG. 3, a mask of a semiconductor device according to the present invention includes a real active pattern region 21 for forming an active region in a cell region and a peripheral region (or core region). The real active pattern region 21 of the cell region was formed in a narrow width, whereas the real active pattern region 21 of the peripheral region was formed in a wide width. The dummy active pattern region 30 is isolated from each of the real active pattern regions 21 at regular intervals, and is isolated from each other and is repeatedly formed in a rectangular shape around the real active pattern region 21. Here, the dummy active pattern region 30 is formed in an isolation region between the real active pattern region 21 of the cell region and the real active pattern region 21 of the ferry region.

In addition, the dummy active pattern region 30 is formed to remove a portion to cross the gate line pattern region 29. The width of each of the plurality of dummy active pattern regions 30 is equal to or greater than the minimum width of the real active pattern region 21. The width of the gate line pattern region 29 is equal to or greater than the minimum width of the final isolation region 22 (see FIG. 4A).

In the method of fabricating a mask of the semiconductor device of the present invention having the above configuration, as shown in FIG. 4A, the active active region is defined in the cell region and the peripheral region to define the real active pattern region 21 in each active region. Form. In this case, the real active pattern region 21 of the peripheral region has a wider width than the real active pattern region 21 of the cell region. The isolation region 22 is a region excluding the real active pattern region 21 and has a wide width between the cell region and the peripheral region.

Next, as shown in FIG. 4B, the first pattern region 23 is over-sized by K than the real active pattern region 21. The second pattern region 24 is defined by downsizing by W than the first pattern region 23. Subsequently, the first dummy pattern region 25 is formed by subtracting the second pattern region 24 from the first pattern region 23.

As illustrated in FIG. 4C, the third pattern region 26 is oversized and defined than the first pattern region 23, and the fourth pattern region 27 is downsized than the third pattern region 26. To define. Subsequently, the second dummy pattern region 28 is formed by subtracting the fourth pattern region 27 from the third pattern region 26.

This process is repeated until a plurality of desired dummy pattern regions are formed.

Here, the first dummy pattern region 25 and the second dummy pattern region 28 have a width greater than or equal to the minimum width of the real active pattern region 21.

Thereafter, the gate line pattern region 29 for forming the gate line is defined to have a width of 't'.

Next, as shown in FIG. 4D, the plurality of dummy pattern regions except the real active pattern region 21 and the gate line pattern region 29 are ORed together, and then the gate line pattern region 29 is removed from the plurality of dummy pattern regions. The dummy active pattern region 30 is formed by subtraction. The gate line pattern region 29 has a width that can electrically isolate the plurality of dummy active pattern regions 30.

As shown in FIG. 4E, the dummy active pattern region 30 of FIG. 4D and the real active pattern region 21 of FIG. 4A are logically combined to form a final active pattern formation mask.

Next, a method for manufacturing a semiconductor device having a trench isolation region using the mask of FIG. 4E will be described. (Not shown in the drawing)

An initial oxide film and a buffer nitride film are formed on a semiconductor substrate. Afterwards, the buffer nitride film and the initial oxide film are anisotropically etched to expose the semiconductor substrate to form the isolation region using the mask of the present invention. The semiconductor substrate is etched to a predetermined depth to form a trench region. After the insulating material is deposited to fill the trench region, the insulating material is etched back using a reactive ion etching (RIE) method or flatly polished using the chemical mechanical polishing method. The buffer nitride film and the buffer oxide film are removed to expose the semiconductor substrate in the active region. In addition, a well region is formed by implanting ions into the semiconductor substrate, and a channel ion implantation process is performed in the active region. Next, an oxide film and a polysilicon layer are deposited on the entire surface and anisotropically etched to form a gate oxide film and a gate electrode.

FIG. 5 is a plan view illustrating a combination of a mask defining an isolation region and an active region and a mask defining a gate line according to a second exemplary embodiment of the present invention. At least two dummy region patterns are used.

First, the dummy active pattern formed in the relatively large area of the isolation region must be sufficiently flattened on the wafer surface to form the shallow trench isolation region. Therefore, the chemical mechanical polishing process creates a uniform surface.

First, the dummy active pattern region in the first embodiment of the present invention is formed using the real active pattern region. The dummy active pattern area in the first embodiment serves as a loading pattern for controlling the critical dimension of the circuit element.

However, the first embodiment in which the formation of the dummy active pattern by synthesis by calculation and editing as described above has a problem of delaying the photolithography process.

In contrast, in the second embodiment, the first dummy active pattern 50 is made through rapid calculation and formation while maintaining a uniform dummy pattern density, and the second dummy active pattern 52 provides a functional device. It is to adjust the critical dimension of the device.

The first dummy active pattern 50 having a rectangular array structure is made in the center of the chip, which is called dummy active zero. The size of the rectangle and the spacing between the rectangles depends on the process design rules. For example, the size of the rectangular first dummy active pattern 50 is 2 µm in width and 20 µm in length, and the interval therebetween is 4 µm.

In addition, the second dummy active pattern 52 is formed by repeating two dummy active area pattern areas twice to surround the real active pattern area 21.

That is, as shown in FIG. 5, in order to form the plurality of dummy active pattern regions 60, the plurality of first and second dummy active patterns 50 and 52 and the gate line pattern regions except for the real active pattern regions 21. The plurality of dummy pattern regions of the gate line pattern region 29 are subtracted from the logical sum of (29).

Subsequently, an ion implantation process is performed to create a source / drain region, and an ion implantation mask is formed in the real active region. The photosensitive film is patterned to open the real active region. At this time, the photoresist is not opened in other areas on the isolation area. During ion implantation, a positive charge is generated and flows into the open area of the photoresist film. At this time, the gate oxide film may be degraded by the positive charge accumulated on the real active region. During the ion implantation process in the dummy active region, the positive charge also flows into the open portion of the dummy active region. In order to solve such a charging problem, an ion implantation mask is formed not only in the real active region but also in the dummy active region.

The dummy active patterns in the first and second embodiments of the present invention can be arbitrarily adjusted to increase the reliability and functionality of the device. After the formation of the dummy active region is completed, dummy pieces (Slivers) smaller than the allowable minimum active size may be generated. The presence of such dummy slivers can cause problems in part during the inspection of the manufactured mask.

To solve the problem caused by these dummy pieces, downsize the final data and then oversize it again to recover the data. Any dummy pieces downsized for vertical or horizontal lines or dots are removed before oversizing to recover the final data.

Also, the dummy active region formed on the isolation region between the wells reduces the reliability of the device. For example, if a dummy active pattern is generated in the edge region of the N well while generating the dummy active pattern, an electrical short occurs when a salicide process is performed between the N well and the P well in the dummy active region. In other words, the salicide metal formed on the dummy active pattern on the edge region 55 of the N well is interconnected between the N-type and P-type active regions in the dummy active region. One way to solve this problem in an interwell is to create or delete data from scratch to form a dummy active pattern close to the edge of the interwell. For example, a dummy active region is formed by patterning in a path having a width of 1 탆 on the edge of the interwell. The path is generated by subtracting the finally generated dummy active data from the data obtained by subtracting the N well edge by 0.5 μm from the value oversized by 0.5 μm.

In other words, Fig. 5 shows a mask having a dummy active region in accordance with a process design rule defined for fabrication of a device.

In order to manufacture such a mask, first, the data is positioned at the center of the wafer or chip to form a dummy active pattern 0 having a rectangular dummy active array structure. The rectangular size (horizontal, vertical length) and the space (gap) between the rectangles are changed depending on the process design rules.

The real circuit active patterns RCAPs are oversized to form the dummy active pattern 1 (eg, about 3.8 μm at each corner). The dummy active pattern 1 is formed by subtracting a rectangular dummy active pattern 0 in order to remove the dummy active regions DARs in the upsized real circuit active patterns.

Next, a dummy active pattern 2 'is formed by oversizing the real circuit active pattern RCAP 1.6 mu m, and a dummy active pattern 2 "is made by oversizing the real circuit active pattern RCAP 0.6 mu m. The dummy active pattern 2 is subtracted from 'to form a dummy active pattern 2. The dummy active region 2 is formed around the real active pattern region.

Next, dummy active pattern 3 'is made by oversizing the real circuit active pattern by 3.2 mu m, and dummy active pattern 3' is made by oversizing the real circuit active pattern by 2.2 mu m. Thereafter, dummy active pattern in dummy active pattern 3 'is made. The dummy active pattern 3 is formed by subtracting 3 ". The dummy active pattern 3 is positioned around the real circuit active patterns.

The dummy active patterns 2 and 3 serve as a loading pattern for improving the photolithography process to control the critical dimension of the device.

The edges of the N well are then oversized by 0.5 mu m at each corner and downsized by 0.5 mu m at each corner.

The dummy active pattern 4 is formed by subtracting 0.5 µm downsized data from 0.5 µm oversized data. The dummy active pattern 4 is formed along the N well edge periphery.

Thereafter, a dummy active pattern 5 is formed to cover a process monitoring pattern or an unnecessary dummy active pattern region.

Each edge of the gate electrode layer (for example, the edge of the poly layer) is oversized by 0.15 mu m to form a dummy active pattern 6.

The dummy active patterns 1, 4, and 5 are subtracted from the dummy active pattern 0 to form a dummy active pattern 7.

The final active pattern may be represented as (RCAP) ∪ {DAP2∪DAP3∪DAP7-DAP6}. Here, RCAP is a real circuit active pattern, DAP2 is a dummy active pattern 2, DAP3 is a dummy active pattern 3, DAP7 is a dummy active pattern 7, and DAP6 is a dummy active pattern 6. In other words, the dummy active patterns 2 and 3 and the dummy active pattern 6 excluding the gate electrode pattern are added together and merged together with the original real circuit active patterns.

After the final active patterns are formed as described above, the size of the merged active patterns is reduced by 0.07 μm and then increased by 0.07 μm in order to remove dummy active pieces (Slivers).

The mask of the semiconductor device of the present invention as described above and a method of manufacturing the same have the following effects.

First, when the trench isolation region is formed using the mask of the present invention, a trench having a constant width can be obtained, and thus CMP can be performed regardless of the mask pattern integration degree.

Second, when forming the trench isolation region using the mask of the present invention, planarization by reactive ion etching (RIE) instead of CMP can simplify the process and improve the uniformity of subsequent processes.

Third, when the trench region is formed using the mask of the present invention, a trench having a constant width can be obtained, thereby eliminating a micro loading phenomenon in which the trench depth and the trench sidewall angle are changed.

Fourth, since no gate line is formed in the dummy active pattern region in the isolation region, parasitic capacitance can be prevented from occurring.

Fifth, since the real active pattern region and the dummy active pattern region are manufactured and synthesized separately, difficulty in mask correction can be eliminated.

Sixth, when the integrated plasma chemical vapor deposition method is applied, damage due to excessive sputtering on the edge portion of the real active pattern region or clipping of the real active pattern region can be prevented.

Claims (20)

Real active areas, An isolation region formed around the real active regions, A plurality of dummy active pattern regions formed in an isolation region around the real active regions; And a plurality of dummy active pattern regions having gate regions extending in one direction and excluding portions corresponding to the gate regions. The mask of claim 1, wherein real active patterns are formed in the real active regions, and gate patterns are formed in the gate regions. The mask of claim 1, wherein the dummy active pattern regions are isolated from the real active regions, and the gate regions intersect the real active patterns. The mask of claim 3, wherein the dummy active pattern regions are formed at predetermined intervals from each other. The mask of claim 1, wherein each of the plurality of dummy active pattern regions has a width not less than a minimum width of the real active regions and fills the isolation region. The mask of claim 1, wherein the gate region is formed to have a width that is basically electrically isolated to reduce the parasitic capacitor. The mask of claim 1, wherein the gate area is formed to have a width not smaller than a minimum width of the dummy active pattern areas. Forming real active regions, Defining the real active pattern regions having a current pattern; Increasing the area of the current pattern by a first prescribed amount to form a first pattern region around each of the current patterns, Increasing the area of the current pattern by a second prescribed amount less than the first prescribed amount to define a second pattern region around each of the current patterns, Removing the second pattern region from the first pattern region to form a dummy pattern region; Defining a dummy pattern region having the current pattern; Repeatedly forming the first pattern region from the third step to the fifth step of forming the dummy pattern region to form a plurality of dummy pattern regions; Summing the plurality of dummy pattern regions; Defining gate line pattern regions in an area intersecting the real active regions; Defining a set of dummy active pattern regions by removing dummy pattern regions located in the gate line pattern regions from the combined dummy pattern regions; And forming a mask of the semiconductor device by synthesizing the set of the real active pattern areas and the dummy active pattern areas. 9. The method of claim 8, wherein the dummy active pattern regions are isolated from the real active regions, and the set of dummy active pattern regions is formed to fill regions except for the real active regions. Way. 10. The method of claim 8, wherein the real active regions define real active pattern regions that are not larger than the width of the dummy active pattern regions, and the gate line pattern regions have a predetermined width and extend along a predetermined direction. Method of manufacturing a mask of a semiconductor device. 10. The method of claim 8, wherein the gate line pattern regions have a width equal to a basic distance for electrical isolation to reduce parasitic capacitance. The method of claim 8, wherein an isolation region is defined outside the real active regions, and wherein the plurality of dummy pattern regions form a first dummy region pattern. Forming a second dummy region pattern made of dummy active patterns around the first dummy region pattern to fill the isolation region; Removing the dummy active pattern located in the gate line pattern regions in the second dummy pattern regions to define a set of additional dummy active pattern regions; And synthesizing the set of real active pattern regions and the set of dummy active pattern regions and the set of additional dummy active pattern regions to form the semiconductor device mask. The method of claim 12, wherein the second dummy region pattern is formed by defining a center point of a mask and determining an array of dummy active patterns having a rectangular shape having a predetermined size and spacing. A method of manufacturing a mask of a semiconductor device, characterized in that. Forming real active regions on the semiconductor substrate, the outer active regions being defined as isolation regions; Forming a first dummy region pattern around the real active regions; Forming a second dummy region pattern around the first dummy region pattern to fill the isolation region with dummy active patterns; Defining gate line pattern regions intersecting the real active regions; Removing the dummy active pattern located in the gate line pattern areas from the first and second dummy area patterns to define a set of dummy active pattern areas; And combining the real active pattern regions with the set of dummy active pattern regions to form a mask of the semiconductor device. 15. The method of claim 14, wherein the formation of the first dummy region pattern comprises: defining real active regions having a current pattern, each of the first around the current pattern by increasing the current pattern area by a first prescribed amount; Forming a pattern region, defining a second pattern region around the current pattern by increasing the area of the current pattern by a second prescribed amount smaller than the first prescribed amount, Removing a second pattern region from the first pattern region to form a dummy pattern region, defining a dummy pattern region having the current pattern, and forming the first dummy region pattern; And repeatedly forming the dummy pattern region having the current pattern in forming the region. Method of operation. 15. The semiconductor device of claim 14, wherein the second dummy region pattern is formed by defining a center point of the mask and determining an array of rectangular active patterns of rectangular shape having a prescribed size and spacing. Method for manufacturing a mask of the device. The method of claim 16, wherein the dummy active patterns are isolated from the real active region, the rectangular dummy active patterns are 2㎛ horizontally 20㎛ vertical, the interval between them is 4㎛ Method of manufacturing a mask of a semiconductor device. 15. The method of claim 14, wherein the gate line pattern regions are formed to have a width equal to a basic distance to enable electrical isolation to reduce parasitic capacitance. The semiconductor device of claim 14, further comprising removing a region having a predetermined shape covering the inter-well edges from the set of the dummy active pattern regions in the dummy active patterns. How to make a mask. 15. The method of claim 14, further comprising removing dummy pieces from the set of dummy active patterns.