KR100272534B1 - Semiconductor memory cell and method for manufacturing the same - Google Patents

Abstract

According to the present invention, four active regions are defined by two lines orthogonal to each other, and the box-shaped first pattern and the first pattern partially contact each active region while exposing the orthogonal portions of the active regions and the ends of the active regions. In the semiconductor memory cell and a method of manufacturing the same, a word line of a second pattern of partially contacted lines is formed, so that four memory cell transistors are formed on one bit line and four memory cell transistors are formed on one word line. It is about.

A semiconductor memory cell of the present invention and a method of fabricating the same have a substrate in which first, second, third and fourth active regions having different threshold voltages are defined by two orthogonal lines, orthogonal to the active regions on the substrate. A box-shaped first pattern partially contacting each active region while exposing a portion and an end portion of each active region and a line-shaped second pattern formed on the substrate and partially contacting the first pattern; Forming a word line, forming a first ILD layer having a first contact hole formed at an end of each active region on a semiconductor substrate including the word line, and forming a first ILD layer including each of the first contact holes. A second ILD layer having a second contact hole formed at orthogonal portions of the active regions on a first ILD layer including the capacitors; And forming a bit line on a second ILD layer, the bit line partially contacting the first active region and the first pattern of the word line and being orthogonal to the second pattern of the word line and connected to the second contact hole. .

Description

Semiconductor memory cell and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell and a method for manufacturing the same, and more particularly, to a semiconductor memory cell for improving the degree of integration of a memory cell and a method for manufacturing the same.

The DRAM (Dynamic Random Access Memory) memory cell according to the prior art has a first shape on a semiconductor substrate (not shown) in which an active region 11 having a line shape in one direction is defined in a general form as shown in FIG. 1. Two word lines 12 formed with an insulating film interposed therebetween have a predetermined interval and are orthogonal to the active region 11, and are formed with a second insulating film interposed on the word line 12. The bit line 13 connected to the active region 11 is shifted and parallel to the active region 11 and is positioned perpendicular to the word line 12. In addition, a capacitor contact hole 14 is formed between both ends of the active region 11 and the word line 12.

In this case, in the memory cell transistor of the DRAM according to the related art, two transistors are formed by two word lines 12.

However, in the conventional semiconductor memory cell and its manufacturing method, since the active region is defined as one line shape, two memory cell transistors are formed on one bit line, and one memory cell transistor is formed on one word line, thereby integrating the device. There was a problem that is lowered.

The present invention has been made in order to solve the above problems, four active regions are defined by two lines orthogonal to each other, and the box partially contacting each active region while exposing the orthogonal region of the active regions and the end portion of each active region. Since the word pattern of the first pattern of the shape and the second pattern of the line shape partially contacting the first pattern is formed, four memory cell transistors are formed on one bit line, and four memory cell transistors are formed on one word line. It is an object of the present invention to provide a semiconductor memory cell and a method of manufacturing the same.

1 is a plan view showing a DRAM memory cell according to the prior art

2 is a plan view illustrating a DRAM memory cell according to an embodiment of the present invention.

3 is a plan view illustrating a plurality of DRAM memory cells according to an embodiment of the present invention.

4A through 4H are cross-sectional views illustrating a method of manufacturing a DRAM memory cell according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

31: active area 31a: first active area

31b: first active region 31c: first active region

31d: first active region 32: word line

33: open area of the second photosensitive film 34: open area of the second photosensitive film

35: open area of the fourth photosensitive film 36: open area of the fourth photosensitive film

37: first contact hole 38: bit line

The semiconductor memory cell of the present invention includes a substrate in which first, second, third, and fourth active regions having different threshold voltages are defined by two orthogonal lines, orthogonal portions of the active regions on the substrate, and the respective angles. A word line formed of a box-shaped first pattern partially contacting each active region while exposing an end portion of an active region and a second pattern of line shape formed on the substrate and partially contacting the first pattern; A plurality of capacitors formed on a first ILD layer having a first contact hole formed at an end of each active region on the semiconductor substrate including the word line, and on a first ILD layer including each of the first contact holes A second ILD layer having a second contact hole formed at orthogonal portions of the active regions on a first ILD layer including the capacitors, and the second ILD layer formed on the second ILD layer. And a bit line partially contacting the active region and the first pattern of the word line and orthogonal to the second pattern of the word line and connected to the second contact hole.

In the method of manufacturing a semiconductor memory cell of the present invention, the method may further include forming an isolation layer on a substrate such that the first, second, third, and fourth active regions are defined by two lines orthogonal to each other. A word line having a box-shaped first pattern partially contacting each active region and a line-shaped second pattern partially contacting the first pattern while exposing a portion and an end portion of each active region on the substrate; Forming different threshold voltages in the first, second, third, and fourth active regions so that the threshold voltages of the active regions are different; Forming a first ILD layer having a first contact hole formed at an end of each active region, and forming a capacitor on the first ILD layer including each of the first contact holes; Forming a first ILD layer having a second contact hole formed at orthogonal portions of the active regions on a first ILD layer including capacitors, the first ILD layer being connected to the second contact hole and connected to the one active region and the word line; And forming a line-shaped bit line partially contacting the first pattern and orthogonal to the second pattern of the word line, on the second ILD layer.

A preferred embodiment of a semiconductor memory cell and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a DRAM memory cell according to an embodiment of the present invention, Figure 3 is a plan view showing a plurality of DRAM memory cells according to an embodiment of the present invention, Figures 4a to 4h is an embodiment of the present invention The process sectional drawing which showed the manufacturing method of DRAM memory cell according to this is shown.

As shown in FIGS. 2 and 3, a DRAM memory cell according to an exemplary embodiment of the present invention may include first, second, third and fourth active regions 31a and 31b having different threshold voltages by two orthogonal lines. A semiconductor substrate (not shown) defined as 31c and 31d, an orthogonal portion H of the active regions 31 and the first, second, third and fourth active regions 31a and 31c on the semiconductor substrate. 31b, 31c, and 31d exposing end portions of the box-shaped first pattern partially formed in contact with the active regions and the line-shaped second pattern formed on the semiconductor substrate and partially in contact with the first pattern. A first line formed at an end of the first, second, third, and fourth active regions 31a, 31b, 31c, and 31d on the semiconductor substrate including the word line 32 and the word line 32. A first ILD layer having a contact hole 37 and a plurality formed on the first ILD layer including each of the first contact holes 37. A second ILD layer having a second contact hole formed at an orthogonal portion H of the active regions on a first ILD layer including the capacitors, and the first active region on the second ILD layer. 31a) and a bit line 38 partially contacting the first pattern of the word line 32 and orthogonal to the second pattern of the word line 32 and connected to the second contact hole.

At this time, since the threshold voltages of the first, second, third, and fourth active regions 31a, 31b, 31c, and 31d are different from each other, four memory cell transistors are formed in the single word line 32. That is, four memory cell transistors are formed in the one bit line 38.

In the method of manufacturing a DRAM memory cell according to an exemplary embodiment of the present invention, as shown in FIG. 4A, the active region 31 is formed of two first or second active regions 31a and 31b by two lines orthogonal to each other. A field oxide film (not shown) is selectively formed on a semiconductor substrate (not shown) so as to be defined as 31c and 31d.

As shown in FIG. 4B, polycrystalline silicon and a first photoresist film are formed on a semiconductor substrate including the field oxide film, and the first photoresist film is selectively exposed and developed so that the first photoresist film remains only at a portion where a word line is to be formed by a photolithography process.

The polycrystalline silicon is selectively etched using the selectively exposed and developed first photoresist layer to form a word line 32, and then the first photoresist layer is removed.

In this case, the word line 32 exposes the orthogonal portions H of the active regions 31 and the end portions of the active regions 31 and has a box-shaped first pattern partially contacting the active regions 31. Pattern) and a line-shaped second pattern partially contacting the first pattern.

As shown in FIG. 4C, a second photoresist film is coated on the entire surface including the word line 32 and the second photoresist film is removed so as to be removed only at the junction between the first active region 31a and the word line 32. Etch it.

The first threshold voltage control ion is injected into the first active region 31a through the open region 33 of the selective photo-etched second photoresist layer.

As shown in FIG. 4D, after removing the second photoresist film, a third photoresist film is coated on the entire surface including the word line 32, and the third photoresist film is formed on the second active region 31b and the word line 32. Select photo etch so that only the junction is removed.

In addition, a second threshold voltage regulating ion is injected into the second active region 31b through the open region 34 of the selected photo-etched third photoresist layer.

As shown in FIG. 4E, after the third photoresist film is removed, a fourth photoresist film is coated on the entire surface including the word line 32, and the fourth photoresist film is formed on the third active region 31c and the word line 32. Select photo etch so that only the junction is removed.

In addition, a third threshold voltage regulating ion is injected into the third active region 31c through the open region 35 of the fourth photoresist etched by the selected photo.

As shown in FIG. 4F, after the fourth photoresist film is removed, a fifth photoresist film is coated on the entire surface including the word line 32, and the fifth photoresist film is applied to the fourth active region 31d and the word line 32. Select photo etch so that only the junction is removed.

In addition, a fourth threshold voltage regulating ion is implanted into the fourth active region 31d through the open region 36 of the fifth photosensitive film etched through the selective photo.

As shown in FIG. 4G, after the fifth photoresist layer is removed, the first, second, third, and fourth active regions 31a, 31b, 31c, and 31d are formed on the semiconductor substrate including the word line 32. A first ILD layer (not shown) is formed having a first contact hole 37 formed at an end portion.

As shown in FIG. 4H, a capacitor (not shown) is formed on the first ILD layer including each of the first contact holes 37, and the orthogonal portions of the active regions 31 are formed on the first ILD layer including the capacitors. A second ILD layer (not shown) having a second contact hole formed in (H) is formed.

And a bit line 38 partially contacting the first active region 31a and the first pattern of the word line 32 and orthogonal to the second pattern of the word line 32 and connected to the second contact hole. Is formed on the second ILD layer.

In this case, the threshold voltages of the first, second, third, and fourth active regions 31a, 31b, 31c, and 31d may be increased by implanting different first, second, third, and fourth threshold voltage adjustment ions. Since they are different from each other, four memory cell transistors are formed in the single word line 32. That is, four memory cell transistors are formed in the one bit line 38.

Here, the first, second, third, and fourth active regions 31a, 31b so that the threshold voltages of the first, second, third, and fourth active regions 31a, 31b, 31c, and 31d are different from each other. The steps of injecting the first, second, third and fourth threshold voltage ions into the respective ones 31c and 31d may be performed before the word line 32 is formed.

In the semiconductor memory cell and a method of manufacturing the same, four active regions are defined by two lines orthogonal to each other, and a box shape partially contacting each active region while exposing orthogonal portions of the active regions and end portions of the active regions is formed. Since a word line of a line-shaped second pattern partially contacting the first pattern and the first pattern is formed, four memory cell transistors are formed on one bit line and four memory cell transistors are formed on one word line. There is an effect of improving the degree of integration of the device than the technology.

Claims (2)

A substrate in which first, second, third, and fourth active regions having different threshold voltages are defined by two orthogonal lines; A box-shaped first pattern formed on the substrate and partially contacting each active region while exposing orthogonal portions of the active regions and end portions of the active regions on the substrate and partially formed on the substrate. A word line formed in a line-shaped second pattern in contact with each other; A first ILD layer formed on the semiconductor substrate including the word line and having a first contact hole formed at an end of each active region; A plurality of capacitors formed on a first ILD layer including each of the first contact holes; A second ILD layer formed on the first ILD layer including the capacitors and having a second contact hole formed at orthogonal portions of the active regions; And a bit line on the second ILD layer, the bit line partially contacting the first active region and the first pattern of the word line and being orthogonal to the second pattern of the word line and connected to the second contact hole. A semiconductor memory cell characterized by the above. Selectively forming an isolation layer on the substrate such that the first, second, third, and fourth active regions are defined by two lines orthogonal to each other; A word line having a box-shaped first pattern partially contacting each of the active areas and a line-shaped second pattern partially contacting the first pattern while exposing orthogonal portions of the active regions and end portions of the active regions. Forming on the substrate; Implanting different threshold voltage control ions into the first, second, third, and fourth active regions so that the threshold voltages of the active regions are different from each other; Forming a first ILD layer having a first contact hole formed at an end of each active region on the substrate including the word line, and forming a capacitor on the first ILD layer including each first contact hole; Forming a first ILD layer having a second contact hole formed at orthogonal portions of the active regions on a first ILD layer including the capacitors; Forming a line-shaped bit line connected to the second contact hole and partially contacting the one active region and the first pattern of the word line and orthogonal to the second pattern of the word line, on the second ILD layer Method for manufacturing a semiconductor memory cell, characterized in that consisting of.