KR100264785B1 - ATM random cell generation and test device - Google Patents

Abstract

PURPOSE: An apparatus for generating and testing ATM(Asynchronous Transfer Mode) random cells is provided to generate the test ATM cells and to feed back the ATM cells, in a line interface module, so as to perform the testing at low cost, regardless of an ATM cell speed. CONSTITUTION: A utopian interface unit(71) interfaces an ATM(Asynchronous Transfer Mode) cell switch with ATM cells through a utopian interface. A cell monitor(72) monitors a state of cell interfaced with a physical layer converter(73), and checks a state of a test cell and outputs a state result value to a monitor. A function selector(74) selects a normal operation state and a test function, according to a user function selection. If the test function is selected, a test cell generator(75) generates the test cell for checking a line interface module state. If the test function is selected, a cell output controller(76) interrupts a normal cell output of the cell monitor(72), and transmits the test cell to the physical layer converter(73). The physical layer converter(73) transmits cells outputted from the cell monitor(72) to a user, under control of the cell output controller(76). The physical layer converter(73) feeds back the test cell and transmits the test cell to the cell monitor(72).

Description

ATM random cell generation and test device

The present invention relates to an Asynchronous Transfer Mode (ATM) cell test, and in particular, generates a test ATM cell in the Line Interface Module itself and feeds it back to the Line Interface Module to The present invention relates to an ATM random cell generation and testing apparatus for testing.

In general, when a development board using ATM technology is made, separate test equipment is used to test the function.

That is, the test equipment generates an ATM cell and delivers it to the development board. The development board processes the input ATM cell and then delivers the processed ATM cell to the test equipment. The test equipment compares the ATM cell received feedback with the ATM cell previously sent to the development board to check whether the development board is normal by its identity, and monitors the result so that the inspector can check whether the development board is abnormal. Be aware.

Hereinafter will be described the operation of the conventional ATM cell tester for the ATM cell test as described above.

1 is a schematic configuration diagram of a general ATM switch.

As shown therein, first and second line interface module units 10 and 40 for interfacing ATM cells with external users (PCs, W / S (workstations)), and the first and second lines. An ATM cell switching unit 20 for switching mutual data in the interface module unit 10 and 40, and a controller 30 for controlling cell switching of the ATM cell switching unit 20 and controlling overall system operation. It consisted of

In the general ATM exchanger configured as described above, the user's PC or W / S is connected to the first line interface module 11 in the first line interface module unit 10, and the user sends an ATM cell. The switching unit 20 checks the reception position of the transmitted ATM cell under the control of the controller 30 and switches the ATM cell to the second line interface module unit 40 corresponding to the receiver so that the corresponding receiver can receive it. To deliver. The first line interface module 41 in the second line interface module unit 40 (assuming a line interface module corresponding to the receiver) transmits the transferred ATM cell to a PC or workstation of a connected user (receiver). Interface to.

Similarly, the ATM cell transmitted by the user (receiver) is reversed from the above process, that is, through the first line interface module 41, the ATM cell switching unit 20, and the first line interface module 11. It is delivered to the other user (PC or W / S).

In a general ATM switch that performs this operation, a new line interface module should be tested when it is developed. FIG. 2 is a block diagram of a conventional ATM cell test apparatus for testing a newly developed line interface module. .

As shown here, mutual ATM cells of the first and first 'line interface modules 11 and 41 and the first and first' line interface modules 11 and 41 for interfacing the ATM cells are shown. An ATM cell switching unit 20 for switching, a controller 30 for controlling the ATM cell of the ATM cell switching unit 20, and controlling the overall operation of the system, and connected to the first 'line interface module 41. And the test equipment 60 for checking the state of the first 'line interface module 41.

The operation of the line interface module test apparatus of the conventional ATM switch configured as described above is as follows.

First, the test equipment 60 generates an ATM cell generated by itself to test the state of the first 'line interface module 41 (assuming a newly developed line interface module), and then, The ATM cell is delivered to the 1 'line interface module 41.

The first 'line interface module 41 converts the transmitted optical ATM cell into an electrical signal and then transmits the converted optical ATM cell to the ATM cell switching unit 20 through an internal signal line, and the ATM cell switching unit 20 is a controller. Switching the input ATM cell by the control of (30).

The ATM cell thus switched is delivered to the first 'line interface module 41 again, and the first' line interface module 41 converts it into an optical signal, and then again the test apparatus 60 through the optical cable 62. Pass it on.

The test equipment 60 compares the data transmitted first with the received data and monitors the result on its own monitor (not shown) to allow the inspector to check the state of the newly developed board.

3 is a diagram illustrating an internal configuration of the first line interface module 41 of FIG. 2.

Here, reference numeral 41a is a utopia interface unit which is connected to the ATM cell switching unit 20 and mutually interfaces ATM cells through a utopia interface, and 41b is a mutual transmission in the utopia interface unit 41a and the physical layer conversion unit 41c. Is a cell monitoring unit that monitors the state of a received ATM cell and delivers the result to the monitor 50. 41c is a physical layer conversion unit that is connected to a user (PC or W / S) and is in charge of the interface of an ATM cell. .

The line interface module having such a configuration converts the test optical ATM cell transmitted from the test equipment 60 into an electrical signal in the physical layer converter 41c and transmits the electrical signal to the cell monitor 41b. 41b transmits the test cell to the utopia interface unit 41a after checking the cell state. The utopia interface unit 41a transfers the test cell to the ATM cell switching unit 20 through the utopia interface, and the utopia interface unit 41a retransmits the test ATM cell switched by the ATM cell switching unit 20 again. It delivers to the monitoring part 41b. The cell monitoring unit 41b checks the state of the test cell and transfers the test cell to the physical layer converting unit 41c. The physical layer converting unit 41c converts the data into optical data and then, via the optical cable. To the test equipment.

However, such a conventional ATM cell test apparatus does not have a function of generating an ATM cell in its own line interface module. Therefore, when a board is newly developed, a board developed by using an expensive test equipment is separately used for board testing. Since it is necessary to test, the board test is not only complicated, but also has a problem of being expensive due to the use of expensive test equipment.

In addition, when the signal transmission and reception method between the test equipment and the line interface module is not an optical signal method, a separate device is required for the data interface between the test equipment and the line interface module.

Accordingly, the present invention has been proposed to solve various problems occurring in the test apparatus of the conventional ATM switch as described above.

An object of the present invention is to provide an ATM random cell generation and test apparatus capable of testing an ATM cell by generating a test ATM cell in a line interface module itself and feeding it back to a line interface module. have.

Apparatus according to the present invention for achieving the above object,

A utopia interface unit for interfacing the ATM cell switching unit and the ATM cell through the utopia interface;

A cell monitoring unit for monitoring a state of a cell interfaced with the utopian interface unit and a physical layer conversion unit connected to a user, and checking a state of a test cell and outputting a result value to a monitor;

A function selection unit for selecting a normal operation state and a test function according to a user's function selection;

A test cell generator for generating a test cell for checking a state of a line interface module when a test function is selected in the function selector;

A cell output control unit for blocking a normal cell output of the cell monitoring unit and transferring a test cell generated by the test cell generator to the physical layer converting unit when a test function is selected by the function selecting unit;

Under the control of the cell output control unit, the cell output from the cell monitoring unit is delivered to the user side, and the test cell generated from the cell output control unit is made up of a physical layer conversion unit for feeding back to the cell monitoring unit. It is done.

The test cell generation unit may include: a utopia processing unit generating an enable signal for generating a test cell when a function selection unit receives a signal that a test function is selected;

A test cell generator for generating a test cell for a test when an enable signal for generating a test cell is driven in the utopia processor;

When the enable signal for generating a test cell is driven in the utopia processor, the input clock is counted to recognize the number of data generated by the test cell generator. A counter for generating a signal for notifying the beginning of the cell data and the header data simultaneously with the notification;

And a multiplexer which multiplexes a signal indicating the header data generated by the counter and a test cell generated by the cell generator and transmits the test cell to the output control unit as a test cell.

1 is a schematic configuration diagram of a general ATM switch;

2 is a block diagram of a conventional ATM cell test apparatus;

3 is a detailed configuration diagram of one line interface module of FIG. 2;

4 is a schematic configuration diagram of an ATM random cell generation and test apparatus according to the present invention;

5 is a block diagram of the AT random number generation and test apparatus according to the present invention;

6 is a detailed configuration diagram of the test cell generator of FIG. 5;

<Explanation of symbols for the main parts of the drawings>

71: Utopia interface unit 72: Cell monitoring unit

73: physical layer conversion unit 74: function selection unit

75: test cell generating unit 76: cell output control unit

75a: Utopia processing unit 75b: counter

75c: test cell generator 75d: multiplexer

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

4 is a schematic configuration diagram of an ATM random cell generation and test apparatus of an ATM switch system according to the present invention.

As shown therein, a first line interface module 11 connected to a user and interfacing an ATM cell through a utopia interface, and a mutual connection between the first line interface module 11 and the first 'line interface module 70. The ATM cell switching unit 20 for switching data, the controller 30 for controlling the ATM cell switching of the ATM cell switching unit 20, and the ATM cell transmitted from the ATM cell switching unit 20 are Utopian interfaces. It is delivered to the user side through, and the test cell generated by itself is composed of the first 'line interface module 70 to feed back through the feedback cable 80, process and deliver the result to the monitor 50 .

In the ATM random cell generation and test apparatus of the ATM switch system according to the present invention configured as described above, when the user's ATM cell is input through the first line interface module 11, the ATM cell switching unit 20 is the controller 30. Switch to the other subscriber's side according to the control. This switched cell is delivered to the subscriber side through the first 'line interface module 70.

In addition, the ATM cell transmitted from the subscriber side is transferred to the ATM cell switching unit 20 through the first 'line interface module 70, and the ATM cell switching unit 20 is controlled by the controller 30. Switch the cell.

The switched ATM cells are interfaced to the user through the first line interface module 11.

On the other hand, the first 'line interface module 80 generates a test ATM cell itself during the board test, and after outputting it, is fed back to the board through the feedback cable 80.

The fed back test ATM cell is processed in the first'line interface module 70 and the result is monitored by the monitor 50 to check the functional state of the developed board (herein referred to as the first'line interface module). Do it.

Hereinafter, a process of generating an actual ATM cell and a test apparatus of the generated ATM cell will be described in more detail.

5 is a block diagram of an ATM random cell generation and test apparatus according to the present invention.

As shown therein, a utopian interface unit 71 for interfacing an ATM cell switching unit and an ATM cell through a utopia interface; The cell monitoring unit monitors the state of the cell interfaced with the utopia interface unit 71 and the physical layer conversion unit 73 connected to the user, and checks the state of the test cell and outputs the result to the monitor 50. 72); A function selection unit 74 for selecting a normal operation state and a test function according to a user's function selection; A test cell generator 75 for generating a test cell for checking a state of a line interface module when a test function is selected by the function selector 74; When the test function is selected by the function selector 74, the cell output of the cell monitoring unit 72 is blocked and the test cell generated by the test cell generator 75 is transferred to the physical layer converter 73. A cell output controller 76 for transmitting; The cell output from the cell monitoring unit 72 is transferred to the user side under the control of the cell output control unit 76, and the test cell generated from the cell output control unit 76 is fed back to the cell monitoring unit ( 72 is composed of a physical layer transform unit 73 to be delivered to.

The test cell generator 75 may include: a utopia processor 75a for generating an enable signal for test cell generation when the function selector 74 receives a signal indicating that a test function is selected; A test cell generator 75c for generating a test cell for a test when an enable signal for generating a test cell is driven in the utopia processor 75a; When the enable signal for generating a test cell is driven by the utopia processing unit 75a, the input clock is counted to recognize the number of data generated by the test cell generator 75c, and as a result, the number of data forming the ATM cell is increased. A counter 75b for notifying the utopian processing unit 75a and generating a signal for notifying the beginning of the cell data and the header data; A multiplexer 75d multiplexes a signal indicating the header data generated by the counter 75b and a test cell generated by the test cell generator 75c and transmits the test cell to the output control unit 76 as a test cell.

When the ATM cell generation and test apparatus according to the present invention configured as described above normally interfaces ATM cells, the ATM cells switched by the ATM cell switching unit are interfaced by the utopia interface unit 71 and then the cell monitoring unit 72. The cell monitoring unit 72 checks the state of the cell and transmits the monitoring result to the monitor 50, and the input ATM cell is transferred to the physical layer conversion unit 73.

The physical layer converter 73 transfers the same to the connected subscriber.

In addition, the ATM cell transmitted from the subscriber is processed by the physical layer conversion unit 73 and then transmitted to the cell monitoring unit 72, the cell monitoring unit 72 monitors the cell state and the result value is monitored (50). And transmits the approved cell to the Utopia interface unit 71 to be transferred to the ATM cell switching unit.

On the other hand, if the developed board (referred to as the first 'line interface module described in the present invention) is mounted, and the examiner selects a test function to check the state of the board, the function selection unit 74 recognizes this and The test cell generator 75 and the cell output controller 76 inform the user that the test function has been selected.

Accordingly, the test cell generator 75 generates an ATM random cell for a test.

That is, when the function selection signal CNT transmitted from the function selection unit 74 is a high signal, the utopia processing unit 75a in the test cell generator 75 transmits the signal TxFul transmitted from the utopia interface unit 71. If the signal is a high signal, it is determined that the cell reception condition of the ATM cell switching unit is possible, and thus it is determined that it is a test cell generation condition, and a drive signal ce of the test cell generator 75c and the counter 75b is generated.

Here, CLK is a clock indicating a data transmission rate among the signals transmitted to the utopia processing unit 75a, and CLR is a signal indicating clear, and is used when resetting the entire board or reactivating the utopia processing unit. The utopia processor 75a generates a drive signal ce of the test cell generator 75c and the counter 75b, and at the same time, signals d_en indicating that the data currently output to the cell output controller 76 is valid data. Will be delivered.

On the other hand, when the enable signal is transmitted as a high signal from the utopia processing unit 75a as described above, the test cell generator 75c generates arbitrary data according to the input clock CLK and delivers it to the multiplexer 75d.

When the enable signal ce is generated as a high signal from the utopia processor 75a as described above, the counter 75b counts the number of generations of the test cell data by counting the input clock CLK. During this counting, if the counting value is 53 (actually, the ATM cell is composed of 53 bytes including 5 bytes of headers and 48 bytes of user information), the Utopia processor 75a is informed (CM52). In addition, the counter 75b generates a signal SOC indicating that the test cell is the first of the cell data at the same time as the test cell is generated and transmits the signal to the cell output controller 76, which corresponds to 5 bytes of the test cell data during counting. When counting is performed, a signal CM4 indicating that the header is 5 bytes is generated and transmitted to the multiplexer 75d.

When the Utopia processing unit 75a obtains the signal CM52 from the counter 75b, the utopia processing unit 75a recognizes that one ATM cell is output (generated) and performs a new cell generation.

The multiplexer 75d multiplexes the data indicating that the test cell generated by the test cell generator 75c and the header data obtained by the counter 75b is multiplexed and delivers the test cell to the cell output controller 76 as a test cell.

Here, the counter 75b transmits data indicating the header data to the multiplexer 75d to inform the multiplexer 75d as a CM4 signal, in order to make all of the HEC values in the data zero in order to facilitate calculation of the CRC8. It is used.

In other words, all of the cell data at the position where the CM4 signal is generated as a "low signal" is in a "0" state.

In addition, when the test function is selected from the function selection unit 74 as described above, the cell output control unit 76 suppresses the data output from the cell monitoring unit 72 from being transmitted to the physical layer conversion unit 73. At the same time, the test cell generated from the test cell generator 75 is transferred to the physical layer converter 73.

Then, the physical layer converter 73 outputs the same, feeds it back through the feedback cable 80, processes it, and delivers it to the cell monitoring unit 72.

The cell monitoring unit 72 compares the ATM cell data generated by the board itself fed back with the test cell generated by the test cell generator 75 to check whether the cell is an error, that is, whether the development board is abnormal. The result is transmitted to the monitor 50 so that the state of the development board is monitored.

Then, the examiner can easily recognize whether the newly developed board is normal by checking the state of the development board monitored on the monitor 50.

As described above, the present invention enables the generation and inspection of a test ATM cell on its own board (line interface module) itself, so that the board can be easily tested without using a separate expensive test equipment. It is effective.

In addition, since the development board itself can generate and test ATM cells, there is an advantage in that the board status can be checked without being bound to the predetermined ATM cell speed.

In addition, the development board can generate cells and receive feedback again, thus eliminating the disadvantage that the test cannot be performed at different interfaces between the test equipment and the development board.

Claims (2)

In the line interface module test apparatus of the ATM switch, A utopia interface unit for interfacing the ATM cell switching unit and the ATM cell through the utopia interface; A cell monitoring unit for monitoring a state of a cell interfaced with the utopian interface unit and a physical layer conversion unit connected to a user, and checking a state of a test cell and outputting a result value to a monitor; A function selection unit for selecting a normal operation state and a test function according to a user's function selection; A test cell generator for generating a test cell for checking a state of a line interface module when a test function is selected in the function selector; A cell output control unit for blocking a normal cell output of the cell monitoring unit and transferring a test cell generated by the test cell generator to the physical layer converting unit when a test function is selected by the function selecting unit; Under the control of the cell output control unit, the cell output from the cell monitoring unit is delivered to the user side, and the test cell generated from the cell output control unit comprises a physical layer conversion unit for feeding back to the cell monitoring unit ATM random cell generation and testing apparatus, characterized in that. The method of claim 1, wherein the test cell generation unit, A utopian processor configured to generate an enable signal for generating a test cell when the function selector receives a signal indicating that a test function is selected; A test cell generator for generating a test cell for a test when an enable signal for generating a test cell is driven in the utopia processor; When the enable signal for generating a test cell is driven in the utopia processor, the input clock is counted to recognize the number of data generated by the test cell generator. A counter for generating a signal for notifying the beginning of the cell data and the header data simultaneously with the notification; And a multiplexer for multiplexing a signal indicative of the header data generated from the counter and a test cell generated from the cell generator and transmitting the test cell to the output control unit as a test cell.