KR100264786B1 - ATM Random Cell Generator - Google Patents

Abstract

PURPOSE: A device for generating an ATM(Asynchronous Transfer Mode) random cell is provided to enable a test ATM random cell appropriate for a requirement of a user to be generated in a line interface module itself. CONSTITUTION: A CPU interface unit(75a) interfaces designated data for generating ATM(Asynchronous Transfer Mode) cell data designated by a user, if a signal indicating the selection of a test function is delivered from external. A utopia processor(75b) generates an enable signal for generating a test cell, if a signal indicating the selection of a test function is delivered from the external. A header generator(75c) generates header data appropriate for the designated data obtained from the CPU interface unit(75a), if the enable signal is driven. A random data generator(75d) generates user information of a cell except for a header, if the enable signal is driven. A counter(75e) counts an inputted clock if the enable signal is driven, to recognize the number of data generated in the random data generator(75d). If the number of data reaches a data number forming an ATM cell, the counter(75e) informs the utopia processor(75b) of the data number, and generates a signal indicating a start of cell data and header data. And a multiplexer(75f) multiplexes the header data generated in the header generator(75c) and user information data generated in the random data generator(75d), to output the data as a test cell.

Description

ATM Random Cell Generator

The present invention relates to the generation of Asynchronous Cells (ATM) cells, and in particular, an ATM random cell capable of generating a test ATM cell that meets user requirements in a line interface module itself. It relates to a generating device.

In general, when a development board using ATM technology is made, separate test equipment is used to test the function.

That is, the test equipment generates an ATM cell and delivers it to the development board. The development board processes the input ATM cell and then delivers the processed ATM cell to the test equipment. The test equipment compares the ATM cell received feedback with the ATM cell previously sent to the development board to check whether the development board is normal by its identity, and monitors the result so that the inspector can check whether the development board is abnormal. Be aware.

Hereinafter will be described the operation of the conventional ATM cell tester for the ATM cell test as described above.

1 is a schematic configuration diagram of a general ATM switch.

As shown therein, first and second line interface module units 10 and 40 for interfacing ATM cells with external users (PCs, W / S (workstations)), and the first and second lines. An ATM cell switching unit 20 for switching mutual data in the interface module unit 10 and 40, and a controller 30 for controlling cell switching of the ATM cell switching unit 20 and controlling overall system operation. It consisted of

In the general ATM exchanger configured as described above, the user's PC or W / S is connected to the first line interface module 11 in the first line interface module unit 10, and the user sends an ATM cell. The switching unit 20 checks the reception position of the transmitted ATM cell under the control of the controller 30 and switches the ATM cell to the second line interface module unit 40 corresponding to the receiver so that the corresponding receiver can receive it. To deliver. The first line interface module 41 in the second line interface module unit 40 (assuming a line interface module corresponding to the receiver) transmits the transferred ATM cell to a PC or workstation of a connected user (receiver). Interface to.

Similarly, the ATM cell transmitted by the user (receiver) is reversed from the above process, that is, through the first line interface module 41, the ATM cell switching unit 20, and the first line interface module 11. It is delivered to the other user (PC or W / S).

In a general ATM switch that performs this operation, a new line interface module should be tested when it is developed. FIG. 2 is a block diagram of a conventional ATM cell test apparatus for testing a newly developed line interface module. .

As shown here, mutual ATM cells of the first and first 'line interface modules 11 and 41 and the first and first' line interface modules 11 and 41 for interfacing the ATM cells are shown. An ATM cell switching unit 20 for switching, a controller 30 for controlling the ATM cell of the ATM cell switching unit 20, and controlling the overall operation of the system, and connected to the first 'line interface module 41. And the test equipment 60 for checking the state of the first 'line interface module 41.

The operation of the line interface module test apparatus of the conventional ATM switch configured as described above is as follows.

First, the test equipment 60 generates an ATM cell generated by itself to test the state of the first 'line interface module 41 (assuming a newly developed line interface module), and then through the optical cable 61 The ATM cell is delivered to the first line interface module 41.

The first 'line interface module 41 converts the transmitted optical ATM cell into an electrical signal and then transmits the converted optical ATM cell to the ATM cell switching unit 20 through an internal signal line, and the ATM cell switching unit 20 is a controller. Switching the input ATM cell by the control of (30).

The ATM cell thus switched is delivered to the first 'line interface module 41 again, and the first' line interface module 41 converts it into an optical signal, and then again the test apparatus 60 through the optical cable 62. Pass it on.

The test equipment 60 compares the data transmitted first with the received data and monitors the result on its own monitor (not shown) to allow the inspector to check the state of the newly developed board.

3 is a diagram illustrating an internal configuration of the first line interface module 41 of FIG. 2.

Here, reference numeral 41a is a utopia interface unit which is connected to the ATM cell switching unit 20 and mutually interfaces ATM cells through a utopia interface, and 41b is a mutual transmission in the utopia interface unit 41a and the physical layer conversion unit 41c. Is a cell monitoring unit that monitors the state of a received ATM cell and delivers the result to the monitor 50. 41c is a physical layer conversion unit that is connected to a user (PC or W / S) and is in charge of the interface of an ATM cell. .

The line interface module having such a configuration converts the test optical ATM cell transmitted from the test equipment 60 into an electrical signal in the physical layer converter 41c and transmits the electrical signal to the cell monitor 41b. 41b transmits the test cell to the utopia interface unit 41a after checking the cell state. The utopia interface unit 41a transfers the test cell to the ATM cell switching unit 20 through the utopia interface, and the utopia interface unit 41a retransmits the test ATM cell switched by the ATM cell switching unit 20 again. It delivers to the monitoring part 41b. The cell monitoring unit 41b checks the state of the test cell and transfers the test cell to the physical layer converting unit 41c. The physical layer converting unit 41c converts the data into optical data and then, via the optical cable. To the test equipment.

However, such a conventional ATM cell test apparatus does not have a function of generating an ATM cell in its own line interface module. Therefore, when a board is newly developed, a board developed by using an expensive test equipment is separately used for board testing. Since it is necessary to test, the board test is not only complicated, but also has a problem of being expensive due to the use of expensive test equipment.

In addition, when the signal transmission and reception method between the test equipment and the line interface module is not an optical signal method, a separate device is required for the data interface between the test equipment and the line interface module.

Accordingly, the present invention has been proposed to solve various problems occurring in the test apparatus of the conventional ATM switch as described above.

It is an object of the present invention to provide an ATM random cell generating apparatus capable of generating a test ATM random cell that meets a user's requirement in a line interface module itself.

Apparatus according to the present invention for achieving the above object,

A central processing unit interface unit for interfacing designated data for generating ATM cell data designated by a user when a signal indicating that a test function has been selected is received from the outside;

A utopian processor configured to generate an enable signal for generating a test cell when a signal indicating that a test function is selected is received from the outside;

A header generator for generating header data corresponding to user-specified data obtained from the CPU interface unit when an enable signal for generating a test cell is driven in the utopia processor;

A random data generator for generating user information of a cell excluding a header when an enable signal for generating a test cell is driven in the utopia processor;

When the enable signal for the test cell generation is driven in the utopia processor, the input clock is counted to recognize the number of data generated by the random data generator. As a result, when the number of data forming the ATM cell is reached, the utopia processor A counter for notifying this and generating a signal for notifying the beginning of the cell data and the header data;

And a multiplexer configured to multiplex the header data generated by the header generator and the user information data generated by the random data generator to output the test data to a test cell.

1 is a schematic configuration diagram of a general ATM switch;

2 is a block diagram of a conventional ATM cell test apparatus;

3 is a detailed configuration diagram of one line interface module of FIG. 2;

4 is a schematic structural diagram for explaining the concept of an ATM random cell generator in the present invention;

5 is a block diagram of the AT random number generation and test apparatus to which the present invention is applied;

6 is a block diagram of an ATM random cell generator according to the present invention.

<Explanation of symbols for the main parts of the drawings>

75: test cell generating unit 75a: central processing unit interface unit

75b: Utopia processing unit 75c: Header generation unit

75d: random data generator 75e: counter

75f: multiplexer

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

4 is a schematic block diagram illustrating the concept of an ATM random cell generation and testing apparatus of an ATM switch in the present invention.

As shown therein, a first line interface module 11 connected to a user and interfacing an ATM cell through a utopia interface, and a mutual connection between the first line interface module 11 and the first 'line interface module 70. The ATM cell switching unit 20 for switching data, the controller 30 for controlling the ATM cell switching of the ATM cell switching unit 20, and the ATM cell transmitted from the ATM cell switching unit 20 are Utopian interfaces. It is delivered to the user side through, and the test cell generated by itself is composed of the first 'line interface module 70 to feed back through the feedback cable 80, process and deliver the result to the monitor 50 .

In the ATM random cell generation and test apparatus of the ATM switch system according to the present invention configured as described above, when the user's ATM cell is input through the first line interface module 11, the ATM cell switching unit 20 is the controller 30. Switch to the other subscriber's side according to the control. This switched cell is delivered to the subscriber side through the first 'line interface module 70.

In addition, the ATM cell transmitted from the subscriber side is transferred to the ATM cell switching unit 20 through the first 'line interface module 70, and the ATM cell switching unit 20 is controlled by the controller 30. Switch the cell.

The switched ATM cells are interfaced to the user through the first line interface module 11.

On the other hand, the first 'line interface module 80 generates a test ATM cell itself during the board test, and after outputting it, is fed back to the board through the feedback cable 80.

The fed back test ATM cell is processed in the first'line interface module 70 and the result is monitored by the monitor 50 to check the functional state of the developed board (herein referred to as the first'line interface module). Do it.

5 is a block diagram of an ATM random cell generation and test apparatus to which the present invention is applied.

As shown therein, a utopian interface unit 71 for interfacing an ATM cell switching unit and an ATM cell through a utopia interface; The cell monitoring unit monitors the state of the cell interfaced with the utopia interface unit 71 and the physical layer conversion unit 73 connected to the user, and checks the state of the test cell and outputs the result to the monitor 50. 72); A function selection unit 74 for selecting a normal operation state and a test function according to a user's function selection; A test cell generator 75 for generating a test cell for checking a state of a line interface module when a test function is selected by the function selector 74; When the test function is selected by the function selector 74, the cell output of the cell monitoring unit 72 is blocked and the test cell generated by the test cell generator 75 is transferred to the physical layer converter 73. A cell output controller 76 for transmitting; The cell output from the cell monitoring unit 72 is transferred to the user side under the control of the cell output control unit 76, and the test cell generated from the cell output control unit 76 is fed back to the cell monitoring unit ( 72 is composed of a physical layer transform unit 73 to be delivered to.

In the ATM random cell generation and test apparatus to which the present invention configured as described above is normally interfaced with an ATM cell, the ATM cell switched by the ATM cell switching unit is interfaced by the utopia interface unit 71 and then the cell monitoring unit 72. The cell monitoring unit 72 checks the state of the cell and transmits the monitoring result to the monitor 50, and the input ATM cell is transferred to the physical layer conversion unit 73.

The physical layer converter 73 transfers the same to the connected subscriber.

In addition, the ATM cell transmitted from the subscriber is processed by the physical layer conversion unit 73 and then transmitted to the cell monitoring unit 72, the cell monitoring unit 72 monitors the cell state and the result value is monitored (50). And transmits the approved cell to the Utopia interface unit 71 to be transferred to the ATM cell switching unit.

On the other hand, if the developed board (referred to as the first 'line interface module described in the present invention) is mounted, and the examiner selects a test function to check the state of the board, the function selection unit 74 recognizes this and The test cell generator 75 and the cell output controller 76 inform the user that the test function has been selected.

Accordingly, the test cell generator 75 generates an ATM random cell for a test.

In addition, when the test function is selected from the function selection unit 74 as described above, the cell output control unit 76 suppresses the data output from the cell monitoring unit 72 from being transmitted to the physical layer conversion unit 73. At the same time, the test cell generated from the test cell generator 75 is transferred to the physical layer converter 73.

Then, the physical layer converter 73 outputs the same, feeds it back through the feedback cable 80, processes it, and delivers it to the cell monitoring unit 72.

The cell monitoring unit 72 compares the ATM cell data generated by the board itself fed back with the test cell generated by the test cell generator 75 to check whether the cell is an error, that is, whether the development board is abnormal. The result is transmitted to the monitor 50 so that the state of the development board is monitored.

Then, the examiner can easily recognize whether the newly developed board is normal by checking the state of the development board monitored on the monitor 50.

Hereinafter, the ATM random cell generator (hereinafter referred to as the test cell generator of FIG. 5) which is the core of the present invention will be described in more detail.

6 is a block diagram of an ATM random cell generator according to the present invention.

As shown in the figure, the central processing unit interface unit 75a for interfacing the designated data for generating ATM cell data designated by the user when receiving a signal that the test function is selected from the outside; A utopian processor 75b which generates an enable signal ce for generating a test cell when a signal indicating that a test function is selected is received from the outside; A header generator 75c for generating header data corresponding to user-specified data obtained from the central processing unit interface unit 75a when the enable signal for generating a test cell is driven by the utopian processor 75b; A random data generator 75d for generating user information of a cell excluding a header when an enable signal for generating a test cell is driven in the utopia processor 75c; When the enable signal for generating a test cell is driven by the utopia processor 75b, the clock CLK is counted to recognize the number of data generated by the random data generator 75d, thereby forming an ATM cell. A counter 75e for notifying the utopian processor 75b of the number of data and generating a signal for notifying the beginning of the cell data and the header data; And a multiplexer 75f that multiplexes the header data generated by the header generator 75c and the user information data generated by the random data generator 75d and outputs them to a test cell.

In the ATM random cell generating apparatus according to the present invention configured as described above, when a user first selects a test function and inputs designated data to generate a desired ATM cell, the central processing unit interface unit 75a interfaces this to generate a header. Provided to section 75c.

At the same time, when the function selection signal CNT transmitted from the outside is a high signal, the utopia processing unit 75b searches for a signal TxFul transmitted from the utopia interface unit 71 of FIG. Since the cell reception of the ATM cell switching unit is possible, it is determined that the cell generation condition is a test cell, and the driving signal ce is transmitted to the header generation unit 75c, the random data generation unit 75d, and the counter 75e.

Here, CLK is a clock indicating a data transmission rate among the signals transmitted to the utopia processing unit 75b, and CLR is a signal indicating clearing and is used when resetting the entire board or reactivating the utopia processing unit. The utopia processor 75b generates a drive signal ce of the header generator 75c, the random data generator 75d, and the counter 75e, and outputs the current to the cell output controller 76 of FIG. The signal d_en indicating that the data being used is valid data is delivered.

Meanwhile, the header generating unit 75c receives the user-specified data through the central processing unit interface unit 75a and stores the data in an internal register or RAM, and generates 5 bytes of header data (ATM cell generates 5 bytes. Header data and 48 bytes of user information data).

When the enable signal ce is transmitted as the high signal from the utopia processing unit 75b as described above, the random data generator 75d generates arbitrary user data in accordance with the input clock CLK to the multiplexer 75f. Deliver it.

In addition, when the enable signal ce is generated as the high signal from the utopia processor 75b as described above, the counter 75e counts the number of generations of the test cell data by counting the input clock CLK. During this counting, if the counting value is 53 (the ATM cell is composed of 53 bytes including 5 bytes of headers and 48 bytes of user information), it is notified to the utopia processing unit 75b (CM52). In addition, the counter 75e generates a signal SOC indicating that the cell data is the first as soon as the test cell is generated, and transmits the signal SOC to the cell output controller 76 of FIG. 5. When counting is performed, a signal CM4 indicating that the header is 5 bytes is generated and transmitted to the random data generator 75d.

Here, the utopian processing unit 75b recognizes that one ATM cell is output (generated) when the signal CM52 is obtained from the counter 75e, and generates a new cell again.

The multiplexer 75f multiplexes 5 bytes of header data generated by the header generator 75c and 48 bytes of user information data generated by the random data generator 75d to output 53 bytes of test cells. The cell output control unit 76 of FIG.

Here, the counter 75e transmits data indicating that the header data is a CM4 signal to the random data generation unit 75d, which is zero in all of the HEC values in the data in order to facilitate calculation of the CRC8. It is used to make

In other words, all of the cell data at the position where the CM4 signal is generated as a "low signal" is in a "0" state.

As described above, in the present invention, since the developed board (line interface module) can generate a test ATM cell required by the user itself, the ATM randomly can be easily used without using a separate expensive test equipment. The effect is that cells can be generated and tested.

In addition, since the development board itself can generate and test ATM cells, there is an advantage in that the board status can be checked without being bound to the predetermined ATM cell speed.

In addition, the development board can generate cells and receive feedback again, thereby eliminating the disadvantage that the test is impossible at the interface between the test equipment and the development board.

Claims (3)

In the line interface module test apparatus of the ATM switch, A central processing unit interface unit for interfacing designated data for generating ATM cell data specified by a user when receiving a signal indicating that a test function has been selected from the outside; A utopian processor configured to generate an enable signal for generating a test cell when a signal indicating that a test function is selected is received from the outside; A header generator for generating header data corresponding to user-specified data obtained from the CPU interface unit when an enable signal for generating a test cell is driven in the utopia processor; A random data generator for generating user information of a cell excluding a header when an enable signal for generating a test cell is driven in the utopia processor; When the enable signal for the test cell generation is driven in the utopia processor, the input clock is counted to recognize the number of data generated by the random data generator. As a result, when the number of data forming the ATM cell is reached, the utopia processor A counter for notifying this and generating a signal for notifying the beginning of the cell data and the header data; And a multiplexer for multiplexing the header data generated by the header generator and the user information data generated by the random data generator and outputting the multiplexer to a test cell. The method of claim 1, wherein the header generation unit, Atm random cell generator, characterized in that for generating the header data of 5 bytes according to the user specified data. The method of claim 1, wherein the random data generation unit, The AT cell random cell generator of claim 48, wherein the counter generates 48 bytes of random data excluding the header data as user information according to a signal indicating the header data.