KR100248408B1 - Channel loopback device for testing pba - Google Patents

Abstract

The present invention relates to an apparatus for providing a channel loopback path for a printed circuit board assembly (PBA) test of an ATM subscriber matching device. The present invention relates to a loopback of a subscriber matching device using a loopback channel in an online state without a separate test device for testing a subscriber matching device. Its purpose is to provide a test path, by placing a loopback first-in, first-out (FIFO) at the front end of the physical layer, selecting a random channel and looping back the channel at the front end of the physical layer, so that the path state of the PBA can be checked online. The advantage is that a single loopback FIFO allows all switch paths to be tested, making path testing of ATM switch systems easy.

Description

Asynchronous Transfer Mode Subscriber Interface Channel Loopback Unit for Testing PCB Assembly

The present invention relates to an apparatus for providing a path of a channel loopback for a printed board assembly (PBA) test in an asynchronous transfer mode (hereinafter referred to as ATM) subscriber registration device.

Conventionally, loopback test method for PBA test of subscriber matching device is performed by link loopback method through physical layer.

In other words, since a loopback path is provided by directly connecting between a transmitting side and a receiving side using a physical medium such as a coaxial cable, a twisted pair cable, or an optical cable, only a specific cell cannot be looped back online.

In order to solve the above disadvantages, an object of the present invention is to provide a loopback test path of a subscriber matching device using a loopback channel in an online state without a separate test device for testing an ATM matching device.

The subscriber matching device of the ATM exchanger extracts ATM cells carried through various frames, adds routing information for switching and cell header conversion, and transfers them to a switch so that the user cell is delivered to a desired destination.

In addition, by monitoring the transmission path status of the physical layer and ATM layer and detecting the failure of the path, maintenance is performed for each layer to prevent the degradation of service quality due to the failure.

The path test method of ATM subscriber registration device is classified into two types, on-line and off-line, depending on the operation type of the exchange.

The online test is performed in the operation state where the exchange system provides the actual service. The online test does not affect the service provided to the user. The offline test is performed when the service is interrupted due to a failure in the exchange installation. Test it by connecting.

Not only is it necessary to test all paths off-line to measure faulty paths for the path test of ATM subscriber-facing devices, but also during the operation or when a fault occurs, the operator requests or is periodically online on the exchange's maintenance processor. In the state, it is necessary to monitor the inside of the subscriber matching device and maintain the result, so that it is possible to monitor the status of all the paths of the exchange and to provide the function that the operator can easily maintain by detecting the location of the failure. Do.

1 is an overall configuration diagram of an ATM switching system according to the present invention;

2 is a block diagram of a loopback path device to which the present invention is applied;

3 is a structure diagram of a transmit cell memory according to the present invention;

4 is a structure of routing tag information according to the present invention;

<Explanation of symbols for main parts of drawings>

100: ATM switching system 110: ATM subscriber matching device

111: physical layer processing unit 112: AT processing unit and control unit

113: receiving cell information memory section 114: receiving ATM processing section

115: loopback FIFO unit 116: transmitting ATM processing unit

117: transmitting cell information memory section 117a: loopback connection separator

117b: Transmit loopback cell copy unit 117c: N +1 channel number

118: loopback cell copy FIFO unit 119: control unit

120: switch fabric 200: path test apparatus

301: idle cell 302: multicast cell

303: cell delay priority 304: receive loopback cell copy unit

305: cell type portion 306: routing information

In order to achieve the above object, the present invention is characterized by having a loopback first-in first-out (FIFO) unit at the front end of the physical layer and setting an arbitrary channel to route the channel to the loopback first-in first-out unit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of an ATM switching system according to the present invention. The ATM switching system 100 includes a subscriber matching device 110, a switch fabric 120, and a path test device 200. The device 110 is composed of an ATM processing unit and a control unit 112, and a physical layer processing unit 111 for terminating an ATM cell.

The present invention relates to a channel loopback device for subscriber PBA testing in the ATM subscriber matching device 110. The function implementation is located in the ATM processor and the control unit 112, and the loopback FIFO 115 for loopback at the physical layer front end. It is a device that puts.

Device and path for testing the path state of the switch fabric 120, the path state of the subscriber matching device 112, and the internal link connection state of the switch fabric 120 and the subscriber matching device 112 in the ATM switching system. Is needed.

Therefore, a detailed description will be made of an apparatus and method for testing the state and fault location detection function of the ATM switching system 100 in an on-line state by providing a loopback cell path in the ATM subscriber matching apparatus 110.

2 is a configuration diagram of a loopback path device to which the present invention is applied, and includes a physical layer processor 111, a receiving ATM processor 114, a transmitting ATM processor 116, a controller 119, and a loopback first-in first-out (First Input First) unit. Out, hereinafter referred to as FIFO) 115, a receiving cell information memory section 113, and a transmitting cell information memory 117.

In order to provide a loopback path, a loopback FIFO unit 115, a transmitting cell information memory unit 117, and a receiving cell information memory unit 113 are provided in the subscriber matching device 110, and the control unit of the subscriber matching device 110 is provided. In 119, information necessary for loopback is recorded in the receiving cell information memory section 113 and the transmitting cell information memory section 117.

For the connection to a specific loopback virtual path identifier / virtual channel identifier (hereinafter referred to as VPI / VCI) specified in the system, the transmitting cell information memory unit 117 includes a loopback connection separator 117a. The connection channel number 117c to be added to the loopback is recorded, and the reception cell information memory unit 113 records 3 bytes of routing tag information that can reach the path test apparatus 200 for a connection to a specific loopback VPI / VCI. do.

The loopback channel number 117c recorded in the receiving cell information memory unit 113 is set to 1 plus the maximum number of links provided by the PBA 110.

In the path test apparatus 200, the loop back cell is generated by determining the path of the switch fabric 120 to be tested and the subscriber matching device 110.

When the generated loopback cell is transmitted to a specific port of the switch fabric 120, the loopback cell is transmitted to the subscriber matching device 110 determined by routing in the switch fabric 120 according to the routing tag information of the loopback cell.

When the cell is transmitted from the switch fabric 120 to the subscriber registration device 110, the cell is transmitted through the transmission link interface.

The transmitting ATM processor 116 of the subscriber matching device 110 receives a switch output cell transmitted through the transmission link interface.

The loopback connection separator and the connection channel number are read by reading the information in the transmitting cell information memory section 117 with the VPI / VCI in the header of the input switch output cell.

If the read loopback connection separator is a logic level '1', the loopback cell is determined as a loopback cell, and the loopback cell is not transmitted to the physical layer, and the loopback cell of 53 bytes is written to the loopback FIFO unit 115.

In addition, after recording the loopback cell, the loopback write signal is notified to the receiving ATM processor 114.

The receiving ATM processor 114 sets the loopback cell counter and increases the loopback cell counter by one when the loopback write signal is received.

The reception ATM processor 114 decrements the loopback counter by one when one loopback cell is read.

If the read loopback cell counter is 0, it means that the loopback cell does not exist in the loopback FIFO unit 115.

When the loopback cell counter is 1 or more, the reception ATM processor 114 multiplexes the cell input to the physical layer and the cell of the loopback FIFO unit 115 to receive the reception cell. Scheduling is performed on the reception cell and the loopback cell inputted from the physical layer, and the method receives the loopback cell when there is no cell to be input in the physical layer.

The loopback cell input to the receiving ATM processing unit 114 reads additional routing information for the corresponding loopback VPI / VCI from the receiving cell information memory unit 113 by adding 3 bytes to the cell header and receives the switch input cell as a switch input cell to the switch fabric 120. It is transmitted through the link interface.

The cell input to the switch fabric 120 is transmitted back to the path test apparatus 200 generated according to the routing information.

As described above, the subscriber path can be tested in an online state by providing the loopback path with the loopback FIFO unit 115 in the subscriber matching device 110.

The control unit 119 of the subscriber matching device 110 has a loopback cell copy FIFO unit 118 between the receiving ATM processor 114 and the transmitting ATM processor 116 in order to grasp the information of the loopback cell in detail. The transmission ATM processor 116 or the reception ATM processor 114 replicates the data to the control unit 119 through the loopback cell copy FIFO unit 118.

That is, when the transmission loop back cell copy 117b signal is at the logic level '1', the transmission ATM processing unit 116 writes the cell to the loop back cell copy FIFO unit 118.

The reception ATM processing unit 114 also records the cell in the loopback cell copy FIFO unit 118 when the reception loop back cell copy signal in the routing information is logic level '1'.

Therefore, there is an advantage that the path information in the switch system can be obtained by obtaining detailed test information included in the looped cell.

As described above, the present invention can test the subscriber PBA using a specific channel without a separate test device for the path test of the subscriber matching device, and the feature of the implementation is that a loopback FIFO is performed before the physical layer. It is possible to check the path state of the PBA while online by selecting an arbitrary channel and looping the channel at the front end of the physical layer.At the same time, all the switch paths can be tested with one loopback FIFO. The path test of the switch system has an easy effect.

Claims (6)

An apparatus for providing a channel loopback path for a printed circuit board assembly (PBA) test of an asynchronous transmission mode (ATM) subscriber registration device, A receiving cell information memory section for recording routing tag information that can arrive at the path test apparatus for a connection to a specific loopback virtual path identifier / virtual channel identifier; A reception asynchronous transmission mode processor configured to receive a loopback write signal with a loopback cell counter and increment the loopback counter; A transmission asynchronous transmission mode processing unit which receives a switch output cell transmitted through a transmission link interface; A transmitting cell information memory section for recording a loopback connection identifier and a connection channel number to be added to the loopback for a connection to a specific loopback identifier specified in the system; And a control unit for recording information necessary for loopback in the receiving cell information memory unit and the transmitting cell information memory unit. The method of claim 1, wherein the receiving cell information memory unit A channel loopback device for testing an asynchronous transfer mode subscriber station printed circuit board assembly, comprising recording a loopback channel number of one plus the maximum number of links provided by one subscriber line printed circuit board assembly. The method of claim 1, wherein the receiving asynchronous transmission mode processing unit An asynchronous transmission mode subscriber registration device channel loopback device for testing a printed circuit board assembly, characterized in that the reception cell is multiplexed with the cell input to the physical layer and the loopback first-in first-out part when the loopback counter is 1 or more. The transmission asynchronous transmission mode processing unit of claim 1, wherein the transmission asynchronous transmission mode processing unit is performed. An asynchronous transmission mode subscriber registration device channel loopback device for testing a printed circuit board assembly, characterized by recording a transmit loopback cell copy signal according to a logic level to a loopback cell copy first-in, first-out. 2. The transmission cell information memory unit according to claim 1, wherein the transmission cell information memory unit An asynchronous transmission mode subscriber registration device channel loopback apparatus for testing a printed circuit board assembly, characterized in that the loopback cell is determined according to the logic level of the loopback connection separator and the loopback cell is written to the loopback first-in, first-out. The method of claim 1, wherein the control unit In order to grasp the information of the loopback cell, a loopback cell copying first-in, first-out is placed between the reception asynchronous transmission mode processing unit and the transmission asynchronous transmission mode processing unit, and the loop back cell is copied from the transmission asynchronous transmission mode processing unit or the reception asynchronous transmission mode processing unit to copy the loopback cell. An asynchronous transmission mode subscriber registration device channel loopback device for testing a printed circuit board assembly, characterized in that it is delivered through a first-in, first-out.

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