KR100262692B1 - Method for control of device in a process - Google Patents

Abstract

PURPOSE: A method for controlling an external device of a processor is provided to prevent a malfunction of the device, and make it easy to expand the device, by enabling the processor to combine many selection signals and thereby select the device, allowing the processor to use a confirming signal as a reference signal for controlling the device and thereby stabilize the operation timing of the device. CONSTITUTION: An address strobe signal, a selection signal and an operation signal are activated in response to a clock signal of the processor, and an address signal and a data signal are applied to the device via an interface part. When a cycle of the clock signal expires, the processor applies the signal for confirming an active state to the device via the interface part. When the processor receives an acknowledgement signal responsive to data transmission and its size from the device via the interface part, it changes the state of the confirming signal to a reactive state.

Description

Device control method on processor

The present invention relates to a method of controlling a device in a processor. In particular, when the processor operates at a high speed, the processor selects a device by combining a selection signal, and when the device is located at a remote location, the control signal output operation of the processor is performed. The present invention relates to a method for controlling a device in a processor that enables the timing to be stabilized using an acknowledgment signal.

In general, the basic control signal used by the processor to control devices present in the external circuitry includes a selection signal (CS /) for selecting a device to be controlled and an address signal for designating a specific register or memory of the device. And a data signal between the processor and the memory or the interface unit and the device, and when the processor reads data from a device other than the processor and writes data to a device other than the processor, that is, an operation indicating a current operation of the processor. There is a signal (RD / signal, WR / signal).

On the other hand, the conventional configuration for signal transmission between the processor and the device, as shown in Figure 1 processor 11 for controlling the overall operation for the transmission and reception of various control signals and the interface unit for matching the control signals transmitted and received And a plurality of devices 13 for transmitting and receiving control signals and data to and from the processor 11 through the interface unit 12, wherein the processor 11 and the device 13 are devices in the processor 11. An address bus for transmitting an address signal applied to (13) and a data signal for transmitting data from the processor 11 to the device 13 or for receiving data applied from the device 13 to the processor 11; The data bus to be read, and the RD / signal when the processor 11 reads data from the device 13 and the WR / signal when the data is written to the device 13. And RW / bus for transmission, and is connected to a selection signal produced by decoding the address signals from the internal processor 11 to the CS / bus transfer.

The data transmission / reception operation between the conventional processor 11 and the device 13 configured as described above is performed as follows.

First, when the processor 11 intends to transmit data to the device 13 through the interface unit 12, the processor 11 may decode the selection signal generated by decoding the address signal using the CS / bus interface unit ( 12 selects the device 13 corresponding to the selection signal. Subsequently, when a clock signal of approximately 1.5 cycles has passed since the frame synchronization signal for notifying the start of the transmission of the address signal was applied to the corresponding device 13, the n-bit address signal A0-An and WR for specifying data transmission were passed. When the / signal is applied to the interface unit 12 using the address bus and the RW / bus, respectively, the interface unit 12 matches and applies the applied signal to the device 13. Subsequently, the device 13, which is the receiving side of the data, recognizes the frame synchronization signal, the address signal, and the WR / signal applied from the processor 11, and notifies that the data reception is ready after approximately two cycles of the clock signal have passed. When the ready signal is applied to the processor 11, the processor 11 may transmit data to the device 13 through the interface unit 12 using a data bus according to the received ready signal.

Next, when the processor 11 wants to read data transmitted from the device 13, the device 13 selected by the processor 11 uses the data bus when the operation signal of the processor 11 is an RD signal. The processor 11 transmits its own data. When the clock signal of approximately 1.5 cycles has elapsed after the frame synchronization signal for notifying the start of transmission of the address signal is applied to the device 13, the processor 13 When the n-bit address signal and the RD signal to read data are applied to the interface unit 12 using the address bus and the RW / bus, respectively, the interface unit 12 matches the applied signal and the corresponding device 13 ) Is applied. Thereafter, the device 13 on the data transmission side recognizes the frame synchronization signal, the address signal, and the RD signal applied from the processor 11, and after the clock signal of approximately two cycles has elapsed, it is ready to notify that the data transmission is ready. After the completion signal is applied to the processor 11 and the data to be transmitted using the data bus is applied to the processor 11 through the interface unit 12, the processor 11 transmits data through the interface unit 12. Read data sent to the bus.

In the conventional processor as described above, when the controlled device is located at a long distance, a signal attenuation occurs while the control signal output by the processor is transmitted to the device, thereby causing the corresponding device to malfunction, and the selection signal is limited. The problem is that each time you add a device, you must change the hardware part.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a device selection by combining a plurality of selection signals in a processor when the processor operates at a high speed, and at the same time, for a device located at a remote location. By using the confirmation signal as a reference signal for controlling the external device to stabilize the operation timing of the device, to prevent malfunction of the device and at the same time provide device convenience.

A feature of the present invention for achieving the above object is, in a device control method in a processor, an address strobe signal, a selection signal, and an operation signal are activated in accordance with a clock signal of the processor, Applying a data signal to the device through an interface unit; A second step of applying, by the processor, an active confirmation signal to the device through an interface unit when a clock signal of the processor has passed one cycle; And a third process of converting the confirmation signal into a reactive state when an ACK signal for data transmission and size is applied to the processor from the device to the processor in an active state.

A plurality of selection signals are output from the processor, and a corresponding device is selected by a combination of selection signals from two signals output in an active state among the plurality of selection signals.

The confirmation signal is used as a reference signal when outputting an address signal, a data signal, a selection signal, and an operation signal for controlling the device of the processor, and stabilizes timing. The confirmation signal is generated in synchronization with the state transition of the processor. It is characterized in that it is generated in association with the ACK signal for data transmission and size.

1 is a block diagram illustrating a signal transmission between a conventional processor and a device.

2 is a block diagram illustrating a signal transmission between a processor and a device according to the present invention;

3 is a device control signal timing diagram in a processor in accordance with the present invention.

4 is a block diagram illustrating an embodiment of the processor shown in FIG.

Explanation of symbols on the main parts of the drawings

11, 21: processor 12, 22: interface unit

13, 23: device

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the configuration for signal transmission between the processor and the device according to the present invention, as shown in Figure 2, the processor 21 for controlling the overall operation of the transmission and reception of various control signals and the interface unit for matching the control signals transmitted and received And a plurality of devices 23 for transmitting and receiving control signals to and from the processor 21 through the interface unit 22. The processor 21 and the device 23 are devices 23 in the processor 21. Address bus for transmitting an address signal to be applied to the device), and data for transmitting a data signal for transmitting data from the processor 21 to the device 23 or for receiving data applied from the device 23 to the processor 21. The bus and the RD signal when the processor 21 reads data from the device 23 and the WR / signal when writing data to the device 23 are transmitted. RW / bus, a CS / bus for transmitting a selection signal generated by decoding an address signal inside the processor 21, and an STB for transmitting a confirmation signal for timing the control of the device 23 by the processor 21. / Connected by bus.

As control signals for data transmission and reception between the processor 21 and the device 23 according to the present invention configured as described above, eight selection signals CS / for selecting the device 23 and specific registers of the device 23 are provided. Or an address signal of 8 bits for designating a memory, when the processor 21 reads data from a device 23 other than the processor 21, and when data is written to a device other than the processor. The operation signals RD and WR / indicating the current operation of the processor and the confirmation signal STB / for timing the processor 21 in controlling the device 23 are used. As shown in the example, the processor 21 includes a CPU 31, a buffer 32, a selection signal generation logic 33, a confirmation signal generation logic 34, and a clock generator 35 as shown in FIG. ) Is made. The CPU 31 transmits and receives data via a data bus, transmits an address via an address bus, transmits an address strobe signal AS / and an operation signal RD, WR /, and receives an external device 23 from an external device 23. Receives an ACK signal (DSACK /) for the data transmission and size applied. The clock generator 35 generates a clock for operating the CPR 31, and the buffer 32 transmits an address signal, a data signal, an address strobe signal AS /, an operation signal RD, WR / and data transmission. It plays a role of buffering and transmitting the magnitude ACK signal (DSACK /). The selection signal generation logic 33 is composed of a field programmable gate array (FPGA), which includes a clock signal applied from the clock generator 35, addresses A0 to A3 and an address strobe signal applied from the CPU 31. According to AS /, a plurality of selection signals CS0 / to CS7 / are generated and transmitted to the device 23 side via the interface unit 22. The confirmation signal generation logic 34 is composed of an FPGA, and includes a clock signal applied from the clock generator 35, an address strobe signal AS / applied from the CPU 31, and a selection signal generation logic 33. The acknowledgment signal STB / is generated according to the selection signals CS0 / to CS7 applied and the ACK signal DSACK / corresponding to the data transmission and magnitude applied from the device 23, and then via the interface unit 22. Transfer to the device 23 side.

The control operation of the device 23 in the processor 21 as described above is as follows. First, the address strobe signal AS /, the selection signal CS /, and the operation signals RD and WR / correspond to a clock signal for operating the processor 21 generated by the clock generation unit 35. After being in an active state and applying an address signal and a data signal to the device 23 through the interface unit 22, when the clock signal of the processor 21 passes one cycle, the interface unit ( The confirmation signal STB / of the active state is applied to the device 23 through 22. Subsequently, when the ACK signal DSACK / is transmitted to the processor 21 from the device 23 through the interface unit 22 in the active state, the acknowledgment signal STB / is set to the reactive state. Convert.

The select signal CS / is outputted from the processor 21 circuit unit to eight signals CS0 / to CS7 / to the outside, and a combination of two CS / signals output at a low level among the eight signals is performed. It is used as a selection signal for selecting 23), and the two CS / signal combinations among the eight signals are all 28 so that 28 devices 23 can be selected.

In addition, the confirmation signal STB / may be used when the address signal, data signal, selection signal, and operation signal among the signals used by the processor 21 to control the device 23 of the external circuit are depleted or delayed. Since a malfunction occurs, a confirmation signal STB / generated by the confirmation signal generation logic 34 of the processor 21 is used to prevent such a malfunction. First, the confirmation signal STB / is used as a processor 21. (2) generates a signal by operating together with a clock signal for driving the second signal. Second, the hob signal STB / is a reference when the processor 21 outputs a selection signal, an address selection signal CS0 / to CS7, and an address signal. Generated using the address strobe signal AS /, which is used as a signal, and third, the acknowledgment signal STB / is an ACK signal DSACK0 for data transmission and size used when the processor 21 performs an actual operation. /, Associated with DSACK1 /) It has a feature that. That is, the acknowledgment signal STB / is synchronized with the operation of the processor 21, operates by sensing the operation of the selection signal and the address signal, and operates in relation to the actual operation of the processor 21. . Therefore, the confirmation signal STB / can be used as a reference signal for the processor 21 to control the device 23 of the external circuit section, and stabilizes the timing in addition to the basic control signal.

The timing of these control signals is shown in FIG. 3, in which a data signal is also output along with the AS / signal in accordance with the clock signal of the processor 21. At this time, the processor 21 creates the CS / signal and enables the AS / signal. The acknowledgment signal STB / is generated in accordance with the CS / signals made of the AS / signal and the address signal and the clock signal of the processor 21. This confirmation signal STB / starts as one clock cycle after the AS / signal outputs the clock signal of the processor 21. Since the processor 21 performs and terminates the operation when the ACK signal DSACK / for data transmission and size is applied, the confirmation signal STB / also terminates the operation. Since the confirmation signal STB / is applied to the device 23 in various ways in association with the processor 21, the use of the confirmation signal STB / is external to the control of the processor 21 circuit operating at high speed. It can be used effectively in a circuit.

As described above, according to the present invention, when the processor operates at a high speed, the processor may combine a plurality of selection signals to select a device, and at the same time, the processor controls the external device to confirm the confirmation signal with respect to a remote device. By using the signal to stabilize the operation timing of the device, it is possible to prevent malfunction of the device and to provide device expansion convenience.

Claims (3)

In the device control method in the processor, A first step of applying an address signal and a data signal to the device through an interface unit while an address strobe signal, a selection signal, and an operation signal become active in accordance with a clock signal of the processor; A second step of applying, by the processor, an active confirmation signal to the device through an interface unit when a clock signal of the processor has passed one cycle; And converting the acknowledgment signal into a reactive state when an ACK signal for data transmission and magnitude is applied from the device to the processor through an interface unit in an active state. The device of claim 1, wherein a plurality of the selection signals are output from the processor, and a corresponding device is selected by combining two selection signals output in an active state among the plurality of selection signals. Control method. The method of claim 1, wherein the confirmation signal is used as a reference signal when outputting an address signal, a data signal, a selection signal, and an operation signal for controlling the device of the processor to stabilize the timing. And generated in synchronization with the ACK signal for data transmission and size.

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