KR100317329B1 - DMA(Direct Memory Access) controller - Google Patents

Abstract

The present invention provides a DMA controller suitable for shortening the transmission time by enabling data to be transferred in the dual address transfer mode to the dual address transfer mode using a DMA having a structure in which an internal memory and a DMA are combined. And a DMA controller for transferring data transfer between an external memory and an external input / output device and an internal memory in a dual address mode, comprising: a plurality of channels, the channel and the DMA control, and a channel controlling an internal memory, a DMA control An internal memory controller, a first address mux for muxing the addresses output from the channels, and outputting a DMA address; a second address mux for muxing and outputting addresses output from the channels; Input address of the second address mux unit and input via the internal bus Muxing an address that is output by the third address MUX unit, comprising an internal memory for performing write and read of data in accordance with an address outputted from the third address MUX unit.

Description

DDMA controller {Direct Memory Access (DMA) controller}

The present invention relates to a microcontroller unit (MCU: hereinafter referred to as "MCU"), in particular, the MCU for the internal memory and DMA (Direct Memory Access; hereinafter referred to as "DMA") When transferring data in dual address transfer mode with a controller, transfer in dual address transfer mode using DMA with a combination of internal memory and DMA to shorten the transfer time. What is needed is a DMA controller capable of transferring in a single address transistor mode.

Hereinafter, a DMA controller according to the prior art will be described with reference to the accompanying drawings.

1 is a block diagram of a MCU having a DMA.

As shown in FIG. 1, the MCU 11 includes a CPU 11a, a DMA 11b, an internal memory unit 11c, an external bus controller 11d, an MCU controller 11e, and a plurality of internal input / outputs. Devices 11f_1, 11f_2, ...

Here, the respective blocks are commonly connected to the internal bus 12.

Meanwhile, the external bus controller 11d is connected to an external bus 13 located outside the MCU 11, and the external bus 13 has an external memory unit 14 and a plurality of external bus controllers in addition to the external bus controller 11d. External input / output devices 15_1, 15_2, ... are commonly connected.

Here, the DMA will be described in more detail.

FIG. 2 is a block diagram illustrating a DMA showing the DMA of FIG. 1 in more detail.

As shown in FIG. 2, the DMA includes a channel control and DMA control unit 21, a plurality of channels CH0, CH1, ..., CHn, and an address input from each channel. An address mux (MUX) 22 muxed by the control signal of (21), a DMA register 23, a data register 24, and the like.

Here, the data register 24 and the DMA register 23, and the channel and DMA control unit 21 is connected to the internal bus 12 of the MCU.

In addition, a start / end register 25 and a channel control register 26 are connected between the channel and the DMA control unit 21 and the DMA register 23.

Each channel consists of a source address register 31, a destination address register 32, a counter register 33, and a control register 34. Counters 35a and 35b are connected to the source and destination address registers 31 and 32 to increment the register value by one after the address is output.

The enable register 34 stores an enable bit, a single / dual mode bit, a burst / single steal mode bit, and a status bit.

A sequence controller 36 is further configured to receive outputs of the source address register 31, the destination address register 32, the counter register 33, and the control register 34 to control the sequence.

The operation of the DMA according to the prior art configured as described above will be described with reference to FIGS. 1 and 2.

First, the transmission mode of the DMA includes a burst / cycle steal mode and a single / dual address mode. Hereinafter, the dual address mode will be described in the related art.

When data is transferred using DMA in the dual address mode, first, the source address is output by the DMA 11b to read the source data. Therefore, data stored in the device (memory or input / output device) is read (source address read cycle).

After storing this data in the internal data register of the DMA for a while, the data is immediately written to the destination address (destination address write cycle).

First, in the source address read cycle, the data is loaded from the external memory 14 or the external input / output devices 15_1, 15_2, ... onto the external system bus, and the data is loaded into the internal bus 12 of the MCU. On Thereafter, the source address read cycle ends when stored in the data register 24 in the DMA again.

Thereafter, the destination address write cycle for the write operation begins. That is, the data stored in the data register 24 in the DMA is loaded on the internal data bus 12 again, and the destination address is internal input / output devices 11f_1, 11f_2, ... or internal memory 11c. ) Is written to the corresponding memory or I / O device inside the MCU, and if the destination address is an external I / O device (15_1, 15_2, ...) or external memory (14) It can be written to external memory or an external input / output device.

This process is illustrated in the data transmission timing diagram of FIG. 3.

On the other hand, in the case of the source address read cycle, the value of the source address register 31 outputs the DMA address via the address mux unit 22.

At this time, the read data is written to the data register 24, and in the next cycle of the destination address write cycle, the destination address is output to the outside through the address mux section 22. At this time, the data stored in the data register 24 is also outputted so that the data is written to the corresponding address.

However, the conventional DMA controller has the following problems.

When data needs to be transmitted or received in the dual address mode for the internal memory, the write operation is performed only after the execution cycle for data transmission is read. Therefore, the time required for accessing the internal memory is further consumed as the transmission time. Occurs.

The present invention has been made to solve the above problems of the prior art, by using the DMA structure of the combination of the internal memory and the DMA to transmit the data to be transmitted in the dual address transfer mode in a single address transfer mode It is an object of the present invention to provide a DMA controller suitable for shortening the time.

1 is a block diagram of a MCU according to the prior art

2 is a block diagram of a conventional DMA control apparatus

3 is a data transmission timing diagram according to the prior art.

4 is a block diagram of a DMA control apparatus according to the present invention;

5 is a timing diagram according to data transfer from an external memory and an external input / output device to the internal memory.

6 is a timing diagram according to data transfer from an internal memory to an external memory and an external input / output device.

Explanation of symbols for main parts of the drawings

41: channel, DMA control and internal memory controller

42,43: first and second address mux unit 44: DMA register

45: data register 46: third address mux unit

47: internal memory 51: source address register

52: destination address register 53: counter register

54: control register

The DMA control apparatus of the present invention for achieving the above object in the DMA control apparatus for transmitting data transfer between the external memory and the external input / output device and the internal memory in a dual address mode, a plurality of channels, and the channel And a channel for controlling DMA control and internal memory, a DMA control and internal memory control unit, a first address mux unit for outputting a DMA address by muxing addresses output from the respective channels, and addresses output from the respective channels. A second address mux unit for muxing and outputting a second address, a third address mux unit for muxing and outputting an output address of the second address mux unit and an address input through an internal bus, and an address output from the third address mux unit It is configured to include an internal memory for performing the writing and reading of the data.

Hereinafter, a DMA control apparatus of the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of a DMA control apparatus according to the present invention.

As shown in Fig. 4, the channel, DMA control and internal memory control section 41, a plurality of channels CH0, CH1, ..., and an address input from each channel are assigned to the channel, DMA control and the like. First and second address mux sections 42 and 43, the DMA register 44, the data register 45, and the second address mux section 43 muxed by control signals of the internal memory control section 41. The third address mux section 46 for inputting and muxing the address output from the second address and the internal memory address input through the internal memory address bus, and the internal memory 47 for addressing the output of the third address mux section 46. It is composed of

Here, the data register 45 and the DMA register 44, and the channel and DMA controller 41 are connected to the internal bus of the MCU.

Each channel is composed of a source address register 51, a destination address register 52, a counter register 53, and a control register 54, and an address is output to the source and destination address registers 51 and 52. After that, the counters 55a and 55b which increase the register value one by one are connected.

The enable register 54 stores enable bits, IM bits, single / dual mode bits, burst / single still mode bits, and status bits.

Herein, the IM bit is an internal memory transfer mode bit.

The control register 54 further stores an IM bit that has been stored in a control register according to the prior art.

On the other hand, the second address mux unit 43 uses its output as the input of the third address mux unit 46, while the first address mux unit 42 outputs the DMA address as in the prior art.

Meanwhile, the data bus 47a of the internal memory is connected to the internal bus 12 of the MCU.

In addition, a start / end register 48 and a channel control register 49 are connected between the channel, the DMA control, and the internal memory controller 41 and the DMA register 44.

A sequence controller 56 is further configured to receive the output of the source address register 51, the destination address register 52, the counter register 53, and the control register 54 to control the sequence.

The operation of the DMA control apparatus of the present invention configured as described above will be described with reference to FIGS. 4 to 6.

First, as illustrated in FIGS. 4 and 5, when data is imported from an external input / output device or an external memory into the internal memory, the data output from the external memory or the external input / output device may be an external bus. This data will be loaded on the MCU's internal bus 12.

This data is not transferred to the data register 49 of the DMA but is transferred directly to the corresponding address of the internal memory 47.

On the contrary, that is, when data is imported from the internal memory 47 to an external input / output device or an external memory, the data of the internal memory 47 is directly transferred to the internal bus 12 by the address output function of the DMA. ) And the address corresponding to the external memory or the external input / output device output at the same time is output to the outside of the MCU to complete the data write operation.

That is, in the conventional case of dual cycle access related to the internal memory, two cycles are terminated in one simultaneous cycle to increase the data transfer speed of the DMA.

On the other hand, as shown in FIG. 6, when transferring from the internal memory to the external memory in the dual address mode, as shown in FIG. 6, the value of the source address register 51 indicates a part of the internal memory. The value is transferred to the internal memory 47 through the second address mux section 43 to the third address mux section 46 which is the internal memory address mux.

At this time, the channel, the DMA control and the internal memory control unit 41 transmits a control signal to the internal memory 47 until the data of the internal memory 47 is directly loaded on the internal bus 12 of the MCU.

At the same time, the value of the destination address register 52 designates any address of the external memory, and this value is carried on the internal bus through the first address mux section 42, and this address is stored in the internal memory 47. It is output to the outside as the data of.

The externally output address and data are stored in the corresponding external memory and the DMA cycle ends.

As described above, the DMA control apparatus of the present invention has the following effects.

In the DMA transfer in dual address mode toward the internal memory, the conventional method requires a clock (at least 1 clock or more) required to access the internal memory. However, in the present invention, since the internal memory cycle is processed in parallel during internal memory-related transfer, Time savings by this clock can improve the DMA transfer rate.

Claims (4)

A DMA control apparatus for transferring data transfer between an external memory and an external input / output device and an internal memory in a dual address mode, A plurality of channels, A channel, a DMA control and an internal memory control unit for controlling the channel and the DMA control and the internal memory; A first address mux unit for muxing the addresses output from the channels and outputting a DMA address; A second address mux unit for muxing and outputting addresses output from the respective channels; A third address mux unit configured to mux and output an output address of the second address mux unit and an address input through an internal bus; And an internal memory configured to write and read data according to the address output from the third address mux unit. The DMA control apparatus according to claim 1, wherein each channel comprises a source address register, a destination address register, a counter register, and a control register. 3. The DMA controller according to claim 2, wherein the control register stores enable bits, single / dual mode bits, burst / cycle still mode bits, internal memory transfer mode bits, and status bits. The DMA control apparatus of claim 1, wherein the internal memory transfers data corresponding to an input address to an internal bus.