KR100262531B1 - Method of post treatment a polysilicon layer in a semiconductor device - Google Patents

Method of post treatment a polysilicon layer in a semiconductor device Download PDF

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KR100262531B1
KR100262531B1 KR1019970079326A KR19970079326A KR100262531B1 KR 100262531 B1 KR100262531 B1 KR 100262531B1 KR 1019970079326 A KR1019970079326 A KR 1019970079326A KR 19970079326 A KR19970079326 A KR 19970079326A KR 100262531 B1 KR100262531 B1 KR 100262531B1
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polysilicon
polysilicon layer
semiconductor device
layer
post treatment
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KR1019970079326A
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Korean (ko)
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KR19990059129A (en
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김수호
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A post treatment method of a polysilicon layer is provided to improve electrical properties and a reliability by easily removing the etching residues of the polysilicon. CONSTITUTION: A polysilicon layer(3) is formed on a semiconductor substrate(1) having a step difference, thereby forming simultaneously a concave part(2). By selectively etching the polysilicon layer(3), a polysilicon pattern(3A) is formed and etching residues(3B) are formed in the concave part(2). By performing a wet oxidation process at the temperature of 700-800°C and by the oxidation speed of 1¯100 Å/min using H2 gas of 1000¯20000 sccm and O2 gas of 1000¯20000 sccm, the etching residues(3B) and the surface of the polysilicon pattern(3A) are transferred to an oxide layer(30). The oxide layer(30) is then removed.

Description

반도체 소자의 폴리실리콘층 후처리 방법Post-processing polysilicon layer of semiconductor device

본 발명은 반도체 소자의 폴리실리콘층 후처리(post treatment) 방법에 관한 것으로, 특히 반도체 소자의 제조 공정중 폴리실리콘층을 사용하여 전극 또는 배선 등으로 사용하는데, 폴리실리콘층 패터닝 공정 후에 남게되는 폴리실리콘 잔존물을 용이하게 제거하여 소자의 전기적 특성 향상 및 신뢰성을 증대시킬 수 있는 반도체 소자의 폴리실리콘층 후처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a post-processing method of a polysilicon layer of a semiconductor device. In particular, the polysilicon layer is used as an electrode or a wiring by using a polysilicon layer during a manufacturing process of a semiconductor device. The present invention relates to a polysilicon layer post-treatment method of a semiconductor device capable of easily removing silicon residues to increase electrical properties and reliability of a device.

일반적으로, 반도체 소자의 제조 공정중 트랜지스터의 게이트, 캐패시터의 전극, 접지 라인, 플래쉬 메모리의 전극 등을 형성하기 위해 폴리실리콘층이 널리 사용되고 있는데, 폴리실리콘층 패터닝 공정 후에 하부층의 심한 굴곡 부분에 폴리실리콘 잔존물이 남게 된다. 폴리실리콘 잔존물은 소자의 전기적 특성 및 신뢰성을 저하시키는 요인으로 작용되기 때문에 이를 제거하여야 한다.In general, a polysilicon layer is widely used to form a gate of a transistor, an electrode of a capacitor, a ground line, an electrode of a flash memory, and the like in a semiconductor device manufacturing process. Silicon residues are left behind. Polysilicon residues should be removed because they act as a factor of deteriorating the electrical characteristics and reliability of the device.

종래 폴리실리콘 잔존물 제거 방법은 건식 식각 공정을 일정한 정도로 추가하거나, 50 : 1 HF 또는 100 : 1 BOE 식각제를 사용한 습식 식각 방법 또는 건식 산화공정으로 제거하였다. 그러나, 이러한 방법중 첫째로, 건식 식각 방법은 잔존물을 제거할 정도로 식각을 하게되면 하부층, 예를 들어, 액티브 영역에 식각 손상을 입히게 되어 이 영역에 형성될 소자의 전기적 특성 저하를 초래하게 된다. 또한 잔존물을 제거할 정도로 충분한 식각 처리가 진행되지 않으면, 잔존물로 인하여 패터닝된 폴리실리콘 라인 사이에 브릿지(bridge) 현상이 발생된다. 둘째로, 습식 식각 방법은 잔존물을 제거할 정도로 습식 식각을 하게 되면, 패터닝된 폴리실리콘층의 하부 가장자리부분이 식각 되어 소자의 특성을 악화시키게 된다. 마지막으로, 폴리실리콘층의 패터닝 후에 폴리실리콘층 내부의 불순물을 활성화시키기 위한 공정인 건식 산화공정으로 잔존물을 제거할 정도로 과도한 산화를 하게 되면, 기판이 받는 열이 너무 크게 되어 소자의 특성이 바뀌어 기본적인 불순물 이온 주입 조건을 다시 제어해야 하는 단점이 있다.Conventional polysilicon residue removal methods have been added by a dry etching process to a certain degree, or by a wet etching method using a 50: 1 HF or 100: 1 BOE etchant or dry oxidation process. First of all, however, the dry etching method etched enough to remove the residues causes etch damage to the underlying layer, for example, the active area, resulting in deterioration of the electrical characteristics of the device to be formed in this area. In addition, if the etching process does not proceed enough to remove the residue, a bridge phenomenon occurs between the patterned polysilicon lines due to the residue. Second, in the wet etching method, when wet etching is performed to remove residues, the lower edge portion of the patterned polysilicon layer is etched to deteriorate the device characteristics. Finally, if the oxidation is excessive enough to remove the residue by the dry oxidation process to activate impurities inside the polysilicon layer after patterning of the polysilicon layer, the heat received by the substrate becomes too large and the characteristics of the device are changed. There is a disadvantage in that the impurity ion implantation conditions must be controlled again.

따라서, 본 발명은 폴리실리콘층 패터닝 공정 후에 남게되는 폴리실리콘 잔존물을 용이하게 제거하여 소자의 전기적 특성 향상 및 신뢰성을 증대시킬 수 있는 반도체 소자의 폴리실리콘층 후처리 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a polysilicon layer post-treatment method of a semiconductor device capable of easily removing polysilicon residues remaining after a polysilicon layer patterning process, thereby improving electrical characteristics and increasing reliability of the device.

이러한 목적을 달성하기 위한 본 발명의 폴리실리콘층 후처리 방법은 반도체 소자의 도전층을 형성하기 위해 폴리실리콘 증착 및 패터닝 공정 후에 남게되는 폴리실리콘 잔존물을 습식 산화 공정으로 산화시켜 제거하는 것을 특징으로 한다.The polysilicon layer post-treatment method of the present invention for achieving this object is characterized in that the polysilicon residue remaining after the polysilicon deposition and patterning process is oxidized and removed by a wet oxidation process to form a conductive layer of the semiconductor device. .

도 1(a) 내지 도 1(d)는 본 발명의 실시예에 따른 반도체 소자의 폴리실리콘층 후처리 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of a device for explaining a polysilicon layer post-processing method of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1: 기판 2: 굴곡부1: substrate 2: bend

3: 폴리실리콘층 3A: 폴리실리콘 패턴3: polysilicon layer 3A: polysilicon pattern

3B: 잔존물 30: 산화막3B: Residue 30: Oxide Film

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(d)는 본 발명의 실시예에 따른 반도체 소자의 폴리실리콘층 후처리 방법을 설명하기 위한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of a device for explaining a polysilicon layer post-processing method of a semiconductor device according to an embodiment of the present invention.

도 1(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)상에 반도체 소자의 전도층으로 사용될 폴리실리콘층(3)이 형성된다. 제공된 기판(1)의 표면은 필드 산화공정 또는 기타 소자를 형성하기 위한 공정 등으로 인하여 단차가 지게 되며, 심한 굴곡부(2)가 생기게 된다.Referring to FIG. 1A, a polysilicon layer 3 to be used as a conductive layer of a semiconductor element is formed on a substrate 1 having a structure in which various elements for forming a semiconductor element are formed. The surface of the provided substrate 1 is stepped due to a field oxidation process or a process for forming other elements, and a severe bend 2 is produced.

도 1(b)를 참조하면, 포토리소그라피(photolithography) 공정 및 패터닝 공정으로 폴리실리콘층(3)의 선택된 부분을 식각 하여, 폴리실리콘 패턴(3A)이 형성되고, 이때 기판(1) 표면의 굴곡부(2)에 잔존물(3B)이 생기게 된다.Referring to FIG. 1B, a selected portion of the polysilicon layer 3 is etched by a photolithography process and a patterning process to form a polysilicon pattern 3A, wherein the curved portion of the surface of the substrate 1 is formed. Residue 3B is produced in (2).

도 1(c)를 참조하면, 700 내지 800℃의 온도에서, 1000sccm 내지 20000slpm의 H2가스와 1000sccm 내지 20000sccm의 O2가스를 흘려 1Å/min 내지 100Å/min의 산화속도로 습식 산화공정을 실시하여, 잔존물(3B)과 폴리실리콘 패턴(3A)의 표면이 산화되어 산화막(30)이 형성된다.Referring to FIG. 1 (c), a wet oxidation process is performed at an oxidation rate of 1 kW / min to 100 kW / min by flowing H 2 gas of 1000 sccm to 20000 slm and O 2 gas of 1000 sccm to 20000 sccm at a temperature of 700 to 800 ° C. Thus, the surface of the residue 3B and the polysilicon pattern 3A is oxidized to form an oxide film 30.

도 1(d)를 참조하면, 산화막(30)을 산화 제거 공정으로 제거하여 기판(1) 표면에 폴리실리콘 잔존물(3B)이 없이 폴리실리콘 패턴(3A)이 형성된다.Referring to FIG. 1 (d), the oxide film 30 is removed by an oxidation removal process to form a polysilicon pattern 3A on the surface of the substrate 1 without the polysilicon residue 3B.

폴리실리콘 패턴(3A)은 반도체 소자의 트랜지스터의 게이트, 캐패시터의 전극, 접지 라인, 플래쉬 메모리의 전극으로 사용된다.The polysilicon pattern 3A is used as a gate of a transistor of a semiconductor element, an electrode of a capacitor, a ground line, and an electrode of a flash memory.

상술한 바와 같이, 본 발명은 반도체 소자에서 트랜지스터의 게이트, 캐패시터의 전극, 접지 라인, 플래쉬 메모리의 전극 등과 같은 전도층을 형성하기 위해 폴리실리콘층 패터닝 공정 후에 남게되는 폴리실리콘 잔존물을 습식 산화시킨 후 제거하므로, 폴리실리콘 잔존물로 인한 소자의 전기적 특성 저하 및 신뢰성 저하를 방지할 수 있다.As described above, the present invention, after wet oxidation of the polysilicon residue remaining after the polysilicon layer patterning process to form a conductive layer such as a gate of a transistor, an electrode of a capacitor, a ground line, an electrode of a flash memory, etc. in a semiconductor device. As a result, it is possible to prevent the deterioration of the electrical characteristics and the reliability of the device due to the polysilicon residue.

Claims (2)

반도체 소자의 도전층을 형성하기 위해 폴리실리콘 증착 및 패터닝 공정 후에 남게되는 폴리실리콘 잔존물을 습식 산화 공정으로 산화시켜 제거하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 후처리 방법.A method of post-processing a polysilicon layer of a semiconductor device, characterized in that the polysilicon residue remaining after the polysilicon deposition and patterning process is removed by a wet oxidation process to form a conductive layer of the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 습식 산화 700 내지 800℃의 온도에서, 1000sccm 내지 20000slpm의 H2가스와 1000sccm 내지 20000sccm의 O2가스를 흘려 1Å/min 내지 100Å/min의 산화속도로 실시하는 것을 특징으로 하는 반도체 소자의 폴리실리콘층 후처리 방법.Polysilicon of the semiconductor device, characterized in that at the temperature of the wet oxidation 700 to 800 ℃, flowing the H 2 gas of 1000sccm to 20000slpm and O 2 gas of 1000sccm to 20000sccm at an oxidation rate of 1 Å / min to 100 Å / min Layer post-treatment method.
KR1019970079326A 1997-12-30 1997-12-30 Method of post treatment a polysilicon layer in a semiconductor device KR100262531B1 (en)

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