KR100260664B1 - 외부 칩 상호 접속부의 유도성 노이즈를 감소시키기 위한 평형 회로 - Google Patents

외부 칩 상호 접속부의 유도성 노이즈를 감소시키기 위한 평형 회로 Download PDF

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Publication number
KR100260664B1
KR100260664B1 KR1019930002428A KR930002428A KR100260664B1 KR 100260664 B1 KR100260664 B1 KR 100260664B1 KR 1019930002428 A KR1019930002428 A KR 1019930002428A KR 930002428 A KR930002428 A KR 930002428A KR 100260664 B1 KR100260664 B1 KR 100260664B1
Authority
KR
South Korea
Prior art keywords
leads
lead
signal
integrated circuit
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019930002428A
Other languages
English (en)
Korean (ko)
Other versions
KR930018710A (ko
Inventor
죠세프 레이날 애틸리오
Original Assignee
죤 제이. 키세인
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 죤 제이. 키세인, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 죤 제이. 키세인
Publication of KR930018710A publication Critical patent/KR930018710A/ko
Application granted granted Critical
Publication of KR100260664B1 publication Critical patent/KR100260664B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/206—Wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structure Of Printed Boards (AREA)
KR1019930002428A 1992-02-25 1993-02-22 외부 칩 상호 접속부의 유도성 노이즈를 감소시키기 위한 평형 회로 Expired - Lifetime KR100260664B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84113992A 1992-02-25 1992-02-25
US841,139 1992-02-25

Publications (2)

Publication Number Publication Date
KR930018710A KR930018710A (ko) 1993-09-22
KR100260664B1 true KR100260664B1 (ko) 2000-07-01

Family

ID=25284121

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930002428A Expired - Lifetime KR100260664B1 (ko) 1992-02-25 1993-02-22 외부 칩 상호 접속부의 유도성 노이즈를 감소시키기 위한 평형 회로

Country Status (6)

Country Link
US (1) US5329170A (https=)
EP (1) EP0558226B1 (https=)
JP (1) JP2591576B2 (https=)
KR (1) KR100260664B1 (https=)
DE (1) DE69330411T2 (https=)
TW (1) TW214631B (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761049A (en) * 1994-09-19 1998-06-02 Hitachi, Ltd. Inductance cancelled condenser implemented apparatus
US6452442B1 (en) 1995-12-04 2002-09-17 Intel Corporation Apparatus for obtaining noise immunity in electrical circuits
DE19927285C2 (de) 1999-06-15 2003-05-22 Eupec Gmbh & Co Kg Niederinduktives Halbleiterbauelement
TW200501580A (en) * 2003-06-23 2005-01-01 Mitac Technology Corp Offset circuit for constraining electromagnetic interference and operation method thereof
CA2915900C (en) * 2013-07-03 2020-01-21 Rosenberger Hochfrequenztechnik Gmbh & Co. Kg Die package with low electromagnetic interference interconnection

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3383618A (en) * 1966-03-10 1968-05-14 Bell Telephone Labor Inc Suppression of intermodulation distortion
US3584235A (en) * 1968-10-18 1971-06-08 Bell Telephone Labor Inc Video defect eliminator
US4398106A (en) * 1980-12-19 1983-08-09 International Business Machines Corporation On-chip Delta-I noise clamping circuit
DE3787137T2 (de) * 1986-02-07 1993-12-09 Fujitsu Ltd Halbleiteranordnung.
US4816984A (en) * 1987-02-06 1989-03-28 Siemens Aktiengesellschaft Bridge arm with transistors and recovery diodes
US5006820A (en) * 1989-07-03 1991-04-09 Motorola, Inc. Low reflection input configuration for integrated circuit packages

Also Published As

Publication number Publication date
KR930018710A (ko) 1993-09-22
EP0558226A3 (https=) 1994-03-23
JPH0613421A (ja) 1994-01-21
TW214631B (https=) 1993-10-11
DE69330411D1 (de) 2001-08-16
DE69330411T2 (de) 2002-05-29
EP0558226B1 (en) 2001-07-11
EP0558226A2 (en) 1993-09-01
JP2591576B2 (ja) 1997-03-19
US5329170A (en) 1994-07-12

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