KR100259718B1 - Line Agent Service System of ATM Switch - Google Patents

Abstract

PURPOSE: A circuit agency service system in an ATM exchange is provided to easily transfer CBR(Continuous Bit Rate) traffic through an ATM network by interfacing an old transmission circuit network, such as DS3, T1, E1, etc., and the ATM network. CONSTITUTION: A cell bus driver part(10) interfaces transmitting/receiving stream cell bus processing parts(20,30) with an upper layer of an ATM exchange and transmits and receives ATM cells. The transmitting stream cell bus processing parts(20) processes an ATM cell supplied from the cell bus driver part(10) and supplies it to an ATM adaptive layer part(110). The receiving stream cell bus processing parts(30) translates the header of a cell supplied from an SAR/channel part(100), adds a 3-byte header and outputs it to an upper layer. A control part(40), communicating with an upper layer processor through a DPRAM(60), controls the whole operation of the ATM exchange. A clock part(50) drives the ATM adaptive layer part(110) and a line interface part(120) normally and supplies clocks to each device according to the control of the control part(40). The DPRAM(60) stores and then outputs the data necessary for the control part(40) to communicate with an upper layer. An SRAM(70) stores and then outputs the data generated according to communication between the control part(40) and the ATM adaptive layer part(110). A buffer part(80) temporarily stores and outputs the data between the SRAM(70) and the ATM adaptive layer part(110). An SRTS(Synchronous Residual Time Stamp) processing part(90) generates synchronization information and supplies it to a clock oscillation part(130). The SAR/channel part(100) is provided with the ATM adaptive layer part(110), the line interface part(120) and the clock oscillation part(130). The transmitting stream cell bus processing parts(20) is comprised of a transmitting cell processing part(21), a transmitting HTT(Header Translation Table)(22), the first transmitting FIFO(23) and the second transmitting FIFO(24).

Description

Line Agent Service System of ATM Switch

The present invention relates to an ATM (Asynchronous Transfer Mode) switch, and more particularly, to an ATM switching circuit substitute service system for easily delivering CBR (Continus Bit Rate) traffic through an ATM network by interfacing an existing circuit network with an ATM network. It is about.

Recently, with the rapid development of the information society, it has been difficult to provide data transmission speed or quality that satisfies user's needs by existing communication methods. As a result, a new communication protocol called ATM has been proposed, and ATM terminals, transmission devices, and exchanges are actively being developed, and some of them are in pilot service. However, no matter how excellent the ATM method, it is impossible to replace all the Korean systems at once. As a result, ATMs and public-switched telephone networks (PSTNs) will coexist in the coming decades. In this situation, there is a need to devise a method for interworking between the ATM and PSTN exchanges.

As described above, there is no conventional device capable of interworking an ATM network and a PSTN, and thus, it is difficult to provide a data transmission speed or quality that satisfies a user's needs without replacing the existing PSTN network with an ATM method. have.

The present invention has been made in view of the above-described problems, by interfacing an existing network such as DS3, T1, E1 and ATM network, the line substitute service of ATM switch for easily delivering CBR traffic through ATM network The purpose is to provide a system.

In order to achieve the above object, the present invention, in the ATM switch, receiving stream cell bus processing unit for processing and outputting the cell received from the subscriber to be recognized by the upper layer; A transmission stream cell bus processing unit for processing and outputting a cell applied from an upper layer; A cell bus driver unit for transmitting / receiving an ATM cell by interfacing the transmission stream cell bus processing unit and the reception stream cell bus processing unit with an upper layer; After buffering a certain amount of data of the internal cell transmitted from the transmission stream cell bus processing unit and converting the data into a specific line shape, the corresponding data stream is output to the line, and the data stream received from the line is converted into cell units. A SAR / channel unit for applying to the receiving stream cell bus processing unit; A clock unit for driving the SAR / channel unit normally and generating and supplying a clock for performing cell bus matching with an external device; A controller for controlling the overall operation of the ATM switch; A first memory unit which stores and outputs data for the controller to communicate with a higher layer; A second memory unit for storing and outputting data generated according to communication between the control unit and the SAR / channel unit; A buffer unit which temporarily stores and outputs the data during data input / output operation between the SAR / channel unit and the second memory unit; And an SRTS processing unit for generating synchronization information for synchronizing frequency between another channel or terminal interworking with each channel of the SAR / channel unit and applying it to the SAR / channel unit side.

On the other hand, the transmission stream cell bus processing unit, the transmission cell processing unit for converting the cell applied from the cell bus driver unit in accordance with the pre-stored header information to convert into a header recognizable by the SAR / channel unit; A transmission header conversion table for storing header information of a cell processed by the transmission cell processing unit and applied to the SAR / channel unit side; A first transmission FIFO for storing cells applied from the transmission cell processing unit so as to be processed one by one in the SAR / channel unit; And a second transmission FIFO for storing cells applied from the cell bus driver and processing the cells one by one in the transmission cell processing unit.

On the other hand, the receiving stream cell bus processing unit for receiving the data from the SAR / channel unit in accordance with the pre-stored header information to the internal cell and transmits to the cell bus driver side; A reception header conversion table for storing header information of a cell processed by the reception cell processor and applied to the cell bus driver; A first receiving FIFO for storing data applied from the SAR / channel unit and processing the received cell processing unit one by one; And a second receiving FIFO for storing the cells applied from the receiving cell processing unit and processing the cells one by one in the cell bus driver unit.

1 is a block diagram of a circuit proxy service system of an ATM switch for DS3 according to a first embodiment of the present invention;

2 is a block diagram of a circuit substitute service system of an ATM switch for a T1 according to a second embodiment of the present invention;

3 is a block diagram of a circuit proxy service system of an ATM switch for an E1 according to a third embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

10: cell bus driver 20: transmission stream cell bus processing unit

21: transmitting cell processing unit 22,32: transmitting / receiving HTT

23: 1st transmission FIFO 24: 2nd transmission FIFO

30: receiving stream cell bus processor 31: receiving cell processor

33: first receiving FIFO 34: second receiving FIFO

40: control unit 50: clock unit

60: DPRAM 70: SRAM

80: buffer unit 90: SRTS processing unit

100,200,300: SAR / channel part 110,210,220: ATM adaptation layer part

120: line interface unit 130: clock generator

220a to 220d: T1 channel processor 320a to 320d: E1 channel processor

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the line substitute service system of the ATM switch for DS3 according to the first embodiment of the present invention, the cell bus driver unit 10, the transmission stream cell bus processing unit 20, the reception stream cell Bus processing unit 30, control unit 40, clock unit 50, DPRAM 60, SRAM 70, buffer unit 80, Synchronous Residual Time Stamp (SRTS) processing unit 90 and Segmentation And Reassembly ) / Channel section 100 is provided.

The cell bus driver unit 10 transmits / receives an ATM cell by interfacing the transmit / receive stream cell bus processing units 20 and 30 with the upper layer of the ATM switch.

The transmission stream cell bus processing unit 20 processes the ATM cells applied from the cell bus driver unit 10 and applies them to the ATM adaptation layer unit 110.

The reception stream cell bus processing unit 30 converts the header so that the cell applied from the SAR / channel unit 100 can be recognized at the upper side, and attaches a 3-byte header to output the upper side. At this time, 8-bit to 16-bit parallel conversion is performed.

The control unit 40 communicates with the upper layer processor through the DPRAM 60 and controls the overall operation of the ATM switch.

The clock unit 50 normally drives the ATM adaptation layer unit 110 and the line interface unit 120 and supplies a clock to each device under the control of the controller 40 to perform cell bus matching with the outside. .

The DPRAM 60 stores and outputs data for the controller 40 to communicate with higher layers.

The SRAM 70 stores and outputs data generated by the communication between the control unit 40 and the ATM adaptation layer unit 110.

The buffer unit 80 temporarily stores data between the SRAM 70 and the ATM adaptation layer unit 110 and outputs the data.

The SRTS processing unit 90 generates synchronization information for synchronizing frequency between another channel or terminal interworking with each channel of the SAR / channel unit 100 and applies it to the clock oscillation unit 130.

The SAR / channel unit 100 includes an ATM adaptation layer unit 110, a line interface unit 120, and a clock oscillator unit 130, and the ATM adaptation layer unit 110 transmits the transmission stream cell bus processor 20. After buffering a predetermined amount of data of the internal cells, the cell is converted into a circuit form according to the DS3 format, and the converted data stream is transmitted to the DS3 line by performing B3ZS coding through the DS3 line interface unit 120. On the contrary, the data stream received from the DS3 line is converted into units of cells and transmitted to the reception stream cell bus processor 30.

Meanwhile, the transmission stream cell bus processing unit 20 includes a transmission cell processing unit 21, a transmission HTT (Header Translation Table; header conversion table) 22, a first transmission FIFO 23, and a second transmission FIFO 24. do.

The transmitting cell processing unit 21 converts the 16-bit cell applied from the cell bus driver unit 10 into 8-bit parallel data according to the header information stored in the transmitting HTT 22 and then recognizes the SAR / channel unit 100. Convert it to the possible header and send it.

The transmitting HTT 22 stores header information of a cell processed by the transmitting cell processing unit 21 and applied to the SAR / channel unit 100 side.

Since the first transmission FIFO 23 has a limitation of the next stage processing capability in the SAR / channel unit 100, the cells transmitted from the transmitting cell processing unit 21 may be stored to be processed one by one in the SAR / channel unit 100. Do it.

The second transmission FIFO 24 stores the cell applied from the cell bus driver unit 10 so that it can be processed one by one in the transmission cell processing unit 21 because there is a limit in the next stage processing capability in the transmission cell processing unit 21. .

Meanwhile, the reception stream cell bus processor 30 includes a reception cell processor 31, a reception HTT 32, a first reception FIFO 33, and a second reception FIFO 34.

The receiving cell processing unit 31 converts 8-bit parallel data applied from the SAR / channel unit 100 into 16-bit cells according to the header information stored in the receiving HTT 32 and transmits the same to the cell bus driver unit 10. .

The reception HTT 32 stores header information of a cell processed by the reception cell processing unit 31 and applied to the cell bus driver unit 10.

Since the first receiving FIFO 33 has a limitation of the next stage processing capability in the receiving cell processing unit 31, the first receiving FIFO 33 stores data applied from the SAR / channel unit 100 so that the receiving cell processing unit 31 can process them one by one. .

Since the second receiving FIFO 34 has the limitation of the next stage processing capability in the cell bus driver unit 10, the second receiving FIFO 34 stores the cell applied from the receiving cell processing unit 31 so that the cell bus driver unit 10 processes them one by one. Do it.

The operation according to the first embodiment of the present invention configured as described above is described in detail as follows.

The present invention can be divided into a data reception operation from a subscriber and a data transmission operation to a subscriber. In the following description, the operation of receiving data from subscribers is performed. Comes down). When the control unit 40 receives the corresponding command, the control unit 40 changes the reception HTT 32 of the ATM adaptation layer unit 110 and the reception stream cell bus processing unit 30 and the transmission HTT 22 of the transmission stream cell bus processing unit 20. Set the table values appropriately. Thereafter, the DS3 data applied from the subscriber is converted into an ATM cell while passing through the line interface unit 120 and the ATM adaptation layer unit 110. The converted ATM cell is stored in the first receiving FIFO 33 of the receiving stream cell bus processing unit 30, and the receiving cell processing unit 31 reads the ATM cell stored in the first receiving FIFO 33 so as to read the corresponding ATM cell. After the headers of the cells are converted, they are stored in the second receiving FIFO 34. Therefore, the data stored in the second receiving FIFO 34 is transmitted to the ATM switch via the cell bus driver unit 10.

The above operation will be described in more detail as follows. The SAR / channel unit 100 converts the data stream received from the DS3 line into units of cells and transmits the data stream to the reception stream cell bus processing unit 30. Accordingly, when the 8-bit 53-byte data is stored in the first receiving FIFO 33 of the receiving stream cell bus processing unit 30, the receiving cell processing unit 31 reads the first 1 byte and receives the receiving HTT ( The header is stored in the second receiving FIFO 34 in the form of a header stored in 32). At this time, the data applied from the transmission HTT 22 is composed of four 16-bit four words, and is stored in synchronization with a clock of 9.72 MHz obtained by dividing 19.44 MHz in two parts in the SRTS processing unit 90. After the transmission of the header part, the receiving cell processor 31 reads the remaining data stored in the first receiving FIFO 33 and discards the remaining 8 bits 4 bytes of the header and discards the payload 8 bits 48 bytes 16 bits 24. After conversion to a word, it is stored in the second receiving FIFO 34 in synchronization with a clock of 9.72 MHz. When 28 words of data are written to the second receiving FIFO 34, a control signal is applied to the upper layer to indicate that there is a cell bus to be transmitted. When a read enable signal is applied from the upper layer, 16-bit 28 words of data are transmitted to the cell. If the read enable signal is not applied from the upper level through the bus driver 10, the data stored in the corresponding second receiving FIFO 34 is deleted.

On the other hand, in the data transmission operation to the subscriber side, first, the cell bus applied to the transmission stream cell bus processing unit 20 through the cell bus driver unit 10 is composed of 56-byte cells, that is, 16-bit 28 words. . The authorized cell is stored in the second transmission FIFO 24, and the transmission cell processing unit 21 reads the first 16 bits of the corresponding cell, that is, one word of data, and if the cell is normal, 27 cells consisting of the remaining 16 bits are read. Stored in the second receiving FIFO 34. At this time, the transmitting cell processor 21 applies a clock and an enable signal of 9.72 MHz, which can read a cell, to the second receiving FIFO 34. Subsequently, the transmitting cell processor 21 reads the header portion of the cell bus, that is, three words, and supplies necessary information such as 12 bits of VPI (Virtual Path Identifier) information, 16 bits of VCI (Virtual Channel Identifier) information, and 3 bits of line information. If it is normal compared with the contents of the transmission HTT 22, the information of the transmission HTT 22 is replaced with the cell header, and a 5 byte header composed of 8 bits is provided to the first transmission FIFO 23 in synchronization with a clock of 9.72 MHz. Save it. At this time, when the line information becomes an important element constituting the address of the header, the address informs the validity of the cell bus being transmitted and whether it is the actual transmission cell or the test cell in addition to the VPI and VCI information to be actually converted. Send information together. Subsequently, if the header part is normal, the converted header is stored in the first transmission FIFO 23, and the first transmission FIFO 23 converts the payload 16-bit 24-word, which is the actual data part except the header part, into 8-bit 48 bytes. Store in Accordingly, when one cell bus 53 bytes is stored, the first transmission FIFO 23 notifies that the cell bus is stored in the ATM adaptation layer unit 110 of the SAR / channel unit 100, and correspondingly, the ATM adaptation layer unit ( When the enable signal is applied from 110, the cell bus is applied to the ATM adaptation layer unit 110 according to a clock of 9.72 MHz applied from the transmission cell processing unit 21. The clocks used at this time are generated and supplied by the SRTS processor 90. Therefore, the ATM adaptation layer unit 110 collects the corresponding data and reconstructs it into DS3 and transmits the data to the subscriber through the line interface unit 120.

On the other hand, the line substitute service system of the ATM switch for T1 according to the second embodiment of the present invention is shown in Figure 2 attached to the figure, as can be seen, ATM adaptation layer unit 210 and four T1 channels Since only the SAR / channel unit 200 composed of the processing units 220a to 220d is different from the above-described line substitute service system of the ATM switch for DS3 and the other configuration and operation are the same, in the second embodiment of the present invention, the SAR / channel unit 200 Only the operation of) is described.

The SAR / channel unit 200 of the line proxy service system of the T1 ATM switch includes an ATM adaptation layer unit 210 and four T1 channel processing units 220a to 220d that are responsible for the T1 frame function. Referring to the data transmission process, the ATM adaptation layer unit 210 divides the contents of the 8-bit 53-byte cell bus that is applied in synchronization with the 9.72 MHz from the transmission stream cell bus processing unit 20 into four channels, and the corresponding data. And information are applied to the respective T1 channel processing units 220a to 220d. Accordingly, each of the T1 channel processing units 220a to 220d removes the AAL1 function from the applied cell bus, converts the code for each T1, that is, converts the code to the HDB3ZERO code, and transmits it to the subscriber through each channel.

In addition, when the process of receiving data from the subscriber is explained, each T1 channel processor 220a to 220d removes the conversion code from each information and data carried in the HDB3ZERO code received from the four subscribers, and then the ATM adaptation layer unit. (210) side. The ATM adaptation layer unit 210 adds the AAL1 function to convert four channel data and information into a 53-byte cell bus and applies the received stream cell bus processor 30 in synchronization with a clock of 9.72 MHz.

On the other hand, the line substitute service system of the ATM switch for the E1 according to the third embodiment of the present invention is shown in Figure 3 attached to the figure, as can be seen, ATM adaptation layer unit 310 and four E1 channels Since only the SAR / channel unit 300 composed of the processing units 320a to 320d is different from the above-described line substitute service system of the ATM switch for DS3 and the other configuration and operation are the same, in the third embodiment of the present invention, the SAR / channel unit 300 Only the operation of) is described.

The SAR / channel unit 300 of the line proxy service system of the ATM switch for the E1 has an ATM adaptation layer unit 310 and four E1 channel processing units 320a to 320d that are responsible for the E1 frame function. In describing the data transmission process, the ATM adaptation layer unit 310 divides the contents of the 8-bit 53-byte cell bus, which is applied in synchronization with the 9.72 MHz from the transmission stream cell bus processing unit 20, into four channels. And information are applied to each of the E1 channel processing units 320a to 320d. Accordingly, each of the E1 channel processing units 320a to 320d removes the AAL1 function from the applied cell bus, converts the codes for each E1, that is, converts the codes to HDB3ZERO codes, and transmits them to the subscriber side through each channel.

In addition, when the process of receiving data from the subscriber is explained, each information and data carried in the HDB3ZERO code transmitted from the four subscribers are removed from the respective E1 channel processing units 320a to 320d, and then the ATM adaptive layer unit (310) side. The ATM adaptation layer unit 310 adds the AAL1 function, converts four channel data and information into a 53-byte cell bus, and applies it to the reception stream cell bus processor 30 in synchronization with a clock of 9.72 MHz.

As described above, the present invention enables the ATM exchanger and the existing PSTNs such as DS3, T1, and E1 to be interworked, so that CBR traffic can be easily transmitted through the ATM network, thereby improving data transmission speed and quality. do.

Claims (3)

An ATM switch comprising: a receiving stream cell bus processing unit for processing and outputting a cell received and applied from a subscriber to be recognized by a higher layer; A transmission stream cell bus processing unit for processing and outputting a cell applied from an upper layer; A cell bus driver unit for transmitting / receiving an ATM cell by interfacing the transmission stream cell bus processing unit and the reception stream cell bus processing unit with an upper layer; After buffering a certain amount of data of the internal cell transmitted from the transmission stream cell bus processing unit and converting the data into a specific line shape, the corresponding data stream is output to the line, and the data stream received from the line is converted into cell units. A SAR / channel unit for applying to the receiving stream cell bus processing unit; A clock unit for driving the SAR / channel unit normally and generating and supplying a clock for performing cell bus matching with an external device; A controller for controlling the overall operation of the ATM switch; A first memory unit which stores and outputs data for the controller to communicate with a higher layer; A second memory unit for storing and outputting data generated according to communication between the control unit and the SAR / channel unit; A buffer unit which temporarily stores and outputs the data during data input / output operation between the SAR / channel unit and the second memory unit; And a SRTS processing unit for generating synchronization information for synchronizing frequency between another channel or terminal interworking with each channel of the SAR / channel unit and applying it to the SAR / channel unit side. . The method of claim 1, The transmission stream cell bus processing unit includes: a transmission cell processing unit converting a cell applied from the cell bus driver unit according to previously stored header information and converting the cell to a header recognizable by the SAR / channel unit; A transmission header conversion table for storing header information of a cell processed by the transmission cell processing unit and applied to the SAR / channel unit side; A first transmission FIFO for storing cells applied from the transmission cell processing unit so as to be processed one by one in the SAR / channel unit; And a second transmitting FIFO for storing the cells applied from the cell bus driver and allowing the transmitting cell processing unit to process the cells one by one. The method of claim 1, The reception stream cell bus processing unit converts data applied from the SAR / channel unit into internal cells according to previously stored header information and transmits the data to the cell bus driver; A reception header conversion table for storing header information of a cell processed by the reception cell processor and applied to the cell bus driver; A first receiving FIFO for storing data applied from the SAR / channel unit and processing the received cell processing unit one by one; And a second receiving FIFO for storing cells applied from the receiving cell processing unit so that the cell bus driver unit can process them one by one.