KR100255891B1 - 반도체 집적 회로내의 기생부하 산출방법 - Google Patents
반도체 집적 회로내의 기생부하 산출방법 Download PDFInfo
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- KR100255891B1 KR100255891B1 KR1019960032518A KR19960032518A KR100255891B1 KR 100255891 B1 KR100255891 B1 KR 100255891B1 KR 1019960032518 A KR1019960032518 A KR 1019960032518A KR 19960032518 A KR19960032518 A KR 19960032518A KR 100255891 B1 KR100255891 B1 KR 100255891B1
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 97
- 238000004364 calculation method Methods 0.000 title claims description 22
- 239000004065 semiconductor Substances 0.000 title description 18
- 238000000034 method Methods 0.000 claims description 38
- 230000002093 peripheral effect Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 10
- 238000013461 design Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000013341 scale-up Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (8)
- 레이아웃 데이터 또는 심볼릭 데이터내의 기생 부하를 산출하는 기생 부하 산출 방법에 있어서, 기준 레이아웃 패턴 데이터와 견적된 기생 부하로 구성된 기준 패턴 데이터를 포함하는 기준 모델을 미리 준비하는 단계로서, 상기 기준 레이아웃 패턴 데이터는 3차원 영역의 하나 이상의 연결 패턴들에 기초되고, 상기 견적된 기생 부하는 상기 하나 이상의 연결 패턴들 중의 중첩된 연결 패턴들과 중첩되지 않은 연결 패턴들 둘 다를 위한 상기 3차원 영역의 기생 부하에 기초되는, 상기 기준 모델을 미리 준비하는 단계와, 상기 견적된 기생 부하에 기초하여 상기 기생 부하를 계산하기 위해서, 상기 레이아웃 데이터 또는 상기 심볼릭 데이터로 표시되는 레이아웃 패턴 데이터와 상기 기준 레이아웃 패턴 데이터 사이의 3차원 패턴 매칭 동작을 수행하는 단계를 포함하는 기생 부하 산출 방법.
- 기준 패턴 데이터 준비 방법에 있어서, 특정 연결 패턴을 기준 연결 패턴으로서 한정하는 단계와, 상기 기준 연결 패턴을 포함하는 3차원 영역을 미리 결정하는 단계로서, 상기 3차원 영역내에 포함된 어떤 다른 연결 패턴들도 주변 연결 패턴들을 한정하는 상기 3차원 영역을 미리 결정하는 단계와, 상기 3차원 영역내의 기판, 상기 기준 연결 패턴 및 상기 주변 연결 패턴들의 레이아웃에 기초하여 기준 패턴 데이터를 준비하는 단계로서, 상기 기준 패턴 데이터는 상기 기준 연결 패턴과 적어도 하나의 경사 주변 연결 패턴 사이의 관계에 관한 정보를 포함하고, 상기 경사 주변 연결 패턴은, 상기 3차원 영역의 상기 주변 연결 패턴들 중의 하나이며, 상기 기준 연결 패턴과 수직방향으로 중첩되지 않으며, 상기 기준 연결 패턴과 수평방향으로 중첩되지 않는, 상기 기준 패턴 데이터를 준비하는 단계를 포함하는 기준 패턴 데이터 준비 방법.
- 제2항에 있어서, 복수의 3차원 영역들은 상기 기준 연결 패턴의 폭방향, 길이방향 및 높이방향으로 분할함으로써 결정되는 기준 패턴 데이터 준비 방법.
- 제3항에 있어서, 상기 기준 연결 패턴 및 주변 연결 패턴들은 상기 각각의 3차원 영역들에 의해 한정된 메시 패턴 공간내에서 추출되는 기준 패턴 데이터 준비 방법.
- 제3항에 있어서, 상기 기준 패턴 데이터는, 상기 기준 및 주변 연결 패턴들의 위치들, 형상 및 두께와, 산화막의 두께와, 기판과, 관통구멍들의 유무에 관한 정보를 포함하도록 준비되는 기준 패턴 데이터 준비 방법.
- 제2항에 있어서, 상기 기준 패턴 데이터는 상기 3차원 영역내의 상기 기판과 상기 연결 패턴들의 레이아웃 패턴으로부터 추출된 레이아웃 패턴 데이터와, 상기 레이아웃 패턴에 대응하는 견적된 기생 부하를 나타내는 데이터를 포함하는 기준 패턴 데이터 준비 방법.
- 제6항에 있어서, 상기 기준 패턴 데이터는 프로세스 조건, 패키지 의존성과, 동작 주파수에 대응하는 견적된 기생 부하를 나타내는 데이터를 포함하는 기준 패턴 데이터 준비 방법.
- 제6항에 있어서, 여러 가지 크기들의 상기 3차원 영역들의 각각에 대해 상기 패턴 매칭 동작에 필요한 상기 기준 패턴 데이터를 추출하는 단계와, 각각의 3차원 영역내의 상기 기준 연결 패턴 상에서 상기 견적된 기생 부하를 상기 기준 패턴 데이터의 일부로서 얻는 단계를 더 포함하는 기준 패턴 데이터 준비 방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP95-195046 | 1995-07-31 | ||
JP7195046A JP2800881B2 (ja) | 1995-07-31 | 1995-07-31 | 配線寄生負荷算出方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970008457A KR970008457A (ko) | 1997-02-24 |
KR100255891B1 true KR100255891B1 (ko) | 2000-05-01 |
Family
ID=16334651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960032518A KR100255891B1 (ko) | 1995-07-31 | 1996-07-30 | 반도체 집적 회로내의 기생부하 산출방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5847967A (ko) |
JP (1) | JP2800881B2 (ko) |
KR (1) | KR100255891B1 (ko) |
DE (1) | DE19630927A1 (ko) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6405072B1 (en) | 1991-01-28 | 2002-06-11 | Sherwood Services Ag | Apparatus and method for determining a location of an anatomical target with reference to a medical apparatus |
US6061508A (en) * | 1997-07-03 | 2000-05-09 | International Business Machines Corporation | Modeling and processing of on-chip interconnect capacitance |
US6175947B1 (en) | 1998-04-20 | 2001-01-16 | International Business Machines Corporation | Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization |
KR100519504B1 (ko) * | 1998-06-30 | 2005-11-25 | 매그나칩 반도체 유한회사 | 반도체장치의 기생커패시턴스 측정 패턴 및 그측정 방법 |
DE19900980C1 (de) | 1999-01-13 | 2000-05-11 | Siemens Ag | Verfahren und Anordnung zur Verifikation eines Layouts einer integrierten Schaltung mit Hilfe eines Rechners sowie dessen Anwendung zur Herstellung einer integrierten Schaltung |
JP3230233B2 (ja) * | 1999-02-05 | 2001-11-19 | 日本電気株式会社 | 半導体集積回路設計装置及びその配線制御方法並びに配線制御プログラムを格納した記憶媒体 |
US6363516B1 (en) * | 1999-11-12 | 2002-03-26 | Texas Instruments Incorporated | Method for hierarchical parasitic extraction of a CMOS design |
KR100367615B1 (ko) * | 2001-01-06 | 2003-01-10 | 엘지전자 주식회사 | 디지탈 티브이의 리모콘을 이용한 방송정보 표시장치 |
AU2003224379A1 (en) * | 2002-05-16 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer |
US7281229B1 (en) * | 2004-09-14 | 2007-10-09 | Altera Corporation | Method to create an alternate integrated circuit layout view from a two dimensional database |
US7231626B2 (en) * | 2004-12-17 | 2007-06-12 | Lsi Corporation | Method of implementing an engineering change order in an integrated circuit design by windows |
US20080260095A1 (en) * | 2007-04-16 | 2008-10-23 | Predrag Sukovic | Method and apparatus to repeatably align a ct scanner |
JP2009025891A (ja) * | 2007-07-17 | 2009-02-05 | Nec Electronics Corp | 半導体集積回路の設計方法及び設計プログラム |
JP2009026829A (ja) * | 2007-07-17 | 2009-02-05 | Nec Electronics Corp | 半導体集積回路の設計方法及びマスクデータ作成プログラム |
JP4580006B2 (ja) * | 2008-07-10 | 2010-11-10 | パナソニック株式会社 | 半導体集積回路のマスクレイアウト設計データの検証方法 |
JP2011215681A (ja) | 2010-03-31 | 2011-10-27 | Fujitsu Ltd | 配線間隔検証プログラムおよび配線間隔検証装置 |
JP6086017B2 (ja) * | 2013-04-17 | 2017-03-01 | 富士通セミコンダクター株式会社 | データ処理装置、及び、データ処理プログラム |
US9892218B2 (en) * | 2016-04-01 | 2018-02-13 | Synopsys, Inc. | Parasitic-aware blockage |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4651284A (en) * | 1984-07-27 | 1987-03-17 | Hitachi, Ltd. | Method and system of circuit pattern understanding and layout |
JPH0355868A (ja) * | 1989-07-24 | 1991-03-11 | Nec Corp | 電子回路の配線間容量算出方法 |
US5086477A (en) * | 1990-08-07 | 1992-02-04 | Northwest Technology Corp. | Automated system for extracting design and layout information from an integrated circuit |
JPH04273583A (ja) * | 1991-02-28 | 1992-09-29 | Fujitsu Ltd | 配線負荷算出方法 |
US5452224A (en) * | 1992-08-07 | 1995-09-19 | Hughes Aircraft Company | Method of computing multi-conductor parasitic capacitances for VLSI circuits |
JPH0729981A (ja) * | 1993-06-24 | 1995-01-31 | Mitsubishi Electric Corp | 仮想配線負荷評価方法及び仮想配線負荷評価装置 |
-
1995
- 1995-07-31 JP JP7195046A patent/JP2800881B2/ja not_active Expired - Fee Related
-
1996
- 1996-07-30 KR KR1019960032518A patent/KR100255891B1/ko not_active IP Right Cessation
- 1996-07-31 DE DE19630927A patent/DE19630927A1/de not_active Withdrawn
- 1996-07-31 US US08/688,736 patent/US5847967A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5847967A (en) | 1998-12-08 |
JP2800881B2 (ja) | 1998-09-21 |
JPH0944550A (ja) | 1997-02-14 |
KR970008457A (ko) | 1997-02-24 |
DE19630927A1 (de) | 1997-02-06 |
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