US8239804B2 - Method for calculating capacitance gradients in VLSI layouts using a shape processing engine - Google Patents
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- the present invention relates generally to the field of design automation of Very Large Scale Integrated circuit chips, and more particularly, to a system and method for extracting data for estimating the capacitance and for verifying and extracting electrical parameters based on geometric layouts.
- VLSI Very Large Scale Integrated
- Computer-aided design (CAD) tools for parasitic capacitance extraction of a VLSI layout is composed of two main components: a shape processing engine and a capacitance calculation engine.
- the role of the shape processing engine is to trace the nets of the VLSI layout, followed by decomposing each one of them into elementary patterns whose capacitances are computed using the capacitance calculation engine.
- the capacitances of the elementary patterns are then assembled into net capacitances which are ultimately passed to a circuit netlist for further processing by other CAD tools, such as timing, power, signal integrity, reliability tools, and the like.
- the capacitance calculation engine relies on both lookup tables and capacitance formulas for computing the capacitances of the elementary patterns.
- the circuit characterization generally begins with a circuit extraction.
- the circuit extraction software such as a netlist extractor, is typically utilized to extract various circuits that are required to be simulated, from a VLSI circuit layout.
- the result of such circuit extraction includes not only the circuitry itself, but also includes the parasitic capacitance and parasitic resistance that are inherent within the interconnect materials.
- shape-processing algorithms for detecting and reporting each capacitance event in the VLSI circuit layout.
- One important step is to enable the extraction tool to compute the gradients of the electrical parameter of a given net with respect to the process parameters influencing the shapes of which the said net is composed. These gradients can then be used to build parasitic capacitance (and resistance) models that are valid over full ranges of process parameter variations thus avoiding the need for multiple corner analysis or multiple extraction runs.
- the two main difficulties encountered in gradient computation are: 1) how to enable the shape processing engine to translate the variations in physical edges into variations in the edges of the elementary patterns into which the shape processing engine decomposes each net in the layout; and 2) how to enable the capacitance calculation engine to combine the gradients of the elementary patterns into a gradient of the parent net while taking into account gradient information provided by the lookup table as well as gradient information computed directly based on the capacitance formulae encoded in the capacitance calculation engine.
- the prior art does not address the problem of including shape variations due to semiconductor process and manufacturing tolerances in the capacitance extraction system and method. Nor does it address, more specifically, the problem of computing capacitance gradients with respect to those shape variations.
- Another reference where an attempt at computing capacitance gradients is made is “Rapid Method to Account for Process Variations in Full-Chip Capacitance Extraction,” by A. Labun, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, June 2004, pp. 941-951.
- the prior art suffers from two main drawbacks:
- the method and system preferably includes a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine.
- the variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns into which the layout of the integrated circuit is decomposed.
- the gradient calculation engine computes capacitance gradients by combining information from pre-existing gradients in a capacitance lookup table and analytical expressions of capacitance correction factors.
- a method and a system are provided for determining capacitance gradients of an integrated circuit chip layout in order to achieve a better performance.
- the method includes: a) decomposing one or more layout shapes into elementary patterns; b) translating physical parameter variations into variations on parameters of elementary patterns into which the layout shapes are decomposed; c) computing the capacitance gradients of the elementary patterns; d) combining the capacitance gradients into capacitance gradients of one or more layout shapes of the chip layout; and f) transferring capacitance gradient values to a netlist providing electrical-level descriptions of the chip layout.
- the gradients are preferably determined from analytical expressions of capacitance correction factors in which the capacitance can be a net-to-net capacitance or lateral, fringing, up and down capacitances for a center shape.
- a variational mapping is generated along with an associated data structure from the physical edges of the VLSI layout shapes onto the virtual edges of the elementary patterns into which the shapes are decomposed.
- the invention further provides an additive formula for computing the capacitance gradient associated with a single elementary shape is then provided, and a formula for combining gradients issued from the lookup tables with gradients issued from the parameterized capacitance expressions in the capacitance calculation engine. It is followed by an additive formula for assembling the capacitance gradient of a net from the capacitance gradients of its elementary shapes.
- FIG. 1 is a flow chart according to an embodiment of the invention showing how shape processing feeding a variational mapping coupled to gradient computations reflects variations in the shapes of an original VLSI layout.
- FIG. 2 a illustrates an example of a target net surrounded by various source nets.
- FIG. 2 b shows how areas are created on the target net of FIG. 2 a.
- FIG. 2 c is an illustrative example of a virtual edge as contrasted with a physical edge that determines the impact of shape variations of area virtual edges.
- FIG. 2 d is an illustrative example of an area delimited on a target net shape along with an accompanying data structure derived from the area geometric information.
- FIG. 3 a through 3 e depicts various examples of the areas on a target net relative to the shapes that are present below and above the target nets.
- FIG. 4 illustrates how the area data structure changes from one layer to another.
- FIGS. 5 and 6 represent flowcharts of a variational map used in the shape processing engine to assign variation coefficients to virtual edges based on variations of physical edges.
- FIG. 7 is a representation of the parameter abstraction used in one preferred embodiment of the present invention.
- FIG. 8 is an example of the variational mapping from the physical edges to the virtual edges in light of the parameter abstraction of FIG. 7 .
- FIG. 9 is a further illustration of the variational map and the method of assigning multipliers to the virtual edges of an area.
- FIG. 10 is a flowchart showing the capacitance and gradient calculation engine.
- FIG. 11 is a flowchart showing the upward pass in the capacitance and gradient calculation engine.
- FIG. 12 is a flowchart showing the downward pass in the capacitance and gradient calculation engine.
- FIG. 13 illustrates a gradient aware lookup table which includes gradient information of elementary patterns in line with the parameter abstraction of FIG. 7 .
- FIG. 14 is an illustration of a horizontal splitting algorithm used in the capacitance gradient computation.
- FIG. 15 is an illustration of a ghost wire and the vertical splitting algorithm for capacitance gradient computation.
- FIG. 16 is a flowchart of an embodiment of the invention showing table lookup capacitances and algorithmic capacitances and gradients combined to create a net-to-net capacitance and capacitance gradients.
- FIG. 1 there is shown a flowchart of a preferred embodiment of the invention that corrects the shortcomings found in the prior art and incorporates the calculation of gradients for capacitances based on the shape processing of a VLSI layout.
- the flowchart shown in FIG. 1 further illustrates an embodiment of the invention showing a shape processing engine 100 feeding a variational map engine 110 whose role is to reflect variations in the shapes of the original VLSI layout.
- the input to the system and method is a VLSI layout file 105 describing the shapes of all the devices and wires connecting them on the integrated circuit (IC).
- These layout files can advantageously make use of industry standard formats, e.g., a format known as GDSII.
- Another input to the capacitance extraction engine 120 consist a technology file 107 describing various device and wiring layers used in the manufacturing of the IC. Such layer description includes the nature of each layer (diffusion, oxide, poly, via, interconnect) as well as its thickness.
- the technology file 107 also contains information about the dielectric stack (thicknesses and dielectric constants) used to separate horizontally between wires in each layer as well as vertically between wires in two successive layers.
- One main usage of the vertical information provided in the technology file 107 is to enable the shape processing engine 100 to ascertain the net continuity in case a given connection spans several wiring layers.
- the variations in the shapes of the decomposed VLSI layouts 115 lead to a “divide-and-conquer” method to a VLSI extraction method that applies to nominal values of shape sizes, and which is enabled to work with shape sizes undergoing variations or perturbations due to process and manufacturing tolerances.
- the variational map engine 110 will be hereinafter described in more detail with reference to FIGS. 5 and 6 .
- the capacitances of the decomposed VLSI layout 115 are inputted into a capacitance calculation engine 120 driving a gradient calculation engine 130 , wherein the gradients of the capacitances of the shapes 130 of the decomposed VLSI layout are computed.
- the gradients measure the “sensitivities” of shape capacitances with respect to changes in their geometric parameters.
- the geometric parameters include the horizontal dimensions of the shapes (e.g., length, width) as well as their vertical dimensions (e.g., thickness.
- the present embodiment thus creates a new net-to-net capacitance augmented by adding thereto the calculated gradient values 140 .
- the capacitance calculation engine 120 can operate on simpler patterns and compute their capacitances more readily. Another input that eases the burden on the capacitance calculation engine 120 is a capacitance lookup table 117 that contains pre-computed capacitance values for a subset of the elementary patterns that result from the layout decomposition. Other elementary patterns that are not included in the lookup table can obtain their capacitances computed using algorithmic formulas that are programmed within the capacitance calculation engine 120 . The coupling capacitance of any pair of neighboring nets in the layout is computed based on the capacitances of the areas (elementary patterns) into which they are decomposed.
- the final step of the capacitance extraction method consists of passing the net-to-net capacitance values 140 to a netlisting program 145 which produces an electrical-level description of the devices and wires connecting them.
- This description is typically used either in a circuit simulation program such as SPICE, well known in the art, that outputs a SPICE netlist 150 used for the accurate electrical analysis of the layout or in other computer-aided design programs such as programs for timing, signal integrity and power analysis of the IC, but which incorporates therein the necessary gradient information.
- source and target nets are used to describe the preferred embodiment of the present invention, in which target net-to-net capacitance 210 is determined.
- the capacitance is the sum of contributions from a set of source nets 230 in the vicinity of the target net 210 .
- the target and source nets typically span several conducting layers of the VLSI chip. Some source nets 230 may lie in the same layers as the target net 210 while others (with fill patterns) may lie in other layers than the target net. These other layers can be either above 220 or below 230 the target net.
- FIG. 2 b is an example of the principle of such decomposition using physical edges of the target net and neighboring source nets.
- Each physical edge of a selected source net shape e.g., 220 , results in a virtual edge on the target net shape.
- Virtual edges and physical edges on the target net 210 combine to delimit rectangular regions known as areas 250 . It is worth noting that in reference of the target net shape 210 , some areas result in a metal overlap between the target and source nets 230 , while other areas display no such overlap.
- FIG. 2 c an example of shape modification or variation is provided along with its impact on the placement of virtual edges 270 .
- the physical edges of the target net areas 280 may also incur in a displacement due to design and manufacturing tolerances in the physical edges of the target net itself.
- FIG. 2 d is yet another illustration of the area delimited on a target net shape accompanied with the data structure used to represent the area in a computer program.
- the data structure is defined in reference to the area's own composition as well as in reference to the shapes that are in its immediate vicinity.
- the area illustrated in FIG. 2 d is composed of the overlap shapes in layers M 1 and M 2 with no shape from layer M 3 .
- the four edges of the area are related to neighboring shapes with the edge-to-edge distances shown as North (N), South (S), East (E) and West (W) edges of the area.
- the area has a distance 0 to the portion of the target net on layer M 1 , while on layer M 2 , it has a distance d of 50.
- the area has a distance of infinity, meaning that there is no shape on layer M 3 to the west of the area in question.
- FIGS. 3 a through 3 e are further illustrations of how the areas on a target net M 1 are modified as the shape of the net is traced from left to right, each having the horizontal 2D projection on the left and the vertical elevation on the right.
- the area in question is provided by the rectangle with the filled pattern.
- the vertical dashed lines are used to emphasize the fact that the edges from the area often (but not always) result from the projection of the physical edges of the shapes below or above the target shape. Still referring to FIG.
- FIG. 3 b shows yet another area on the target net, but the area is provided with virtual edges from physical edges projected by two different though neighboring shapes on layer M 2 . As a result, the area on FIG. 3 b has no shape overlapping the shape on layer M 1 .
- FIG. 3 c illustrates a virtual edge on a target net area coming from a physical edge in two or more layers above or below the target net. Indeed, the right virtual edge on the target net results from the left physical edge of the shape on layer M 3 whereas the left virtual edge results from the shape on layer M 2 .
- FIG. 3 d shows the target net area having three shapes overlapping on layers M 1 , M 2 and M 3 .
- FIG. 2 e shows that the last area on the target net is made of the left virtual edge projected from the shape on layer M 2 and the physical edge of the target net itself The last area has shapes from layers M 1 and M 3 overlapping, but no shapes overlap from layer M 2 .
- FIGS. 4 a and 4 b contrast the contents of the data structure defined in FIG. 3 d for two of the cases described in FIG. 3 a through 3 e .
- the contrast is defined in terms of the neighboring content in the instance where an area shape on M 2 is present vs. a case where an area shape on M 2 is absent.
- the left data structure refers to the case illustrated in FIG. 3 a
- the right data structure refers to the one shown in FIG. 3 e .
- the remaining edges of the central shape as well as all the edges of the central shape in the right figure ( FIG. 4 b ) can be related to their neighbors in a similar manner.
- FIG. 5 is a flowchart of the variational mapping engine that transforms variations on the physical edges of shapes into variations on the virtual edges of areas.
- the variational mapping engine takes as input the proximity map of the nets in the VLSI layout 500 .
- the proximity map is made of all the nets in the VLSI layout along with the shapes that are in the proximity of each net.
- the proximity is defined by a maximum distance between shapes and results in including in the proximity map shapes that are separated by less than the predefined maximum distance. It is worth noting that members of the proximity list of a given target net includes not only shapes on the same layer of the net, but also shapes that are in layers below or above the target net.
- the first step in the variational mapping uses edges of the proximity shapes 510 to project virtual edges on the target shape 520 .
- the virtual edges (also referred to as slices) can be oriented in either the X direction or the Y direction.
- the second step 520 in the variational mapping is to augment each slice resulting from the first step with what is referenced to according to one preferred embodiment of the invention, as an edge change array.
- Each of such arrays preferably consists of three components.
- the first component quantifies the impact of changes in the physical edges of the target shape itself.
- the second component quantifies the impact of changes in the physical edges of the shapes immediately below the target shape.
- the third component quantifies the impact of changes in the physical edges of the shapes immediately above the target shape.
- the restriction to three components is not limiting, and one skilled in the art will appreciate that the size of the change array may be increased to include the impact of the changes for shapes that more than one layer below or above the target shape.
- One main reason for limiting the size to three is to curtail the memory footprint of the variational map.
- the values assigned to each component of the change array are defined with reference to a global orientation system in the horizontal plane of the target shape.
- the East-West edge variations are defined.
- North-South edge variations are defined, whereas for an X-oriented edge (or slice), a Western edge motion is assigned the value of ⁇ 1. The absence of motion is assigned the value 0, and an Eastern edge motion is assigned the value of +1.
- a Southern edge motion is assigned the value of ⁇ 1, the absence of motion is assigned the value 0, and a Northern edge motion s assigned the value of +1.
- the third step in the variational mapping algorithm is to sort coordinates of the X-oriented edges and the Y-oriented edges 530 . It may occur that two or more edges have the same coordinate.
- the algorithm declares an edge duplication and removes the duplicates from the sorted list 540 .
- removal of duplicates can be refined to reduce the error in the capacitance gradient calculation that may result from removing the duplicate edge that has an edge change array different from the edge that is kept in the sorted list.
- FIG. 6 is a continuation of FIG. 5 whereby the X-edge sorted list and the Y-edge sorted list are used to form the areas of the target net.
- an area is bounded by two X-edges and two Y-edges.
- any pair of two successive X coordinates in the X list defines the X-edges and any pair of two successive Y coordinates in the Y list defines the Y-edges of an area 610 .
- the X-edges and Y-edges of the area define the NEWS neighborhood data structure of FIGS. 2 d and 4 .
- Each of these edges has its own edge change array.
- the impact of the edge change array on capacitance gradient calculation is accomplished using edge multipliers 620 .
- the edge multiplier is defined according to the following rules:
- the reason for selecting 0.5 as the absolute value of the multiplier when there is an edge change is based on the assumption that when the width of the shape is changed by an absolute value of +1, the edges of the shape move symmetrically with respect to the shape medial axis by a value of 0.5.
- This aspect of an embodiment of the invention will be explained further with reference to FIGS. 7 through 9 .
- Each area, thus formed and augmented with edge multiplier, is then processed in the calculation engine that computes capacitances and gradients 630 .
- the parameter abstraction used to control the number of parameters with respect to which capacitance variations are computed Assuming for illustrative purposes that the target net pertains to layer i, then rather than varying the widths of the shapes in layer i independently, it is assumed that they all vary in lockstep so that only one width parameter w(i) is assigned to layer i. Similarly, it is assumed that the layers immediately below (i ⁇ 1) and immediately above (i+1) the target net are each assigned one width parameter, w(i ⁇ 1) and w(i+1), respectively. Therefore, uniform width variations of the target layer, the layer immediately below and the layer immediately above represent abstractions of all the horizontal width variations that impact the capacitance of the target net.
- length variations are also abstracted as are the width variations, and thus, are included in the variational mapping.
- two conducing shapes on a given layer may have different thicknesses due to chemical and mechanical polishing, it assumed that all shapes on layer i have their thickness change in lockstep so that only one thickness parameter is assigned to layer i.
- Capacitances are also dependent not only on the shape separation within a given layer but also on the vertical separation between layers.
- the via layers below and above the target layer may have their heights depending locally on conditions of metallization or etching during the semiconductor fabrication. Yet, to keep the parameter set in a manageable size, it is assumed that local height variations are advantageously abstracted in two via height variations, one for the via height below and one for the via height above.
- target layer thickness, via height below and via height above the target layer are the only vertical parameters considered in the calculation of capacitance gradients.
- the number of parameters with respect to which capacitance gradients are computed is six parameters, three horizontal and three vertical. It should be apparent to a person skilled in the art that these parameters are preferably the ones that most influence the value of the target net capacitance.
- the horizontal parameters are all widths, a convention must be adopted as to how the width variation translates into an edge variation. For illustrative purposes, the convention that is adopted in one embodiment of the invention is that the width variation induces symmetric edge variations with respect to the medial axis of the shape. Other conventions are also possible, including ones in which edge variation is modulated by the proximity of other shapes thereto.
- FIG. 8 is an example showing how to assign edge change arrays and multipliers in the simple case where the target shape is crossed by two other shapes in the Y orientation. Consequently, only Y-oriented shapes are shown.
- the leftmost edge of the target wire becomes the Western edge of area 1 .
- Its edge change array is ( ⁇ 1,0) because wire length increase results in moving the edge in the negative direction with respect to the global X axis and because the crossing shapes have no impact whatsoever on the edge.
- Its multiplier array as the Western edge of the area 1 is calculated per the rules given above.
- the Y-oriented edges of area 2 are all due to the physical edges of the crossing shapes.
- FIG. 9 is yet another example of how to derive multiplier values using the multiplier rules described with reference to FIG. 5 . It is worth noting that the value of the multiplier is the result of the nature of the edge (N, S, E, W) as well as the values of the change array assigned to the edge.
- each area along with its NEWS neighborhood data structure is processed by the capacitance and gradient calculation engine. Details of such processing are described with reference to FIGS. 10 , 11 , and 12 .
- FIG. 10 is a flowchart of the various preliminary checks, verifications, and validations that are advantageously conducted on each area before initiating the capacitance and gradient calculation on the area geometric configuration.
- These preliminary operations include finding the top and bottom occupied levels in the area stack ( 10 . 2 ) and finding the X,Y orientation of each level in the area stack ( 10 . 3 ). Jogs and corners may lead to some shapes taking a direction different from the global orientation of the layer. Also, virtual edges may result in areas that are oriented differently than the global orientation of the layer in which they lie. Thus, a rotation operation ( 10 . 4 ) is sometimes required. Shapes in the area stack may belong to nets with special status. An example of such nets are those of the power grid.
- Net status should be passed to the shapes in the area stack ( 10 . 5 ). Furthermore, since in a VLSI chip layout, only horizontal distances are provided, the technology information should be accessed to obtain vertical distances. This is accomplished in ( 10 . 6 ). Regarding the horizontal distances, a “minimum space violations” check ( 10 . 7 ) is conducted, whereby the spacing between any two shapes on the same layer for the area and its neighbors is checked to ascertain that it is above the minimum spacing required. Minimum spacing requirements are provided in the technology file.
- One preferred embodiment provides automatic fixes to the spacing violations so as not interrupt the capacitance and gradient calculation. In another embodiment, violations are reported back to the user who may provide these fixes manually by changing the VLSI chip layout. The capacitance and gradient calculation ( 10 .
- FIG. 11 is a flowchart of the steps executed in the upward capacitance and gradient calculation pass
- FIG. 12 is a flowchart of the steps executed in the downward calculation pass. The sequence and nature of steps are similar in the two passes, and therefore only detailed description of FIG. 11 is provided.
- the capacitance and gradient calculation in the upward pass consists in checking whether the current level under consideration has indeed a physical shape to be processed ( 11 . 2 ). As evident from the descriptions of FIGS. 3 a through 3 e , a shape above a given target shape may or may not be present depending on the local configuration context. When a shape is present, the capacitance lookup table is accessed ( 11 . 3 ) to extract the capacitance and gradient information of that shape. The specific situation under which such information is available can be found with reference to the description of FIG. 13 . Next, a test on the area data structure is performed to ascertain the presence of a shape anywhere in a level above a current level.
- an operation referred to “horizontal splitting” is applied.
- the operation consists in using a correction factor to adjust the capacitance and gradient values obtained from the capacitance lookup table.
- the specific situation under which such operation is performed is detailed in FIG. 14 .
- the capacitance and gradient values resulting from ( 11 . 3 ) are totaled ( 11 . 6 ) and saved for further processing ( 11 . 10 ).
- an additional check for the presence of a center shape in the upper level is performed ( 11 . 9 ). If such a center shape is present, then capacitance and gradient values are assigned ( 11 . 11 ) to the target net in question.
- the above upward pass is concerned with computing capacitance and gradients when looking up the layers above those of a target net.
- a similar downward pass is used to compute capacitance and gradients as one looks down to the layers below those of the target net (see FIG. 12 ).
- FIG. 12 A detailed description of the flowchart shown in FIG. 12 can be readily inferred from FIG. 13 .
- a shape pattern referred to a nested (or centered) wiring pattern is shown along with the header and a typical entry for the capacitance and gradient lookup table.
- the gradients included in the lookup table are computed with respect to the variables specified in the parameter abstraction of FIG. 8 .
- the width of the centered wire corresponds to that of the minimum design rule width. Accordingly, the capacitance gradient with respect to width is computed at that minimum width.
- the gradients with respect to the width of the wire above the target net and the width of the wire below the target net are not included in the capacitance table. They will be inferred from the upward and downward passes, as explained in FIGS. 14 and 15 .
- Keys to the rows of the lookup table are made of the indices of the lower layer, the target net layer, and the upper layer. Another component of the key is the distance separating the target wire and its nearest neighbor.
- the capacitance columns in the lookup table contain different capacitance components, such as lateral capacitance, and upward and downward capacitance.
- the gradient columns contain the gradients of each of these capacitance components with respect to the abstracted parameters.
- One distinct advantage of the present invention is the reduction in the size of the lookup table because of the use of abstracted parameters rather than the original variables.
- the use of lateral, upward, and downward capacitance is for meant only for illustration as other types of capacitance can be used. Such other types include fringing capacitance, parallel-plate capacitance, and total capacitance.
- the most useful capacitance types are the total net capacitance and the net-to-net coupling capacitance. (Note: a net is a set of electrically connected shapes in the chip layout).
- the net-to-net coupling capacitance results from the electrostatic interaction between the shapes of a given net and the shapes of another net that is not in electrical contact with the first net.
- the total capacitance of a target net consists of the sum of all the net-to-net coupling capacitances between the target net and all the other nets that are in its proximity.
- FIG. 14 is an illustration of the “horizontal splitting” algorithm used to address the case when the area configuration pattern deviates from that of the capacitance lookup table. More specifically, FIG. 14 shows an instance under which the “horizontal splitting” operation in FIGS. 11 and 12 is used. The present case occurs when it is assumed a solid plate of the centered shape pattern of FIG. 13 . Correction factors have to be applied to the capacitances accessed from the capacitance table in order to accommodate the fact that shapes below or above the shapes of the target net are not solid plates but rather disconnected shapes.
- U.S. Pat. No. 5,838,582 to Mehrorta et al. describes how to apply correction factors in the case of nominal capacitance calculation.
- correction factors are preferably also applied to the gradients of the capacitances. These corrections factors are explicitly given in the detailed explanation of FIG. 16 .
- the table lookup gradients of upper layer of FIG. 14 are used to modify the table lookup gradients of the target layer. The modification is operated through the gradients of the correction factors used in the nominal capacitance calculation.
- An advantage of the present invention is that the vertical abstracted parameters are employed to compute the gradients of both the target and upper layers. When a gradient with respect to the horizontal abstracted parameters is sought, two possibilities can be contemplated. One possibility is to use the same width in both the upper layer and target layer. This is illustrated with the two dashed lines showing the symmetric, equal width perturbation of both layers. Another possibility is to let the upper width change independently of target width.
- FIG. 15 shows the case under which the “vertical splitting” operation in FIGS. 11 and 12 is used, and occurs when the center region above or below a target shape has no shape.
- a “ghost” shape is created and its capacitances values are obtained from the lookup table. These capacitances are then used as a basis of adjusting the capacitances of the target shape. The adjustment consists in applying correction factors to the capacitances of the target shape.
- U.S. Pat. No. 5,838,582 previously mentioned, describes how to compute the correction factors based on ghost shapes for the case of nominal capacitance computation. In an embodiment of the present invention, correction factors are also applied to the gradients of the capacitances. These corrections factors are explicitly given in the detailed explanation of FIG. 16 .
- the table lookup gradients of ghost shape of FIG. 15 are preferably employed to modify the table lookup gradients of the target layer.
- the modification is operated through the gradients of the correction factors of used in the nominal capacitance calculation.
- An advantage of the present invention is that the vertical abstracted parameters can be used to compute the gradients of both the target and ghost shapes.
- a gradient with respect to the horizontal abstracted parameters is sought, two possibilities can be contemplated.
- One possibility is to use the same width in both the ghost shape and target shape. This is illustrated by way of the two dashed lines showing the symmetric, equal width perturbation for both layers.
- Another possibility is to let the upper width change independently of the target width.
- the sequence of steps to compute the gradients of a given target net are shown in FIG. 16 .
- a target net is first selected ( 16 . 2 ).
- the variational parameters for that net are defined ( 16 . 3 ), i.e., the parameters with respect to which net capacitance gradients are computed.
- these parameters are the horizontal width parameters ( W ) and the vertical thickness parameters ( T ).
- the area capacitance ( 16 . 4 ) is computed according to the upward ( FIG. 11 ) and downward pass ( FIG. 12 ).
- C area is the capacitance of the area under consideration.
- the capacitance is derived from two sources: the capacitance lookup table C Table ( W , T ) and the correction factor f( W , T ) that result from the area configuration deviating from the elementary pattern of the capacitance table.
- the gradient calculation with respect to the parameters is performed according to ( 16 . 5 ) using the following equation
- d C area d P is the gradients of the area capacitance.
- the first term on the right-hand-side in the above equation provides the gradients of the capacitance as obtained from the capacitance lookup table corrected by the same factors used to correct the nominal capacitance.
- the second term provides the contribution of the correction factor gradients to the capacitance gradients. Note that the correction factors and analytical or semi-analytical expressions whose gradients can be computed explicitly according to the well-know rules of differentiation.
- the target net is made of a set of areas to which the contributions of all capacitances and gradients of the target net areas are added to obtain the net capacitance and gradients. The calculation terminates as soon as the last net is processed.
- One aspect of the invention relates the multipliers assigned to the area virtual edges by the shape processing engine ( FIGS. 8 and 9 ) to the capacitance gradients computed in the flowchart of FIG. 16 .
- the mathematical relationship is given by
- one or more steps of the methods described herein may include a storing, displaying and/or outputting step as required for a particular application. Any data, records, fields, and/or intermediate results previously described can be stored, displayed, and/or outputted to another device, as required for a particular application. Furthermore, steps or blocks in the accompanying figures that recite a determining operation or involve a decision, do not necessarily require that both branches of the determining operation be practiced. Alternatively, one of the branches of the determining operation can be deemed as an optional step.
- the present invention can be realized in hardware, software, or a combination of hardware and software.
- the present invention can be realized in a centralized fashion in one computer system or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system—or other apparatus adapted for carrying out the methods described herein—is suitable.
- a typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
- the present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which—when loaded in a computer system—is able to carry out the methods.
- Computer program means or computer program in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after conversion to another language, code or notation and/or reproduction in a different material form.
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- General Engineering & Computer Science (AREA)
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Abstract
Description
-
- 1) It deals with an extraction flow in which the capacitance calculation engine relies solely on analytical expressions for capacitances. It does not address the more common case when the capacitance information is provided using lookup tables, and
- 2) It uses a shape processing engine in which the nature of the VLSI layout decomposition is dependent on the type of capacitance one is interested in computing. In other words, the elementary patterns considered change according to whether the capacitance of a targeted primary shape is lateral, fringe, or parallel plate.
-
- West and South edges that are assigned an edge change value of −1 (reps. +1) are assigned a multiplier of +0.5 (resp. −0.5).
- East and North edges that are assigned an edge change value of −1 (resp. +1) are assigned a multiplier of −0.5 (resp. +0.5).
- An edge change value of 0 always results in a multiplier of 0.
C area =C Table(
is the gradients of the area capacitance. The first term on the right-hand-side in the above equation provides the gradients of the capacitance as obtained from the capacitance lookup table corrected by the same factors used to correct the nominal capacitance. The second term provides the contribution of the correction factor gradients to the capacitance gradients. Note that the correction factors and analytical or semi-analytical expressions whose gradients can be computed explicitly according to the well-know rules of differentiation. Moreover, the target net is made of a set of areas to which the contributions of all capacitances and gradients of the target net areas are added to obtain the net capacitance and gradients. The calculation terminates as soon as the last net is processed.
are calculated using equation (2). The partial derivatives
are, respectively, those of the table lookup capacitance and the correction factor with respect to an edge location v. The symbol
Claims (19)
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US20120317530A1 (en) * | 2011-06-13 | 2012-12-13 | International Business Machines Corporation | Solutions for on-chip modeling of open termination of fringe capacitance |
US11176308B1 (en) * | 2020-06-19 | 2021-11-16 | International Business Machines Corporation | Extracting parasitic capacitance from circuit designs |
US11314916B2 (en) | 2020-07-31 | 2022-04-26 | International Business Machines Corporation | Capacitance extraction |
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US8365117B2 (en) * | 2011-06-13 | 2013-01-29 | International Business Machines Corporation | Solutions for on-chip modeling of open termination of fringe capacitance |
US11176308B1 (en) * | 2020-06-19 | 2021-11-16 | International Business Machines Corporation | Extracting parasitic capacitance from circuit designs |
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