WO2023130434A1

WO2023130434A1 - Layout design method and apparatus, device, medium and program product

Info

Publication number: WO2023130434A1
Application number: PCT/CN2022/070963
Authority: WO
Inventors: 伍宏忠; 李逸峰; 沈嘉华; 张锐; 黄宇
Original assignee: 华为技术有限公司
Priority date: 2022-01-10
Filing date: 2022-01-10
Publication date: 2023-07-13
Also published as: CN118159976A

Abstract

The present disclosure relates to a method for designing a layout, a program product, a storage medium and an electronic device. The method comprises: applying a local average field to a line length gradient of each circuit unit in an initialized layout and/or a density of circuit units within a grid in a grid array; and obtaining a corresponding synthesized item. The synthesized item is then used to iteratively optimize. In this way, multiple associated circuit units may be uniformly distributed in a layout process, and the tightness of a connection relationship may also be kept through the distribution process. In other words, layout parameters of the circuit units, such as line length and layout tightness, each have their own influences, and also have an overall local influence, in the layout iteration process. In this way, compared with conventional analytical overall layout, the final layout results obtained in accordance with a first aspect of the present disclosure may cause the layout quality to be improved, for example, reducing final wire length characterized by HPWL.

Description

Method, device, apparatus, medium and program product for designing layout

technical field

Embodiments of the present disclosure generally relate to the field of chip design, and more specifically relate to methods, devices, devices, media and program products for designing layouts.

Background technique

In integrated circuit (Integrated Circuit, IC) design, physical design is the process of converting gate-level netlist into geometric layout. Physical design mainly includes steps such as division, layout planning, layout, clock tree synthesis, and wiring, among which layout is an important step in the early stage of physical design. Layout is mainly used to determine the placement of circuit units in the chip, and can be further subdivided into Global Placement (GP), Legalization (LG) and Detailed Placement (DP).

In LSI design, physical design is one of the important steps. In the physical design, the location of the standard unit is an important link. The placement of standard units includes global placement (GP) and detailed layout. The main purpose of global placement is to place standard units on the design area according to a certain optimization goal, but at the same time, a certain degree of standardization is allowed. The location of the unit overlaps, and the optimization goal here can be expressed by indicators such as wire length (WL), routing congestion (congestion) or delay, or a combination of them. A common indicator used to represent wire length is the half parameter wire length (HPWL). The detailed layout is based on the overall layout to eliminate the overlap between layout units and improve the delay. In the design of modern large-scale integrated circuits, the quality of the overall layout has an important impact on the performance, power consumption and area (performance-power-area, PPA) of the final chip, and the overall layout time is also the main factor in the entire physical design. One of the time consuming parts.

Conventional global layout optimization methods mainly fall into three categories: global layout methods based on heuristic partitioning, layout methods based on simulated annealing methods, and analytical iterative optimization layout methods. An analytical overall layout optimization method combines the optimized objective function and related constraints through Lagrangian relaxation technique to obtain a new optimized objective function. By expressing the optimization objective function into a differentiable analytical form, the optimization theory in mathematics can be fully used to solve the optimal layout. However, since the "overlap degree of standard unit" item in the analytical optimization objective function is a non-convex function in many models, the gradient descent method often falls into a local optimal solution. In addition, since no local constraints are added to the layout units on each connection network, the layout units on the same continuous network may be scattered in the final layout result, which will increase the final line length such as HPWL , the layout quality is poor.

Contents of the invention

In view of the above-mentioned problems, embodiments of the present disclosure aim to provide a method, apparatus and electronic device for designing a layout for improving the quality of the overall layout.

In a first aspect of the present disclosure, a method for designing a layout is provided. The method includes: based on the netlist data of the chip, initializing a plurality of circuit units in the chip in a grid array in the layout area to obtain an initial layout of the plurality of circuit units in the grid array, the netlist data at least indicating The size of multiple circuit cells and the connection relationship of multiple circuit cells; based on the initial layout and netlist data, determine the synthetic items of the layout parameters of the initial layout, and the synthetic items are based on the initial items of the layout parameters and the layout parameters associated with the layout parameters locally averaged terms of the set; and determining a target layout of the plurality of circuit cells in the grid array based on the synthesized term and the initialized layout. In the layout process, not only the gradient of the layout parameter itself is considered, but also the local average gradient associated with the layout parameter is considered, so that the layout optimization of the circuit unit can be performed with the synthetic gradient. In this way, a plurality of associated circuit units can be evenly spread out during the layout process, and can also maintain a tight connection relationship during the spread out process. In other words, layout parameters such as line length and layout compactness of circuit cells have both their own unique gradient influences and local overall gradient influences during the layout iteration process. In this way, compared with the conventional analytical overall layout, the final layout result obtained according to the first aspect of the present disclosure can lead to improved layout quality, for example, reduced final line length such as HPWL characterization.

In an implementation manner of the first aspect, the layout parameters include the gradient of the connection line length of the first circuit unit among the plurality of circuit units, the synthesis item includes the synthesis gradient of the connection line length, and the gradient indicates the maximum rate of change of the layout parameter and The direction with the maximum rate of change, based on the initial layout and the netlist data to determine the synthetic item of the layout parameters of the initial layout includes: based on the netlist data and the initial layout, calculating the first initial gradient of the connection line length of the first circuit unit; Table data, determining a first associated circuit unit set of the first circuit unit; calculating a first local average gradient based on the first initial gradient and the initial gradient of the connecting line length of each associated circuit unit in the first associated circuit unit set; and Based on the first initial gradient and the first local average gradient, a resultant gradient of the connecting line length of the first circuit unit is calculated.

In an implementation manner of the first aspect, determining the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data includes: for each circuit unit in the plurality of circuit units, calculating each Respective initial gradients for the circuit cells, determining a respective set of associated circuit cells for each circuit cell, computing a respective local average gradient for each circuit cell, and computing a respective resultant gradient for the connecting line lengths for each circuit cell. By calculating the composite gradient of the circuit unit, both the unique gradient influence of the circuit unit and the local overall gradient influence can be maintained during the layout process. In this way, it is possible to avoid an increase in line length caused by over-dispersion of associated circuit units in the spreading process of the circuit units. In other words, in this way, the overall layout line length of the circuit units in the overall layout process can be reduced.

In an implementation manner of the first aspect, determining the first associated circuit unit set of the first circuit unit based on the netlist data includes: determining the first associated circuit unit of the first circuit unit based on the netlist data and the first associated parameter set, the first associated parameter is used to specify the level of the physical connection of the first circuit unit. For example, the first association parameter is used to specify that the level of the physical connection of the first circuit unit is level 1 indicating direct connection. In other words, only the local average gradients of the first circuit unit and related circuit units directly connected to the first circuit unit are considered when calculating the synthetic gradient of the line length above. In this way, the calculation amount and the subsequent iteration time can be reduced, and the overall layout line length of the circuit cells in the overall layout process can still be significantly reduced.

In an implementation manner of the first aspect, the layout parameter includes the degree of density of the first grid in the grid array, the degree of density of the first grid represents the degree of density of the circuit units in the first grid, and the synthesis item includes The synthesis density of the circuit cells in the first grid, based on the initialization layout and the netlist data, determining the synthesis item of the layout parameters of the initialization layout includes: based on the initialization layout and the netlist data, calculating the first initial density of the first grid. degree; based on the initial layout, determine the associated grid set of the first grid; based on the first initial dense degree and the corresponding initial dense degree of each associated grid in the associated grid set, calculate the first local average dense degree; based on the second An initial denseness and a first local average denseness, calculating a combined denseness of the first grid; and determining a first combined denseness of circuit units in the first grid based on the combined denseness of the first grid.

In an implementation manner of the first aspect, determining the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data includes: for each grid in the grid array, in a manner similar to the above, calculating The corresponding initial denseness of each grid, determine the respective associated grid set of each grid, calculate the corresponding local average denseness of each grid, and calculate the corresponding composite denseness of each grid, and based on each grid The composite density of the grid determines the density of circuit cells within the grid. Through the composition density of each grid, it is possible to maintain both the unique influence of individual grids and the overall influence of local grids during the layout process. For example, a plurality of circuit units can be prevented from gathering in another grid again during the spreading process. In this way, the spreading process of the circuit units can be made more uniform, so as to obtain a better layout effect.

In an implementation manner of the first aspect, determining the first set of associated circuit units of the first circuit unit based on the initialization layout includes: determining the set of associated grids of the first grid based on the initialization layout and the second association parameter, and the second The association parameter is used to specify the grid level adjacent to the first grid. For example, the second association parameter is used to designate the adjacent grid level of the first grid as level 1 representing direct adjacency. In other words, when calculating the composite gradient of the cell density of the grid above, only the local average gradient of the cell density of the first grid and related grids directly adjacent to the first grid is considered. In this way, the amount of computation and subsequent iteration time can be reduced and still achieve significant layout effects.

In an implementation of the first aspect, determining the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data includes: determining the initial gradient and the local average gradient of the layout parameters based on the initialization layout and the netlist data; calculating the initial a first product of the gradient and the first coefficient; calculating a second product of the local average gradient and the second coefficient; and adding the first product to the second product to determine a resultant gradient of the layout parameter. In an implementation manner of the first aspect, the sum of the first coefficient and the second coefficient is 1. By setting different coefficients, relevant parameters in the layout process can be adjusted based on the configuration of the circuit, thereby affecting the layout quality and/or the speed and required time of layout iterations. For example, in the case where the layout parameter is the cell density of the grid, if the density is greater, the coefficient can be set to make the circuit cells spread out faster, thereby speeding up subsequent iterations and reducing the number of steps required for final convergence .

In an implementation manner of the first aspect, the method further includes: determining an initial value of the layout parameter; and setting the second coefficient to a negative value in response to the initial value being higher than the first threshold. For example, the layout parameter may be the density of cells in the grid of the grid array, and the initial value may be the initial value of the density of cells in a grid. By confirming the initial value of the layout parameter before the iteration and comparing the initial value with the threshold value, the circuit cells in the denser grid can be dispersed faster, thereby saving the calculation amount and time of the layout iteration.

According to a second aspect of the present disclosure, an apparatus for designing a layout is provided. The device includes: an initialization module, a composite item determination module and a target layout determination module. The initialization module is configured to: based on the netlist data of the chip, initialize the multiple circuit units in the chip in the grid array in the layout area, so as to obtain the initialization layout of the multiple circuit units in the grid array, and the netlist data At least the dimensions of the plurality of circuit units and the connection relationship of the plurality of circuit units are indicated. The synthesis item determining module is configured to: determine the synthetic gradient of the layout parameters of the initial layout based on the initial layout and the netlist data, the synthetic gradient is based on the initial gradient of the layout parameters and the local average gradient of the layout parameter set associated with the layout parameters, the gradient Indicates the maximum rate of change of the layout parameter and the direction with the maximum rate of change. The target layout determining module is configured to: determine the target layout of the plurality of circuit cells in the grid array based on the synthetic gradient and the initial layout. In the layout process, not only the gradient of the layout parameter itself is considered, but also the local average gradient associated with the layout parameter is considered, so that the layout optimization of the circuit unit can be performed with the synthetic gradient. In this way, a plurality of associated circuit units can be evenly spread out during the layout process, and can also maintain a tight connection relationship during the spread out process. In other words, layout parameters such as line length and layout compactness of circuit cells have both their own unique gradient influences and local overall gradient influences during the layout iteration process. In this way, compared with the conventional analytical overall layout, the final layout result obtained according to the first aspect of the present disclosure can lead to improved layout quality, for example, reduced final line length such as HPWL characterization.

In an implementation manner of the second aspect, the layout parameter includes a connection line length of a first circuit unit among the plurality of circuit units. The synthesis item determination module includes: a calculation module configured to calculate the first initial gradient of the connection line length of the first circuit unit based on the netlist data and the initialization layout; the associated circuit unit set determination module is configured to: based on the netlist data, determining the first associated circuit unit set of the first circuit unit; the calculation module is further configured to: calculate the first partial an average gradient; and based on the first initial gradient and the first local average gradient, calculating a resultant gradient of the connecting line length of the first circuit unit.

In an implementation manner of the second aspect, determining the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data includes: for each circuit unit in the plurality of circuit units, calculating each Respective initial gradients for the circuit cells, determining a respective set of associated circuit cells for each circuit cell, computing a respective local average gradient for each circuit cell, and computing a respective resultant gradient for the connecting line lengths for each circuit cell. By calculating the composite gradient of the circuit unit, both the unique gradient influence of the circuit unit and the local overall gradient influence can be maintained during the layout process. In this way, it is possible to avoid an increase in line length caused by over-dispersion of associated circuit units in the spreading process of the circuit units. In other words, in this way, the overall layout line length of the circuit units in the overall layout process can be reduced.

In an implementation manner of the second aspect, the associated circuit unit set determining module is further configured to: determine the first associated circuit unit set of the first circuit unit based on the netlist data and the first associated parameter, and the first associated parameter is used at the level specifying the physical connection of the first circuit unit. For example, the first association parameter is used to specify that the level of the physical connection of the first circuit unit is level 1 indicating direct connection. In other words, only the local average gradients of the first circuit unit and related circuit units directly connected to the first circuit unit are considered when calculating the synthetic gradient of the line length above. In this way, the calculation amount and the subsequent iteration time can be reduced, and the overall layout line length of the circuit cells in the overall layout process can still be significantly reduced.

In an implementation manner of the second aspect, the layout parameter includes the density of the first grid in the grid array, the density of the first grid represents the density of the circuit units in the first grid, and the synthesis item includes For the synthesis density of the circuit cells in the first grid, the synthesis item determination module is further configured to: calculate the first initial density of the first grid based on the initial layout and netlist data; determine the first initial density based on the initial layout. an associated grid set of meshes; based on the first initial density and the corresponding initial density of each associated mesh in the associated grid set, a first local average density is calculated; based on the first initial density and the first local average The degree of density is to calculate the density of synthesis of the first grid; and based on the density of synthesis of the first grid, determine the first degree of density of synthesis of the circuit units in the first grid.

In an implementation manner of the second aspect, the composite item determination module is further configured to: for each grid in the grid array, in a manner similar to the above, calculate the corresponding initial density of each grid, and determine each the respective associated grid sets of grids, calculate the corresponding local average density of each grid, and calculate the corresponding composite density of each grid, and determine the circuit within the grid based on the composite density of grids density of units. By synthesizing the denseness of the cell compactness of each grid, it is possible to maintain both the unique influence of individual grids and the overall influence of local grids during the layout process. For example, a plurality of circuit units can be prevented from gathering in another grid again during the spreading process. In this way, the spreading process of the circuit units can be made more uniform, so as to obtain a better layout effect.

In an implementation manner of the second aspect, the associated grid set determination module is further configured to: determine the associated grid set of the first grid based on the initialized layout and the second associated parameter, and the second associated parameter is used to specify the The grid level adjacent to the first grid. For example, the second association parameter is used to designate the adjacent grid level of the first grid as level 1 representing direct adjacency. In other words, when calculating the composite gradient of the cell density of the grid above, only the local average gradient of the cell density of the first grid and related grids directly adjacent to the first grid is considered. In this way, the amount of computation and subsequent iteration time can be reduced and still achieve significant layout effects.

In an implementation of the second aspect, the synthetic term determination module is further configured to: determine the initial term and the local average term of the layout parameters based on the initialization layout and the netlist data; calculate the first product of the initial term and the first coefficient ; calculating a second product of the local mean term and the second coefficient; and adding the first product to the second product to determine a resultant term of the layout parameter. In an implementation manner of the second aspect, the sum of the first coefficient and the second coefficient is 1. By setting different coefficients, relevant parameters in the layout process can be adjusted based on the configuration of the circuit, thereby affecting the layout quality and/or the speed and required time of layout iterations. For example, in the case where the layout parameter is the cell density of the grid, if the density is greater, the coefficient can be set to make the circuit cells spread out faster, thereby speeding up subsequent iterations and reducing the number of steps required for final convergence .

In an implementation manner of the second aspect, the device further includes an initial value determination module configured to determine an initial value of the layout parameter; and a setting module configured to set the second Coefficients are set to negative values. For example, the layout parameter may be the density of cells in the grid of the grid array, and the initial value may be the initial value of the density of cells in a grid. By confirming the initial value of the layout parameter before the iteration and comparing the initial value with the threshold value, the circuit cells in the denser grid can be dispersed faster, thereby saving the calculation amount and time of the layout iteration.

According to a third aspect of the present disclosure, there is provided an electronic device, comprising: at least one processor; at least one memory, the at least one memory is coupled to the at least one processor and stores instructions for execution by the at least one processor, the instructions When executed by at least one processor, an apparatus is caused to perform the method according to the first aspect.

According to a fourth aspect of the present disclosure, a computer readable storage medium is provided. A computer-readable storage medium stores a computer program which, when executed by a processor, implements the method according to the first aspect.

According to a fifth aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions which, when executed by a processor, cause a computer to implement the method according to the first aspect.

It should be understood that what is described in the Summary of the Invention is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, identical or similar reference numerals denote identical or similar elements, wherein:

Figure 1 shows a flow chart of the design and manufacture process of an integrated circuit;

Figure 2 shows a block diagram of an example environment according to some embodiments of the present disclosure;

Figure 3 shows a schematic diagram of an exemplary initial layout;

FIG. 4 shows a flowchart of a method for designing a layout according to some embodiments of the present disclosure;

Fig. 5 shows a schematic diagram of dividing layout areas according to some embodiments of the present disclosure;

Fig. 6 shows a schematic diagram of the connection relationship of circuit units according to some embodiments of the present disclosure;

FIG. 7 shows a schematic diagram of a synthetic gradient of a circuit unit according to some embodiments of the present disclosure;

Figure 8 shows a schematic diagram of a composite gradient of circuit cell density in a grid according to some embodiments of the present disclosure;

FIG. 9 shows a schematic block diagram of an electronic device 900 according to some embodiments of the present disclosure; and

Fig. 10 shows a schematic block diagram of an example device 1000 that may be used to implement embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

It should be understood that for the technical solutions provided by the embodiments of the present application, in the introduction of the following specific embodiments, some repetitions may not be repeated, but it should be considered that these specific embodiments have been referred to each other and can be combined with each other.

With the development of integrated circuit manufacturing technology and the reduction of feature size, the complexity of physical design has also increased exponentially. As mentioned above, legalization is a step in the layout stage, and its layout quality has a significant impact on the PPA of the final chip. Conventional layout legalization schemes usually have three types of overall layout optimization methods: overall layout methods based on heuristic partitioning, layout methods based on simulated annealing methods, and analytical iterative optimization layout methods.

However, these three conventional schemes each have corresponding problems. For example, for the overall layout method of heuristic partition, it is greatly affected by the change of the initial input, and the slight change of the initial input may lead to a very different final layout position. At the same time, because the layout optimization of each sub-region is a local process , which may cause routing congestion in other areas to increase while the layout of a certain sub-area is optimized. For the layout method based on the simulated annealing method, the simulated annealing algorithm can effectively accelerate the layout speed of the integrated circuit to a certain extent, but the two problems that this method cannot solve are: firstly, the running time of the algorithm is still relatively long , although the size of the solution space is optimized in this improved algorithm, the randomness of simulated annealing fundamentally restricts the running time gain; secondly, the high temperature and low temperature parameters proposed by the algorithm are different in each specific IC layout situation , which leads to the need to spend a lot of time on the optimization of hyperparameters when using this method, and the increase in workload and the limited benefit of runtime. For the analytical iterative optimization layout method, by expressing the optimization objective function into a differentiable analytical form, people can make full use of the optimization theory in mathematics to solve the optimal layout. However, since the "overlapping degree of standard unit" item in the analytical optimization objective function is a non-convex function in many models, the solution of the gradient descent method often falls into a local optimal solution; The unit adds local constraints, and the layout units on the same connection network may have a large degree of dispersion in the final layout result, which will increase the final line length and poor layout quality.

In an embodiment of the present disclosure, a solution for designing a layout is proposed to solve one or more of the above-mentioned problems and other potential problems. In this disclosure, by introducing a local mean field at the netlist level and/or the layout grid level, the layout units can be fully dispersed during the overall layout, and the connection relationship of the layout units on each wiring network can be improved to a certain extent. Tightness is maintained. That is, layout cells with strong connection relationships are sufficiently close in the final layout result. So as to achieve the goal of line length optimization.

FIG. 1 shows a flowchart of a design and manufacture process 100 for an integrated circuit. The design-to-manufacture process 100 begins with specification development 110 . In the stage of specification formulation 110, the functional and performance requirements that the integrated circuit needs to meet are determined. Then, in the stage of integrated circuit design 120, circuit design 122 is first performed by means of electronic design automation (EDA) software. After the circuit is determined, the physical design 124 is performed to determine the layout and wiring of the circuit units in the integrated circuit, so as to obtain the circuit layout. After obtaining the circuit layout, mask fabrication 126 may be performed to obtain masks for forming the designed circuits on the wafer. Subsequently, in the stage of manufacturing 130, integrated circuits are formed on the wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. In the stage of packaging 140 , the wafer is diced to obtain bare chips, and the bare chips are packaged through processes such as bonding, welding, and molding to obtain chips. The resulting chip is tested in a testing 150 stage to ensure that the performance of the finished chip meets the requirements established in specification 110 . Finally, the tested chips 160 can be delivered to customers.

The physical design 124 mainly includes steps such as division, layout planning, layout, clock tree synthesis, and wiring, and involves evaluation indicators such as routability, delay, power consumption, area, and manufacturability. Layout is an important part of physical design and includes overall layout, legalization, and detailed layout. The main purpose of the overall layout is to place the circuit units in the layout area according to a certain optimization goal, and a certain degree of overlap of the circuit units is allowed in the overall layout. After the overall layout, it is necessary to legalize the circuit units to be placed in legal positions, and to eliminate the overlap between the circuit units. Meticulous layout is to further reduce line length, improve delay, and reduce congestion on the basis of legalization results. Legalization is an intermediate link in the layout process, and its layout quality has a major impact on the final evaluation indicators. Therefore, it is expected to ensure legalized layout quality, thereby shortening the physical design cycle and improving chip development efficiency.

FIG. 2 shows a block diagram of an example environment 200 according to some embodiments of the present disclosure. As shown in FIG. 2 , example environment 200 may generally include electronic device 230 . In some embodiments, the electronic device 230 may be a device having computing functions such as a personal computer, a workstation, a server, and the like. The scope of the present disclosure is not limited in this regard. The electronic device 230 may take as input the netlist data 210 for the chip and the initial layout 220 for the chip. The chip can comprise, for example, a plurality of circuit units. In some embodiments, the plurality of circuit units includes at least one group of movable circuit units. In some embodiments, the plurality of circuit units may also include a set of fixed circuit units.

It should be noted that in the context of the present disclosure, a "movable circuit unit" means a circuit unit whose position can be changed in a layout scheme according to various embodiments of the present disclosure. In some embodiments, the removable circuit unit may be a standard unit such as a gate, for example. It should be understood that the movable circuit unit may also be any other suitable unit whose position is set to be changeable, and the scope of the present disclosure is not limited in this respect.

It should also be noted that in the context of the present disclosure, a "fixed circuit unit" refers to a circuit unit whose position has been predetermined and cannot be changed in the layout scheme according to the various embodiments of the present disclosure. In some embodiments, the fixed circuit cells may be macrocells, for example. "Macro unit" refers to a pre-defined logic function realization unit composed of flip-flops and arithmetic logic units with a higher abstraction level than logic gates. It should be understood that the fixed circuit unit may also be any other suitable unit whose position is set to be unchangeable, and the scope of the present disclosure is not limited in this regard. In this disclosure, since layout optimization is optimized for movable circuit units, if it is not explicitly stated as a "fixed circuit unit" or a non-movable circuit unit, "circuit unit" is usually used to refer to a "movable circuit unit". ” for ease of description.

In some embodiments, the netlist data 210 may at least indicate the size of the multiple circuit units in the chip and the connection relationship of the multiple circuit units. In some embodiments, the netlist data 210 may also indicate information such as chip layout area and process parameters, and the scope of the present disclosure is not limited in this respect.

In some embodiments, the initial layout 220 may indicate the positions of multiple circuit units of the chip in the layout area, for example, the coordinates of each circuit unit. In some embodiments, the initial layout 220 may be a layout obtained through an overall layout, in which a certain degree of overlap exists among some circuit units. It should be understood that the initial layout 220 may also be any other suitable layout to be optimized, and the scope of the present disclosure is not limited in this respect.

In some embodiments, netlist data 210 and initial layout 220 may be entered into electronic device 230 by a user. In some embodiments, the netlist data 210 and the initial layout 220 may have been pre-stored in the electronic device 230 . In some embodiments, electronic device 230 may also be communicatively coupled to other devices to obtain netlist data 210 and initial layout 220 from other devices. The scope of the present disclosure is not limited in this respect. It should be noted that although netlist data 210 and initial layout 220 are shown as two separate files in FIG. Unrestricted in this respect.

The electronic device 230 may divide the layout area of the chip into grid arrays based on the netlist data 210, and then determine the priorities of multiple candidate paths for moving the movable circuit units therein for the overloaded grids in the grid array of the layout area. level, and determine the final target layout 240 according to the determined priority and the initial layout 220 . This will be described in further detail below with reference to FIGS. 3 to 10 .

FIG. 3 shows a schematic diagram of an exemplary initial layout 220 . For the purposes of illustration and simplification, in the example shown in FIG. is a movable circuit unit 320) and four fixed circuit units 330-1 to 330-4 (separately or collectively referred to as fixed circuit unit 330). As shown in FIG. 3 , in the initial layout 220 , some circuit units overlap to a certain extent. For example, movable circuit unit 320-5 overlaps with movable circuit units 320-2, 320-3, 320-5, and 320-6. For another example, the fixed circuit unit 330-3 overlaps with the movable circuit unit 320-11.

It should be understood that the layout area 310 of the chip can also have any other suitable shape, and the number of the movable circuit unit 320 and the fixed circuit unit 330 included in the chip can also be any other suitable value, and the scope of the present disclosure is within This aspect is not limited.

Hereinafter, solutions according to various embodiments of the present disclosure will be described with reference to the initial layout 220 shown in FIG. 3 . It should be understood that the solutions according to the various embodiments of the present disclosure may also be applied to any other suitable layout, and the scope of the present disclosure is not limited in this respect.

FIG. 4 shows a flowchart of a method 400 for designing a layout according to some embodiments of the present disclosure. In some embodiments, the method 400 may be executed by the electronic device 230 as shown in FIG. 2 . It should be appreciated that method 400 may also include additional blocks not shown and/or blocks shown may be omitted, and that the scope of the present disclosure is not limited in this regard.

At 402, based on the netlist data of the chip, initialize the plurality of circuit units in the chip in the grid array of the layout area, so as to obtain the initialization layout of the plurality of circuit units in the grid array, for example as shown in FIG. 3 The initial layout. The netlist data indicates at least the size of the plurality of circuit units and the connection relationship of the plurality of circuit units. In one embodiment, the electronic device 230 may, for example, preprocess input files such as netlist files and design related information. For example, the length and width information of standard cells and macro cells are obtained from the netlist information, and the largest rectangular area is divided on the area to be placed, and the target layout density is calculated. The electronic device can then be initialized in the layout area using initialization methods such as random initialization and quadratic initialization. Further, the electronic device 230 may divide the layout area, for example, divide it into a grid array including a plurality of grids. Fig. 5 shows a schematic diagram of dividing layout areas according to some embodiments of the present disclosure. FIG. 5 includes illustrations 501 , illustrations 502 , and illustrations 503 , wherein illustration 501 shows the initial layout 220 shown in FIG. 3 , and illustration 502 shows a grid array 510 according to some embodiments of the present disclosure. , and diagram 503 shows the result of using grid array 510 in diagram 502 to divide initial layout 220 in diagram 501 .

In illustration 502, grid array 510 includes 16 grids 520-1 through 520-16 (individually and collectively referred to as grid 520). These grids 520-1 to 520-16 have a rectangular shape, and have the same height and the same width, ie, the determined first height and first width. Electronic device 230 may utilize grid array 510 in illustration 502 to divide layout area 310 of initial layout 220 in illustration 501 . As shown in diagram 503, a portion of circuit units may be located in one grid 520, for example, movable circuit unit 320-7 and fixed circuit unit 330-3 are located in grids 520-5 and 520-13, respectively. A part of circuit units may cover two or more grids 520 at the same time, for example, fixed circuit unit 330-2 covers grids 520-4 and 520-8. Since the position of the fixed circuit unit 330 will not be changed, when using this grid array 510 to divide the layout area 310, it is necessary to additionally calculate the fixed circuit unit 330- 2 occupied area.

In order to avoid such additional calculations, in some embodiments, the electronic device 230 may also divide the layout area into 310 is divided irregularly into an array of grids, a first grid in the array of grids having a different height or width than a second grid in the array of grids. For example, referring to illustration 502, the height of grid 520-4 may be increased to the height of fixed circuit unit 330-2, and the height of grid 520-8 may be correspondingly decreased. Similarly, the width of grid 520-4 may be reduced to the width of fixed circuit unit 330-2, and the width of grid 520-3 may be increased accordingly. In this way, the size of a part of the grids 520 in the grid array can be adapted to the size of the fixed circuit unit 330, and these grids 520 previously fully occupied by the fixed circuit unit 330 are no longer considered in subsequent operations, thereby The operating efficiency of the method according to the present disclosure can be improved. In the following, solutions according to various embodiments of the present disclosure will be described with reference to regular rectangular grid array 510 in illustration 502 . It should be understood that the solutions according to the various embodiments of the present disclosure are also applicable to irregularly divided grid arrays, and the scope of the present disclosure is not limited in this respect.

At 404, the electronic device 230 determines a resultant gradient of layout parameters of the initialization layout based on the initialization layout and the netlist data. The composite gradient is based on an initial gradient of the layout parameter and a local average gradient of a set of layout parameters associated with the layout parameter, where the gradient indicates a maximum rate of change of the layout parameter and a direction having the maximum rate of change.

In one embodiment, the layout parameter includes the length of the connection line of the first circuit unit among the plurality of circuit units. The electronic device 230 determines the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data: based on the netlist data and the initialization layout, calculating the first initial gradient of the connection line length of the first circuit unit; based on the netlist data, determining The first associated circuit unit set of the first circuit unit; based on the first initial gradient and the initial gradient of the connection line length of each associated circuit unit in the first associated circuit unit set, calculate the first local average gradient; and based on the first initial The gradient and the first local average gradient are used to calculate the resultant gradient of the connecting line length of the first circuit unit. This embodiment will be described below with reference to FIGS. 6 and 7 .

Fig. 6 shows a schematic diagram of the connection relationship of circuit units according to some embodiments of the present disclosure. Circuit cells C1 to C8 are schematically shown in FIG. 6 , and these circuit cells may be located at different positions in the grid array. For ease of description, grid arrays and other circuit units are not shown here. The circuit unit C1 is directly connected to the circuit units C2, C3 and C4. Circuit unit C3 is connected to C5, circuit unit C4 is connected to C6 and C7, and circuit unit C7 and C8 are connected. FIG. 7 shows a schematic diagram of a composite gradient of a circuit unit according to some embodiments of the present disclosure. In FIG. 7 , for ease of illustration, the connection lines between the various circuit units are omitted, but it can be understood that each circuit unit in FIG. 7 has the connection relationship shown in FIG. 6 . In Fig. 7, the initial gradient of a circuit cell is shown by a thin solid arrow, the local average gradient of a circuit cell is shown by a thin dashed arrow, and the resultant gradient of a circuit cell is shown by a thick solid arrow, where the gradients indicate layout parameters The maximum rate of change and the direction with the maximum rate of change, such as the maximum rate of change and the direction with the maximum rate of change of the line length of the circuit unit. It can be understood that the gradient can actually be represented by a vector. For example, the initial gradients of the circuit cells C1 to C8 can be calculated based on the netlist data and the initialization layout using an analytical optimization function obtained by Lagrangian relaxation technique.

In one embodiment, the following formula can be used to calculate the local average gradient of each circuit unit.

Among them, gl _i represents the local average gradient of the i-th circuit module, n _i represents the number of circuit units associated with the i-th circuit unit, j represents the j-th circuit unit, and k represents the first associated parameter, which is used to specify the level of physical connection of the i-th circuit unit, and

Indicates the initial gradient of each associated circuit unit under the condition that the associated parameter is k.

The circuit unit C1 is taken as an example for description below. When i is 1, k may be specified by the designer or be 1 by default. When k is 1, the associated circuit units of the first circuit unit C1 are the circuit units directly connected to the first circuit unit C1, ie the circuit units C2, C3 and C4. In this case, gl ₁ denotes the local average gradient of the first circuit cell C1, which depends on the initial gradients of the circuit cells C1 to C4. It can be understood that since the circuit units connected to each circuit unit may be different, the local average gradient of each circuit unit may be different. Although a specific calculation manner of the local average gradient is shown by formula (1), this is only for illustration and not limiting the scope of the present disclosure. Other local average gradient calculation methods can be used to calculate the local average gradient. In the case where k is 1, only the local average gradients of the first circuit unit and related circuit units directly connected to the first circuit unit are considered when calculating the composite gradient of the line length above. In this way, the calculation amount and the subsequent iteration time can be reduced, and the overall layout line length of the circuit cells in the overall layout process can still be significantly reduced.

In another embodiment, when k is 2, taking the first circuit unit C1 as an example, its associated circuit units are the circuit units directly connected to the first circuit unit C1 and the circuit units directly connected to these circuit units. Connected circuit unit unit. In this case, the association level of the first circuit unit C1 is two levels, which includes circuit units C2, C3, C4 and circuit units directly connected to the circuit units C2, C3, C4, that is, the association level of the first circuit unit C1 The circuit unit further includes circuit units C5, C6 and C7. At this time, the associated circuit units of the first circuit unit C1 include C2-C7.

After calculating the local average gradient, the composite gradient of each unit can be calculated. For example, the composite gradient can be calculated by the following equation (2).

Substituting formula (1) into formula (2) can get formula (3)

Where α represents the contribution ratio of the local average gradient and the initial gradient of the circuit unit to the composite gradient. In this embodiment, the value of α usually takes a value between 0 and 1, and can be specified by the designer or has a default value. Although Equation (3) is used here to show a specific calculation method of the composite gradient, this is only for illustration and not to limit the scope of the present disclosure. Composite gradients may be calculated using other composite gradient calculation methods.

The composite gradient calculation shown above can be performed for each circuit unit in the chip. Alternatively, the composite gradient calculation shown above may also be performed on a specific part of the circuit units in the chip, which is not limited in the present disclosure. By calculating the composite gradient of the circuit unit, both the unique gradient influence of the circuit unit and the local overall gradient influence can be maintained during the layout process. In this way, it is possible to avoid an increase in line length caused by over-dispersion of associated circuit units in the spreading process of the circuit units. In other words, in this way, the overall layout line length of the circuit units in the overall layout process can be reduced.

FIG. 8 shows a schematic diagram of a resultant gradient of density of circuit cells in a grid according to some embodiments of the present disclosure. In some embodiments, element fill metrics may indicate how densely packed circuit cells are within corresponding grids 520 in grid array 510 . In this case, element fill metrics may also be referred to as cell fill metrics. For the convenience of description, the grid 520 - 6 in the grid array 510 is exemplarily described as the first grid in the following description. The electronic device 230 can use the size information of each circuit unit in the netlist data 210 to calculate the total area of the circuit units located in the first grid 520-6. For example, the circuit cells 320-1 to 320-6 have portions located at the first grid 520-6. In other words, the circuit units 320-1 to 320-6 are at least partially located in the first grid 520-6. When calculating the first grid 520-6, only the total area At of the parts located in the first grid 520-6 among the circuit units 320-1 to 320-6 can be calculated, and the first grid 520-6 has an area An. In one embodiment, the cell density can be expressed as At/An. Although the above method shows a specific calculation method of the cell density, this is only for illustration and not to limit the scope of the present disclosure. In some other embodiments, for example, the ratio of the overall total area Ac of the circuit units 320-1 to 320-6 to the An of the first grid 520-6 can be used to calculate the unit density, which is not discussed in this disclosure. limit.

After that, the following formula can be used to calculate the local average density of each grid.

Among them, GL _i represents the local average density of the i-th grid, n _i represents the number of grids associated with the i-th grid, j represents the j-th grid, and k represents the second associated parameter, which is used for specifies the grid level adjacent to the i-th grid, and

Indicates the initial density of each associated grid under the condition that the associated parameter is k.

The description below takes the first grid 520-6 as an example. When i is 1, k can be specified by the designer or be 1 by default. When k is 1, the associated grids of the first grid 520-6 are grids directly adjacent to the first grid 520-6, that is, grids 520-1, 520-2, 520-3, 520-5, 520-7, 520-9, 520-10, and 520-11. In this case, GL _i represents the local average density of the first grid 520-6, which depends on the grids 520-1, 520-2, 520-3, 520-5, 520-7, 520-9, The initial density of 520-10 and 520-11. It can be understood that since the adjacent grids of each grid can be different, the local average density of each grid can be different. Although a specific calculation method of the local average density is shown by formula (4), this is only for illustration and not to limit the scope of the present disclosure. Other local average gradient calculation methods can be used to calculate the local average density. In the case where k is 1, only the local average denseness of the first grid 520-6 and related grids directly adjacent to the first grid 520-6 is considered when calculating the combined denseness above. In this way, the calculation amount and the subsequent iteration time can be reduced, and the overall layout line length of the circuit cells in the overall layout process can still be significantly reduced.

In another embodiment, when k is 2, taking the first grid 520-6 as an example, its associated grids can be obtained from the above grids 520-1, 520-2, 520-3, 520-5, 520 -7, 520-9, 520-10, and 520-11 expand a circle of grids outward.

After the local average density is calculated, the combined density of each unit can be calculated. For example, the synthesis intensity can be calculated by the following formula (2).

Substituting formula (4) into formula (5) can get formula (6)

Where α represents the contribution ratio of the local average density and the initial density of the grid to the composite density. In this embodiment, the value of α usually takes a value between 0 and 1, and can be specified by the designer or has a default value. In some embodiments, the value of α can also take a negative value. For example, an initial value of the density of circuit units of the first grid 520 - 6 may be calculated, and if the initial value is higher than a first threshold, α may be set as a negative number. When α is a negative number, if the initial density of the layout unit itself is greater than its average field density value, the final result of the average field density calculation formula (6) is greater than the initial density, which is equivalent to the Mesh congested areas are multiplied by a factor greater than 1. For example, as shown in FIG. 8 , the thick arrow representing the resultant gradient of the first mesh 520-6 is longer than the thin arrow representing the initial gradient of the first mesh 520-6. If the initial denseness of the grid such as the second grid 520-3 is partly smaller than the average field denseness value, the final result in the average field denseness calculation formula (6) is smaller than the initial denseness, which is equivalent to A factor less than 1 is multiplied for under-congested areas. For example, as shown in FIG. 8 , thick arrows representing the composite density of the second grid 520 - 3 are shorter than thin arrows representing the initial density of the second grid 520 - 3 . Such a "Matthew effect" can cause circuit cells in more congested grids to spread out more quickly, while circuit cells in less congested grids generally move less. Although formula (6) is used here to show a specific calculation method of the synthesis intensity, this is only for illustration and not to limit the scope of the present disclosure. Other calculation methods of composition intensity can be used to calculate the composition intensity.

The compositing intensity calculation shown above can be performed for each grid in the layout area. Alternatively, the synthesis intensity calculation shown above may also be performed on a specific mesh in the chip, and this disclosure is not limited thereto. For example, in some embodiments, the value of the density of circuit units of each grid may be calculated first, and compared with the second threshold. If it is not higher than the second threshold, it indicates that the density of circuit units in the grid is low, and no adjustment is required. If above the second threshold, then use the method of synthesis density above to adjust the circuit cells in the grid. In this way, the time and computation for computing the compositing intensity of the mesh can be reduced, and the time and computation for subsequent iterations correspondingly reduced.

After that, based on the calculated composite density of the grid, it may be converted into a composite density of circuit units in the grid using a conventional conversion method, which is not limited in the present disclosure.

In some other embodiments, an electrostatic field model may also be used to approximately describe the uniformity of layout unit distribution, and a result of uniform density distribution may be obtained by solving a Poisson (possion) equation. After solving the electric field, the effect of the local mean field can also be considered, and the calculation formula is still consistent with the aforementioned formula (6). The local additional weighted calculation is performed on the electric field distribution calculated by the electric field model. In addition to its own electric field contribution (that is, the initial electric field), each grid also considers the average contribution of the surrounding adjacent grids at the grid position to obtain a smooth The electric field distribution is improved, so that the change of the subsequent electric field gradient tends to be smooth. In this embodiment, the definition of the association grid may be the same as the above definition of the association grid in FIG. 8 , which will not be repeated here.

When calculating the electric field distribution of grids such as the first grid 520-6, it can be divided into two parts. The first part is the electric field strength obtained by solving the possion equation in the electric field model, and the second part is such as the first grid The calculation formula of the average gradient field contribution of grids such as grid 520-6 as the center of 3x3, 5x5, etc. is still as described in the aforementioned formula (6). After obtaining the smoothed electric field in this way, the final gradient of each layout unit is also a relatively continuous transition, thereby improving the final convergence result to a certain extent. In the embodiment of the electric field, the general value in the above formula (6) can be a positive value, so that a smoother layout optimization result with better quality can be obtained.

Returning again to FIG. 4 , at 406 , based on the synthesized gradient and the initial layout, a target layout of the plurality of circuit cells in the grid array is determined. In one embodiment, at least one of the synthetic gradient of the line length of the above circuit unit and the synthetic density of the circuit unit in the grid can be used as the gradient of the iterative solution, and utilize such as Adam or Nesterov optimizer The optimizer performs an iterative solution. For example, in one embodiment, it can be solved iteratively by using the following optimization objective function (7).

min(WL(x,y)+λD(w,y)) (7)

Among them, WL(x,y) represents the HPWL under the current layout, D(x,y) represents the density of standard units corresponding to the current layout, λ represents the weighting coefficient, and can be specified by the designer or use the default value.

After this, the placement of the layout units can be regularized and the final result output. In an embodiment of the present disclosure, a local average gradient may be applied to at least one of the line length gradient of the circuit unit and the density of the circuit units in the grid, so as to obtain a corresponding synthesis item. During the layout process, not only the layout parameters themselves, but also the local average items associated with the layout parameters can be considered, so that the layout optimization of the circuit cells can be performed with the synthesized items. In this way, a plurality of associated circuit units can be evenly spread out during the layout process, and can also maintain a tight connection relationship during the spread out process. In other words, layout parameters such as line length and layout compactness of circuit cells have both their own unique influence and local overall influence during the layout iteration process. In this way, compared with the conventional analytical overall layout, the final layout result obtained according to the first aspect of the present disclosure can lead to improved layout quality, for example, reduced final line length such as HPWL characterization.

In addition, when performing multiple local mean field gradient calculations in a unified calculation method, the mean fields of different scales can be calculated and combined. Further, an attenuation coefficient α can be added to the mean field gradient to improve the convergence quality and a negative α can be added to the mean field gradient to speed up the convergence speed.

FIG. 9 shows a schematic block diagram of an electronic device 900 according to some embodiments of the present disclosure. The electronic device 900 may be implemented as or included in the electronic device 230 of FIG. 2 .

The electronic device 900 may include a plurality of modules for performing corresponding steps in the method 400 as discussed in FIG. 4 . As shown in FIG. 9 , the electronic device 900 includes an initialization module 902 configured to: based on the netlist data of the chip, initialize a plurality of circuit units in the chip in a grid array in the layout area, so as to obtain a plurality of circuit units In the initial layout in the grid array, the netlist data at least indicates the size of the plurality of circuit units and the connection relationship of the plurality of circuit units. The electronic device 900 further includes a composite item determination module 904 configured to: determine a composite item of the layout parameters of the initialization layout based on the initialization layout and the netlist data, the composite item is based on the initial item of the layout parameters and the layout parameters associated with the layout parameters The local average term of the set. The electronic device 900 further includes a target layout determination module 906 configured to: determine a target layout of the plurality of circuit units in the grid array based on the synthesized item and the initialization layout. In the layout process, not only the gradient of the layout parameter itself is considered, but also the local average gradient associated with the layout parameter is considered, so that the layout optimization of the circuit unit can be performed with the synthetic gradient. In this way, a plurality of associated circuit units can be evenly spread out during the layout process, and can also maintain a tight connection relationship during the spread out process. In other words, layout parameters such as line length and layout compactness of circuit cells have both their own unique gradient influences and local overall gradient influences during the layout iteration process. In this way, compared with the conventional analytical overall layout, the final layout result obtained according to the first aspect of the present disclosure can lead to improved layout quality, for example, reduced final line length such as HPWL characterization.

In some embodiments, the layout parameters include the gradient of the connection line length of the first circuit unit among the plurality of circuit units, the composite item includes the composite gradient of the connection line length, and the gradient indicates the maximum change rate of the layout parameter and the maximum change rate of the layout parameter. direction. The synthetic item determination module 904 includes: a calculation module configured to calculate the first initial gradient of the connection line length of the first circuit unit based on the netlist data and the initialization layout; an associated circuit unit set determination module configured to: based on the netlist data , to determine the first associated circuit unit set of the first circuit unit; the calculation module is further configured to: based on the first initial gradient and the initial gradient of the connection line length of each associated circuit unit in the first associated circuit unit set, calculate the first a local average gradient; and based on the first initial gradient and the first local average gradient, calculating a resultant gradient of the connecting line length of the first circuit unit.

In some embodiments, determining the composite gradient of the layout parameters of the initialization layout based on the initialization layout and the netlist data includes: for each circuit unit in the plurality of circuit units, calculating the corresponding initial Gradients, determining a respective set of associated circuit units for each circuit unit, calculating a corresponding local average gradient for each circuit unit, and calculating a corresponding resultant gradient for the connecting line lengths of each circuit unit. By calculating the composite gradient of the circuit unit, both the unique gradient influence of the circuit unit and the local overall gradient influence can be maintained during the layout process. In this way, it is possible to avoid an increase in line length caused by over-dispersion of associated circuit units in the spreading process of the circuit units. In other words, in this way, the overall layout line length of the circuit units in the overall layout process can be reduced.

In some embodiments, the associated circuit unit set determination module is further configured to: determine the first associated circuit unit set of the first circuit unit based on the netlist data and the first associated parameter, the first associated parameter is used to specify the first circuit The level of physical connection of the unit. For example, the first association parameter is used to specify that the level of the physical connection of the first circuit unit is level 1 indicating direct connection. In other words, only the local average gradients of the first circuit unit and related circuit units directly connected to the first circuit unit are considered when calculating the synthetic gradient of the line length above. In this way, the calculation amount and the subsequent iteration time can be reduced, and the overall layout line length of the circuit cells in the overall layout process can still be significantly reduced.

In some embodiments, the layout parameters include the density of the first grid in the grid array, the density of the first grid represents the density of the circuit units in the first grid, and the synthesis item includes The synthesis intensity of the circuit unit. The composite item determination module 904 is further configured to: calculate the first initial density of the first grid based on the initial layout and netlist data; determine the associated grid set of the first grid based on the initial layout; Intensity and the corresponding initial intensities of each associated grid in the associated grid set, calculating a first local average intensification; based on the first initial intensification and the first local average intensification, calculating a composite intensification for the first grid ; and based on the composition density of the first grid, determining a first composition density of the circuit cells in the first grid.

In some embodiments, the composite item determination module 904 is further configured to: for each grid in the grid array, in a manner similar to the above, calculate the corresponding initial density of each grid, and determine the Respective associative mesh sets, computing a corresponding local average density for each mesh, and computing a corresponding composite density for each mesh, and determining the density of circuit cells within a mesh based on the mesh's composite density . Through the synthetic gradient of the cell compactness of each grid, it is possible to maintain both the unique gradient influence of a single grid and the overall gradient influence of a local grid during the layout process. For example, it is possible to prevent multiple circuit units from gathering in another grid again during the spreading process. In this way, the spreading process of the circuit units can be made more uniform, so as to obtain a better layout effect.

In some embodiments, the associated grid set determining module is further configured to: determine an associated grid set of the first grid based on the initial layout and a second associated parameter, the second associated parameter is used to specify Neighboring grid level. For example, the second association parameter is used to designate the adjacent grid level of the first grid as level 1 representing direct adjacency. In other words, when calculating the composite gradient of the cell density of the grid above, only the local average gradient of the cell density of the first grid and related grids directly adjacent to the first grid is considered. In this way, the amount of computation and subsequent iteration time can be reduced and still achieve significant layout effects.

In some embodiments, the synthesis item determination module 904 is further configured to: determine the initial item and the local average item of the layout parameters based on the initialization layout and the netlist data; calculate the first product of the initial item and the first coefficient; calculate the local average A second product of the term and the second coefficient; and adding the first product to the second product to determine a resultant term of the layout parameter. In an implementation manner of the second aspect, the sum of the first coefficient and the second coefficient is 1. By setting different coefficients, relevant parameters in the layout process can be adjusted based on the configuration of the circuit, which in turn can affect the layout quality and/or the speed and time required for layout iterations. For example, in the case where the layout parameter is the cell density of the grid, if the density is greater, the coefficient can be set to make the circuit cells spread out faster, thereby speeding up subsequent iterations and reducing the number of steps required for final convergence .

In some embodiments, the electronic device 900 further includes an initial value determination module configured to determine an initial value of the layout parameter; and a setting module configured to set the second coefficient to negative value. For example, the layout parameter may be the density of cells in the grid of the grid array, and the initial value may be the initial value of the density of cells in a grid. By confirming the initial value of the layout parameter before the iteration and comparing the initial value with the threshold value, the circuit cells in the denser grid can be dispersed faster, thereby saving the calculation amount and time of the layout iteration.

Fig. 10 shows a schematic block diagram of an example device 1000 that may be used to implement embodiments of the present disclosure. Device 1000 may be used to implement electronic device 230 . As shown, device 1000 includes computing unit 1001, which may be loaded into RAM 1003 and/or Computer program instructions in ROM 1002 to perform various appropriate actions and processes. In the RAM 1003 and/or the ROM 1002, various programs and data necessary for the operation of the device 1000 can also be stored. The computing unit 1001 and the RAM 1003 and/or ROM 1002 are connected to each other via a bus 1004. An input/output (I/O) interface 1005 is also connected to the bus 1004 .

Multiple components in the device 1000 are connected to the I/O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The computing unit 1001 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 1001 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 1001 executes various methods and processes described above, such as the method 400 . For example, in some embodiments, method 400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1008 . In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 1000 via RAM and/or ROM and/or the communication unit 1009 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 1001, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the method 400 in any other suitable manner (for example, by means of firmware).

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

In addition, while operations are depicted in a particular order, this should be understood to require that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations should be performed to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

A method for designing a layout comprising:

Based on the netlist data of the chip, initialize the plurality of circuit units in the chip in the grid array of the layout area, so as to obtain the initialization layout of the plurality of circuit units in the grid array, the network The table data indicates at least the size of the plurality of circuit units and the connection relationship of the plurality of circuit units;

Based on the initialization layout and the netlist data, determining a composite item of a layout parameter of the initialization layout, the composite item is based on an initial item of the layout parameter and a local average item of a layout parameter set associated with the layout parameter ;as well as

A target layout of the plurality of circuit cells in the grid array is determined based on the synthesized items and the initialization layout.
The method according to claim 1, wherein the layout parameters include a gradient of a connection line length of a first circuit unit among a plurality of circuit units, and the composite term includes a composite gradient of the connection line length, the gradient indicating The maximum rate of change of the layout parameters and the direction with the maximum rate of change, based on the initialization layout and the netlist data to determine the synthetic items of the layout parameters of the initialization layout include:

calculating a first initial gradient of the connection line length of the first circuit unit based on the netlist data and the initialization layout;

determining a first set of associated circuit units of the first circuit unit based on the netlist data;

calculating a first local average gradient based on the first initial gradient and the initial gradient of the connection line length of each associated circuit unit in the first set of associated circuit units; and

Based on the first initial gradient and the first local average gradient, a composite gradient of the connecting line length of the first circuit unit is calculated.
The method of claim 2, wherein determining a first set of associated circuit elements of the first circuit element based on the netlist data comprises:

A first set of associated circuit units of the first circuit unit is determined based on the netlist data and a first association parameter, where the first association parameter is used to specify a level of physical connection of the first circuit unit.
The method according to any one of claims 1-3, wherein the layout parameters include the degree of density of the first grid in the grid array, and the degree of density of the first grid indicates that the circuit unit is in the The degree of density in the first grid, the synthesis item includes the degree of synthesis density of the circuit cells in the first grid, and the synthesis item of the layout parameters of the initialization layout is determined based on the initialization layout and the netlist data include:

calculating a first initial density of the first grid based on the initialization layout and the netlist data;

determining an associated grid set for the first grid based on the initialization layout;

calculating a first local average density based on the first initial density and the corresponding initial density of each associated mesh in the set of associated meshes;

calculating a composite density of the first mesh based on the first initial density and the first local average density; and

Based on the composition density of the first grid, a first composition density of circuit units in the first grid is determined.
The method of claim 4, wherein determining a first set of associated circuit elements for the first circuit element based on the initialization layout comprises:

An associated grid set of the first grid is determined based on the initialized layout and a second associated parameter, where the second associated parameter is used to specify a grid level adjacent to the first grid.
The method according to any one of claims 1-5, wherein determining the synthetic item of the layout parameters of the initialization layout based on the initialization layout and the netlist data comprises:

determining the initial term and the local average term of the layout parameters based on the initialization layout and the netlist data;

calculating a first product of the initial term and a first coefficient;

calculating a second product of the local average term and a second coefficient; and

Adding the first product and the second product to determine a composite term for the layout parameters.
The method of claim 6, wherein the sum of the first coefficient and the second coefficient is one.
The method according to claim 7, further comprising:

determining initial values for the layout parameters; and

In response to the initial value being higher than a first threshold, the second coefficient is set to a negative value.
An apparatus for designing a layout, comprising:

The initialization module is configured to: initialize the plurality of circuit units in the chip in the grid array of the layout area based on the netlist data of the chip, so as to obtain the grid array of the plurality of circuit units in the grid array The initialization layout of the network list data at least indicates the size of the plurality of circuit units and the connection relationship of the plurality of circuit units;

A synthetic item determination module configured to: determine a synthetic item of a layout parameter of an initialization layout based on the initial layout and the netlist data, the synthetic item is based on an initial item of the layout parameter and is related to the layout parameter The local average term of the linked layout parameter set; and

A target layout determination module configured to: determine a target layout of the plurality of circuit units in the grid array based on the synthetic gradient and the initialization layout.
The apparatus according to claim 9, wherein the layout parameters include a gradient of a connection line length of a first circuit unit among a plurality of circuit units, and the composite term includes a composite gradient of the connection line length, the gradient indicating The maximum rate of change of the layout parameters and the direction with the maximum rate of change, the synthetic item determination module includes:

a calculation module configured to calculate a first initial gradient of the connection line length of the first circuit unit based on the netlist data and the initialization layout;

An associated circuit unit set determining module configured to: determine a first associated circuit unit set of the first circuit unit based on the netlist data;

The calculation module is further configured to:

calculating a first local average gradient based on the first initial gradient and the initial gradient of the connection line length of each associated circuit unit in the first set of associated circuit units; and

Based on the first initial gradient and the first local average gradient, a composite gradient of the connecting line length of the first circuit unit is calculated.
The apparatus according to claim 10, wherein the associated circuit unit set determination module is further configured to:

A first set of associated circuit units of the first circuit unit is determined based on the netlist data and a first association parameter, where the first association parameter is used to specify a level of physical connection of the first circuit unit.
The device according to any one of claims 9-11, wherein the layout parameters include the degree of density of the first grid in the grid array, and the degree of density of the first grid indicates that the circuit unit is in the The degree of density in the first grid, the synthesis item includes the degree of synthesis density of the circuit units in the first grid, and the synthesis item determination module includes:

A calculation module configured to: calculate a first initial density of the first grid based on the initialization layout and the netlist data;

An associated grid set determining module configured to: determine an associated grid set of the first grid based on the initialization layout;

The calculation module is further configured to:

calculating a first local average density based on the first initial density and the corresponding initial density of each associated mesh in the set of associated meshes; and

calculating a first composite density of the first grid based on the first initial density and the first local average density; and

Based on the composition density of the first grid, the composition density of the circuit units in the first grid is determined.
The apparatus of claim 12, wherein the associated mesh set determination module is further configured to:

An associated grid set of the first grid is determined based on the initialized layout and a second associated parameter, where the second associated parameter is used to specify a grid level adjacent to the first grid.
The device according to any one of claims 9-13, wherein the composite item determination module is further configured to:

determining the initial term and the local average term of the layout parameters based on the initialization layout and the netlist data;

calculating a first product of the initial term and a first coefficient;

calculating a second product of the local average term and a second coefficient; and

Adding the first product and the second product to determine a composite term for the layout parameters.
The apparatus of claim 14, wherein the sum of the first coefficient and the second coefficient is one.
The apparatus of claim 15, further comprising:

an initial value determination module configured to determine an initial value of the layout parameter; and

A setting module configured to set the second coefficient to a negative value in response to the initial value being higher than a first threshold.
An electronic device comprising:

at least one processor;

at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor that, when executed by the at least one processor, cause the The device performs the method according to any one of claims 1-8.
A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.
A computer program product, characterized in that the computer program product includes computer-executable instructions, and when the computer-executable instructions are executed by a processor, the computer implements the method according to any one of claims 1 to 8. method.