CN114970440B - Wiring method of ultra-large scale integrated circuit channel - Google Patents
Wiring method of ultra-large scale integrated circuit channel Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G06F30/39—Circuit design at the physical level
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The invention relates to a wiring method of a very large scale integrated circuit channel. A new and efficient solution to the channel routing problem for the i Xin Ji quantum annealing was proposed. The problem of channel wiring of the integrated circuit can be equivalent to a graph coloring problem of searching the least color types in the application, the graph coloring problem can be effectively solved by using the I Xin Ji quantum annealing, and based on the thought, a scheme for solving the problem of channel wiring by using the I Xin Ji is provided.
Description
Technical Field
The invention relates to the technical field of integrated circuit design and manufacture, in particular to a wiring method of a very large scale integrated circuit channel.
Background
Integrated circuit designs are integrated circuit layouts designed by means of Electronic Design Automation (EDA) tools and delivered to integrated circuit manufacturers, and the integrated circuit functions are realized by transferring a circuit mask onto a wafer through a series of manufacturing processes such as preparation of the circuit mask, oxidation, doping, photoetching and the like of the wafer. For digital circuit design, the layout design flow comprises the steps of behavior level synthesis, logic synthesis, physical design, layout optimization and the like. The physical design is the most time-consuming and most influencing step of chip performance, and is divided into steps of layout planning, layout, clock tree synthesis, wiring and the like, and the channel wiring refers to a stage of distributing routing channels in the wiring unit rows before detailed wiring after the overall wiring determines the network topology and the wiring layer distribution in the wiring process. Good channel routing not only can speed up convergence of detailed routing but also can optimize chip routing wire length.
Reliability technology in engineering applications throughout the stages and aspects of VLSI demand analysis, product design, manufacturing processes, test detection, and application of the overall process, the development of conventional electronics and aerospace technology has placed increasing reliability demands on and motivated the continued development of VLSI reliability technology. The reliability of the VLSI is ensured, and the reliability of the VLSI is ensured and improved by mainly controlling the reliability of the final product through reliability tests and screening in the past, turning to enhancing the process control, enhancing the cooperation of the reliability design and the functional design, providing countermeasure measures for the main failure mechanism while considering the process capability and the functional design, comprehensively balancing the reliability indexes and the cost of the VLSI in the whole life cycle and under specific environmental conditions, and introducing proper reliability technology balance mechanisms in the links of circuit design, structural design and layout, material selection, process flow and parameter selection and process control, design verification and evaluation, reliability test evaluation and screening of the product and the like.
In chip fabrication, the nodes of mainstream uv lithography line widths such as 65nm/45nm and 28nm/22nm are developed and the number of transistors receivable on a chip is correspondingly increased due to the reduction of feature sizes, so that the problem size and complexity of circuit design are continuously increased, which makes it necessary for the conventional wiring tool to have the capability of handling the larger-scale complex problem.
Further, at manufacturing process nodes with a photoresist width of, for example, 65nm and below, the delay on the metal interconnect line has been more than seventy percent of the overall circuit delay, and the problem of crosstalk between interconnect lines has become an important factor affecting the chip delay performance. Therefore, conventional routing tools must take into account crosstalk optimization in circuit design that handles these manufacturing processes. As integrated circuit fabrication processes continue to increase, feature sizes rapidly decrease, the number of transistors that can be accommodated on a chip increases accordingly, and the complexity of circuit designs increases accordingly.
The traditional channel wiring method based on linear distribution divides each section of wiring after global wiring into a series of continuous unit wirings, distributes and merges one by one, distributes the unit wirings with the same channel number each time, and the obtained local reasonable design possibly slows down or even does not converge the subsequent detailed wiring convergence. The present application proposes a better solution to the routing-related problems of very large scale integrated circuit channels.
Disclosure of Invention
The application discloses a wiring method of a very large scale integrated circuit channel, comprising the following steps:
and establishing a horizontal constraint graph of the connecting line according to the connecting line condition of a given channel, wherein the horizontal constraint graph is used for constructing an I Xin Hami ton quantity, and distributing the connecting line to different horizontal trend tracks according to the annealing evolution result of the I Xin Hami ton quantity.
The method, wherein:
on the premise of defining that horizontal line segments of different connecting lines on the same wiring track are not overlapped, the number of the wiring tracks is minimized according to annealing evolution results.
The method, wherein:
the method for establishing the horizontal constraint map comprises the following steps: and taking each connecting line as a node, and connecting the nodes corresponding to the two connecting lines by using one edge if the two connecting lines arranged in the same wiring track are overlapped.
The method, wherein:
finding the value of M in a graph coloring mode and coloring each node of the horizontal constraint graph by using M colors, wherein M colors are required to be colored for each node, but M-1 colors cannot be used for coloring each node: the M colors are defined at this time as the minimum color category required and equivalent to the number of track traces with the minimum number of track traces.
The method, wherein:
the maximum degree of the nodes in the horizontal constraint graph is delta, M is found in the range of the initial value interval 2 which is more than or equal to M and less than or equal to delta+1 of the color category number, and the initial midpoint of the interval is M 0 ＝(2+Δ+1)/2。
The method, wherein:
if the annealing evolution of the I Xin Hami ton quantity has a solution, updating to obtain a new value interval of the color category number and updating the interval to be 2-M 0 。
The method, wherein:
if the annealing evolution of the I Xin Hami ton quantity is not solved, updating to obtain a new value interval of the color category number and updating the interval to M 0 ≤M≤Δ+1。
The method, wherein:
obtaining a new interval M through k iterations k-1 M is more than or equal to delta+1, wherein M is more than or equal to k-1 Is the midpoint of the new interval obtained from the k-1 th iteration.
The method, wherein:
midpoint M of the new interval of the kth iteration k ＝(M k-1 +delta+1)/2, each iteration solving M by the annealing evolution of the I Xin Hami ton quantity k Whether the coloring problem of the colors is solved or not, and iterating for a plurality of times until a situation that M colors can be colored for each node, but M-1 colors cannot be colored for each node is found.
The application discloses another wiring method of a very large scale integrated circuit channel, which comprises the following steps:
s10, constructing a horizontal constraint graph according to the connecting lines of the channels;
s11, constructing an I Xin Hami ton amount by a value interval of the color category number corresponding to the node in the horizontal constraint graph;
s12, annealing evolution is carried out on the I Xin Hami ton quantity;
s13, judging whether the annealing evolution result has a solution, if not, executing the step S14, otherwise, executing the step S15;
s14, iterating out a new value interval, and repeatedly executing the steps S11-S13;
s15, finding out the minimum color types required by the coloring of the graph, and minimizing the number of the wiring tracks according to the minimum color types on the premise that horizontal line segments of different connecting lines on the same wiring track are not overlapped.
The channel wiring problem is a sub-problem of integrated circuit wiring, and belongs to the field of integrated circuit design. The method of I Xin Ji quantum annealing in the quantum physical frontier domain is applied here in integrated circuit wiring.
Regarding the Channel Routing Problem (CRP), given a channel and channel interconnect (net) scenario, assigning links to individual horizontal trace tracks (tracks) requires that the horizontal segment portions of different links within the same trace track (track) not overlap (this constraint is called a horizontal constraint). Solving the problem of how to allocate to minimize the number of track tracks (tracks) used is mathematically equivalent to a graph coloring problem that similarly requires the least variety of colors.
With respect to the graph coloring problem, given an undirected graph, given n colors, coloring is required for each node in the graph and the coloring rule requires that the colors of the nodes at both ends of each edge must be different. The minimum number of colors needed to color a single map and how to color is an NP-complete problem (Non-deterministic Polynomial).
By I Xin Ji is meant a physical system constructed and its Hamiltonian H ising Has the following form:
s in Hamiltonian i Sum s j Is the eosin spin: the value is + -1. The end result of the annealing evolution of the I Xin Ji quantum corresponds to a solution to the graph coloring problem as long as the corresponding I Xin Hami ton is constructed for the graph coloring problem and various constraints and various optimization objectives are embodied in the I Xin Hami ton. The graph coloring assignment problem can then be effectively solved with the aid of the graph Xin Jigao.
While genetic algorithms, ant colony algorithms, etc. have been developed for such wiring problems, these algorithms tend to be ineffective once faced with large-scale wiring conditions (meaning many wires in the channel). The channel wiring problem of the integrated circuit can be equivalent to a graph coloring problem searching for the least color types, and the graph coloring problem can be efficiently solved by using the I Xin Ji quantum annealing and is based on the thought, the application proposes a scheme for solving the channel wiring problem by using the I Xin Ji: the method can be applied to the channel wiring problem (channel routingproblem) in the field of very large scale integrated circuit wiring and is called CRP for short.
The channel wiring problem is a sub-problem of integrated circuit wiring, and belongs to the field of integrated circuit design. The method of I Xin Ji quantum annealing in the quantum physical frontier domain can be applied to integrated circuit wiring.
Drawings
So that the manner in which the above recited objects, features and advantages of the present application can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings.
FIG. 1 is a schematic diagram of an alternative example of converting a channel routing problem of an integrated circuit to a graph coloring problem.
FIG. 2 is an example of each line in a channel as a graph node, e.g., five lines for five nodes.
Fig. 3 is a diagram construction schematic of the corresponding amount of i Xin Hami ton of the diagram coloring problem for constructing a plurality of colors.
Detailed Description
The solution according to the invention will now be described more clearly and completely in connection with the following examples, which are given by way of illustration only and not by way of all examples, on the basis of which the person skilled in the art obtains without any inventive effort.
Referring to fig. 1, the present application relates to a Very Large Scale Integration (VLSI) circuit channel routing problem solver based on an i Xin Ji (Ising machine) quantum anneal. The term via in the integrated circuit industry, for example, refers to a lateral routing area and the top and bottom of this area are populated with squares or areas that need to be connected, requiring the use of metal lines to connect the corresponding pins or areas together. Integrated circuit designs consist of a chrome plating stage, where an important design stage is the physical design, such as placing the device in place, and making electrical connections with wire-bond devices, where the latter is called routing and it is a problem that electronic design automation EDA tools need to address. A channel is a term of art referred to in the present context as a wiring design phase.
Referring to fig. 1, a channel routing problem solution for the i Xin Ji quantum anneal is as in steps S10-S15. This solution, for example, in the case of a given channel and channel interconnect (net), belongs to the chip-related segment, assigning the interconnect to each horizontal trace (track), requiring that the horizontal segment portions of different interconnects within the same trace (track) not overlap (this class of constraint is called horizontal constraint). In the metal interconnection layer of the transistor of the chip, if the wirings are overlapped or touched or overlapped or contacted in the same horizontal plane, accidents such as short circuit (short) and the like can be caused, so that the horizontal line segments of different wirings on the same wiring track can not be overlapped or crossed.
Referring to fig. 1, a horizontal constraint graph is constructed from channels and their wiring. One of the purposes is to solve how to distribute the trace so as to minimize the number of traces (tracks), and the main scheme includes the following points (steps) which will be described in detail below.
Referring to fig. 1, a horizontal constraint graph (horizontal constraint graph) is constructed according to the channel and its internal connection at a relevant first point of minimizing the number of used track tracks, and the horizontal constraint graph may be abbreviated as HCG, and a specific construction process is described in a relevant explanation section of the following description. The first point is embodied in step S10.
Referring to fig. 1, the channel routing problem CRP is mathematically equivalent to "coloring with the least color class HCG" at the relevant second point where the number of tracks (tracks) used is the least, let the number of nodes in HCG (nodes) be the greatest Δ then knowing that Δ+1 colors must be able to color HCG, and certain conditions are met at the following intervals:
2≤M≤Δ+1
for example, M is found in this interval so that M colors can be colored, while M-1 colors cannot be colored. If the mid-point of the interval is M 0 Construction of M 0 The graph coloring problem of the color corresponds to the i Xin Hami ton. The second point of the i Xin Hami ton size problem is embodied in step S11: determining the type of color from the value interval, and constructing a reasonable I Xin Hami ton quantity function H according to the coloring problem of the horizontal constraint graph ising 。
Referring to fig. 1, the mathematical calculation of the simplified i Xin Hami ton amount is performed at the third point of the trace track (track) with the least number to obtain the standard i Xin Hami ton amount, the standard parameters are input into the isooctane machine and the quantum annealing evolution is performed, and the third point is embodied in step S12.
Referring to fig. 1, a fourth point of correlation with the least number of used track is determined according to the output of the i Xin Ji after evolution is finished, if yes, the interval is updated as follows:
2≤M≤M 0
in the opposite case, the interval is updated without solution as:
M 0 ≤M≤Δ+1
the fourth point of determining whether there is a solution is embodied in step S13: when the annealing is finished, the isooctane machine outputs the result and judges whether there is a solution according to the annealing result, after which step S14 may call back the case of the interval or jump to step S15. The main content of step S14 is shown in the figure: for example, the value interval is updated according to the output result of the previous round of the i Xin Ji. The main content of step S15 is shown in the figure: if the value interval is small enough after step S13, the minimum color type required for coloring can be found out, the output can be finished at this time, and the output result is a solution of the channel wiring problem.
The preferred option of the solution is to take the mid-point of the interval as M 1 Returning to step S11, build M 1 The steps S11-S12-S13 are repeated for an amount of I Xin Hami ton corresponding to the chart coloring problem of the seed color. After the first round of cycling, it is still possible to repeat steps S11-S12-S13, i.e. the second round of cycling, after performing step S14 if necessary. It is still possible to repeat steps S11-S12-S13, i.e. the third round of the loop, after performing step S14 if necessary. The process can be iterated continuously, which is equivalent to a binary search process, and the interval range is reduced continuously until M is found, so that M colors can be colored, and M-1 colors cannot be colored. The M colors are the minimum color types required, and the output of i Xin Ji is: i.e. a scheme of coloring of M colors.
Referring to fig. 2, regarding the horizontal constraint graph HCG construction: first, each wire (net) in the channel is regarded as a node (node) of a graph, if two wires are placed in the same track (track), respective horizontal line segments will overlap (which means that the two wires cannot be placed in the same track), and the nodes corresponding to the two wires can be connected by a single edge (edge) or an edge. Thereby constructing a horizontal constraint graph HCG.
Referring to fig. 2, the map does not refer to a graphic image (image) or map. Generally, the industry views a graph as an abstract network of "vertices," where each vertex in the network can be connected to each other by an "edge" and represent that the two vertices are associated. Note that here the two keywords in the graph definition, from which we get the two most basic concepts we are most basic, namely vertex (vertex) and edge (edge). The above are the most central items of content of the graph theory. Accordingly, the term "Graph" as used herein refers to a Graph in the Graph theory (Graph) field, and concepts such as the horizontal constraint Graph which are extended from this Graph naturally belong to the Graph in the Graph theory field. The graph is composed of vertices, nodes, or points/vertices connected by edges, arcs, or lines.
Referring to fig. 2, a vertex describes something or an object. Since the terms of the graph are not standardized, the vertices may be referred to as points or nodes or endpoints, etc. The same applies to vertex terms in the context of the application.
Referring to fig. 2, edges represent things-to-things relationships. Edges represent the logical relationship between vertices.
Referring to fig. 2, a Directed Graph/Undirected Graph (Directed Graph). The most basic graph is generally defined as an undirected graph and the corresponding graph is called a directed graph. The difference is that the edges in the directed graph are directional.
Referring to fig. 2, the weight (weight) belongs to a weight, an overhead, and a length, and each edge has a value corresponding to the weight. For example, when a vertex represents some physical location or the like, the weight of an edge between two vertices may be set as a distance in the road network. Sometimes, to cope with special cases, the weights of the edges may be zero or negative.
Referring to fig. 2, regarding the horizontal constraint graph HCG construction: each line (net 1-net12, etc.) in the channel is regarded as a node or a vertex of a graph, if two lines are placed in the same track, the respective horizontal line segments will overlap (this means that the two lines, such as net1/net2, cannot be placed in the same track), and a node corresponding to the two lines can be connected by an edge (edge) in the graph. Similarly, a node corresponding to the two-by-two connection lines between net2 and net3-net4 is connected by an edge (edge). As a counterexample, wires net1-net2 and net5 are placed in the same track without overlapping. Thereby constructing a horizontal constraint map. Of course, the number of channels and connections in an actual design of an integrated circuit is far greater than the example shown in the figures.
Referring to fig. 3, a horizontal constraint map of connections is established based on the connection conditions (e.g., fig. 2) of a given channel.
Referring to FIG. 2, a graph is a more powerful framework in data structures and algorithms. The graph can be used for representing all types of structures or systems, from a traffic network to a communication network, from chess playing to optimal flow solving, from task distribution to an interpersonal interaction network and other field graphs, and has wide utilization points. With respect to the world of graph theory, clear and accurate basic concepts are necessary premises and foundation. The concept of graph theory is remarkable, and the vertex and the edge are the most core contents of graph theory.
Referring to fig. 2, the development of the quantum computer gradually tends to mature and scale, such as a simulation system with quantum computing function based on a traditional computer structure, and development approaches and tools of quantum algorithm are provided. The existing quantum simulation system is mainly deployed on supercomputers and cloud computing platforms, and compared with the traditional computer, the quantum computer has exponential computing acceleration. A way based on the quantum annealing of the i Xin Ji is sought, so that the problem of solving the i Xin Wenti and also the problem of channel wiring are both realized.
Referring to FIG. 3, the connecting edge (uv) assigns a weight W uv S (u, V) as in the graph neural network g= (V, E). Vertices or points or nodes or endpoints in the graph represent connections in the circuit channels, and connecting edges (belonging to edge) represent connection relationships and weight relationships between vertices. The wiring is also called wiring, and attention is paid to the difference between the wiring and the edge of the graph.
Referring to fig. 2, since the integration level of the very large scale integrated circuit has been rapidly increased at a speed of doubling every 18 months following the moore's law, the number of integrated circuit elements on a chip has already exceeded one hundred million, the development trend of the very large scale integrated circuit is changing the role played by the very large scale integrated circuit in electronic equipment from a device chip to a system chip (SOC), meanwhile, the process feature size of the very large scale integrated circuit with deep submicron has reached a few nanometers or less, and under the condition that the feature size is continuously reduced and the integration level and the chip area and the actual power consumption are continuously increased, the effect sensitivity of various failure mechanisms affecting the reliability of the VLSI is enhanced by the approximation of physical limits, the factors needing to be considered and balanced in design and process are greatly increased, and the residual reliability tolerance tends to disappear, so that the guarantee and improvement of the reliability of the VLSI face a great challenge.
Referring to fig. 2, the larger the scale of a large-scale integrated circuit, the more obvious the channel routing problem, and the solution based on the i Xin Ji quantum annealing can face the very large-scale integrated (VLSI) circuit channel routing issue. The current industry is very important to the industry where wafer fabrication and chip design are separated in most cases, i.e., the industry of fab/fabless, how wafer manufacturers flexibly configure the channel routing of various types of dies, because not only the different process nodes but also the channel routing needed by the circuits are different for different chip design companies. The present application provides this flexibility. The related various reliability technologies are purposefully and quantitatively comprehensively applied to the research and development and production processes of the circuit channel wiring, and a large-scale integrated circuit quality and reliability guarantee system is constructed from the aspects of technology and management so as to meet the increasingly higher requirements of users on reducing the channel wiring failure rate and improving the reliability level. The channel routing addressed by graph coloring can meet this need.
Referring to FIG. 3, in the illustrative example of a connection edge, (1, 2) may be used to represent the connection edge from node 1 to node 2 and the weight W on that edge 12 =s (1, 2); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net1 and the connection net2 in fig. 3, the nodes (1, 2) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of a connection edge, (2, 3) may be used to represent the connection edge from node 2 to node 3 and the weight W on that edge 23 =s (2, 3); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net2 and the connection net3 in fig. 3, the nodes (2, 3) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of the connecting edges, (3, 4) may be used to represent the connecting edge pointing from node 3 to node 4 and thisWeight on edge W 34 =s (3, 4); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net3 and the connection net4 in fig. 3, the nodes (3, 4) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of a connection edge, the connection edge pointing from node 4 to node 5 and the weight W on that edge may be represented by (4, 5) 45 =s (4, 5); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net4 and the connection net5 in fig. 3, the nodes (4, 5) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of a connection edge, the connection edge pointing from node 5 to node 2 and the weight W on that edge may be represented by (5, 2) 52 =s (5, 2); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net5 and the connection net2 in fig. 3, the nodes (5, 2) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of a connection edge, (5, 3) may be used to represent the connection edge from node 5 to node 3 and the weight W on that edge 53 =s (5, 3); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net5 and the connection net3 in fig. 3, the nodes (5, 3) corresponding to the two connection lines are connected by an edge (edge).
Referring to FIG. 3, in the illustrative example of a connection edge, the connection edge pointing from node 4 to node 2 and the weight W on that edge may be represented by (4, 2) 42 =s (4, 2); corresponding to the overlapping relationship of the horizontal line segments in the same track between the connection net4 and the connection net2 in fig. 3, the nodes (4, 2) corresponding to the two connection lines are connected by an edge (edge).
Referring to fig. 3, there is no overlap or connecting edge between the connection net1 and the connection net 5. The vertex represented by the connection net1 and the vertex represented by the connection net5 are nodes (1, 5), respectively, and the nodes (5, 1) are not connected by any edge (edge).
Referring to fig. 3, solving the coloring problem of the horizontal constraint graph HCG with the least color variety is equivalent to the channel routing problem using the least track. Each connection (net) corresponds to one node of the horizontal constraint graph HCG, and if the connection corresponding to two nodes (nodes) cannot be placed in the same track, the two nodes are connected by one edge, so that the equivalent expression that the two connections cannot be placed in the same track and the nodes corresponding to the two ends of each edge cannot be same color is considered to be sure in the application, and the equivalent expression that the connection distribution track is equivalent to the equivalent expression that the color is distributed to each node of the HCG; further, "wiring scheme using minimum track" is equivalent to "HCG coloring scheme using minimum color category". This is a unique design of the present application.
Referring to fig. 3, the various vertices in the graph may be colored using different colors.
Referring to fig. 3, based on the teachings herein, the subject matter relates to quantum computing or quantum processing that allows for operations to be performed on a quantum device, the hamiltonian amount of which is designed to meet at least the following objectives: the I Xin Hami ton number operation comprises various annealing and evolution processes such as quantum annealing or simulated annealing.
Referring to fig. 3, the customary integrated i Xin Hami ton amount can be described as:
wherein J ij Representing the ith spin x in I Xin Hami ton i And the j-th spin x j Is used for the coupling strength of the optical fiber.
Results of each spin x i Consisting of binary values-1 and 1, the objective of solving the problem of isooctane is to minimize the amount of I Xin Hami and obtain x under the condition of minimum Hamiltonian i The corresponding value 1 or-1.
As relevant herein to quantum, the relevant content for quantum devices and quantum data is as follows:
the term "quantum device" as used herein includes known quantum computing devices, quantum chips, etc., and may also be used in place of quantum devices using quantum hardware. Typical "quantum devices" include, but are not limited to: quantum computers, quantum information processing systems or quantum cryptography systems, quantum simulators, all kinds of devices, apparatuses and machines that process quantum data.
As used herein, "quantum data" includes information or data carried, stored or otherwise stored by a quantum system, the smallest nontrivial system being a qubit, i.e., a system that defines a quantum information unit. It should be understood that the term "qubit" includes all quantum systems that in the respective context may be suitably approximated as two-level systems. Such quantum systems typically include, for example, typical atoms, electrons, photons, ions, or superconducting qubits, among others.
Referring to fig. 3, an i Xin Hami ton amount is constructed for the coloring scheme that minimizes the color of the horizontal constraint map HCG, for example, using a binary search method. Let HCG middle degree (degree) be the maximum Δ, attention degree is a concept of graph theory, which indicates how many edges (edges) are connected to one node (node) in the graph, i.e., each node has its own degree. Then the easy value must be smoothly colored with delta +1 colors. So that the binary search method or the equivalent search method can be used for iteration continuously in the range of 2-M-delta+1, and the target value which meets the conditions that M colors can be colored and M-1 colors cannot be colored can be found. The number of colors represented by M is a positive integer. Degree of vertex or node: the degree of a vertex refers to the number of edges connected to that vertex or node, and there must be a maximum degree for all nodes, e.g., the number of edges connected to the node or vertex with the greatest degree is the largest of all vertices.
Referring to fig. 3, an alternative iteration rule is as follows: the initial value interval is 2-M-delta+1, and then M is taken 0 Solving M for interval midpoint and using I Xin Ji 0 Whether the coloring problem of the seed color is solved, if so, updating the interval to be M which is more than or equal to 2 and less than or equal to M 0 Updating the interval to M without solution 0 M is more than or equal to M and less than or equal to delta+1, and the midpoint of the interval is taken as M again in the new interval 1 The method comprises the steps of carrying out a first treatment on the surface of the Simultaneous solution of M with I Xin Ji 1 Whether the coloring problem of the seed color is solved, and updating the interval to be 2-M and M according to the same principle 1 Updating the interval to M without solution 1 M.ltoreq.delta.1 and between new regionsTaking the middle point of the interval again as M 2 The method comprises the steps of carrying out a first treatment on the surface of the Simultaneous solution of M with I Xin Ji 2 If the coloring problem of the color is solved, the interval is updated again, … … is iterated continuously, the interval is updated continuously until M is found to meet the requirement that M colors can be colored, and M-1 colors cannot be colored. The mid-point of the interval is the sum of the upper and lower limits of the interval added and divided by 2, e.g. M 1 ＝(M 0 +Δ+1)/2 and M 2 ＝(M 1 +Δ+1)/2。
Referring to FIG. 3, the kth iteration M k The coloring problem of the one color requires that the i Xin Hami ton be so constructed. Let node number in the graph be N first, take binary variable x v,i Subscript value range: v=1, 2, …, N, i=1, 2, …, M k If it satisfies the value relationship x v,i The expression =1 then means that the v node is colored with the i-th color, since a node can only be colored with one color, there is the following constraint 1:one penalty function corresponding to the i Xin Hami ton:
the penalty function means that if the constraint is violated, the value of the penalty function increases, such as here if the color bit x of the v-th node v,i ＝x v,j =1, corresponding to a dot of two colors, i Xin Hami tons increases the energy of a and a can be defined as a first predetermined coefficient term. Whereas i Xin Ji is characterized in terms of physical evolution by finding and stabilizing in the lowest energy ground state. The penalty function in hamiltonian is at least guaranteed that the machine will not evolve to a condition or result that violates the constraint. Note that k and N are both positive integers.
Referring to fig. 3, there is also constraint 2, namely the coloring rule, that the colors of the nodes at both ends of each edge must not be identical and this requires a second penalty function, corresponding to constraint 2:
constraint 2 means that if the nodes at both ends of an edge are the same color, this will bring the energy up of B to the i Xin Hami ton and B can be defined here as a first predetermined coefficient term. This term (constraint 2) exists to avoid this violation of the coloring rules in the evolution of ife Xin Ji.
Referring to fig. 3, the final i Xin Hami ton:
requirements A in I Xin Hami ton>B>0 because constraint 1 is required to be more stringent than constraint 2. If the result of the quantum annealing is H ising The case where =0 describes that there is a solution, if H ising >0 indicates no solution at this time. Note that if the coefficient of the ton of i Xin Hami is simultaneously enlarged or reduced by several times, the ground state of the ton of i Xin Hami is unchanged, so that the specific value of A, B may not be particularly limited as long as a is satisfied>B>0, flexible selection is possible.
Referring to FIG. 3, after all iterations are completed, the last { x }, is output v,i Telling each node what color is colored and how several colors are used together, i.e. the least needed color.
Referring to fig. 3, the graph neural network g= (V, E) is a definition method of a set theory, and the meaning of expression can be summarized as that the graph is a set of vertices and edges. V is the Vertex (Vertex) and E is the Edge (Edge). Other expressions of interferograms in this application are graph neural networks, so interferograms belong to graph neural networks.
As related herein to quantum, the relevant content regarding quantum machinery and quantum data is as follows:
the term "quantum machine" as used herein includes known quantum computing devices, quantum chips, etc., and may also be used in place of quantum devices using quantum hardware. Typical "quantum machines" include, but are not limited to: quantum computers, quantum information processing systems or quantum cryptography systems, quantum simulators, all kinds of devices, apparatuses and machines that process quantum data.
Commercial applications for quantum annealing, most typically quantum annealers, such as a quantum computer specialty company D-Wave, canada. The quantum computer principle sold by D-Wave commercial is that tiny current rings made of metal niobium are used for forming quantum bits, so that the quantum annealing phenomenon is realized, and the effect of storing a large number of values of bit data in quantum computing can be simulated.
Notably, on the ground of commercial applications, quantum annealing can effectively solve the optimization problem by searching for various possibilities using the superposition state, effectively meeting the current effectiveness and acceleration requirements for practical working schemes.
So far, quantum annealing has constructed a number of early applications in various fields of logistics, artificial intelligence, material science, drug discovery, network security and fault detection, and financial modeling. The annealing algorithm commonly used at present is divided into two types, namely simulated annealing and quantum annealing, and quantum annealing is more superior.
Annealing is essentially a metal heat treatment process in which the metal is slowly heated to a temperature and held for a sufficient time and then cooled at a suitable rate. For example, after ion implantation, an annealing process is required because, when impurity ions are implanted into a semiconductor, high energy incident ions collide with atoms on the semiconductor lattice to displace the lattice atoms and anneal the lattice atoms to restore the crystal structure and eliminate defects. The actual annealing solves the problem of unstable hardware process in the development process of the material, and the simulated annealing and quantum annealing solve the problem of non-optimal solution of mathematical calculation such as combination optimization.
Quantum annealing is a form of Adiabatic Quantum Computing (AQC). Informally, the adiabatic theorem states that if a quantum mechanical system starts from a certain hamiltonian ground state and the speed of changing the hamiltonian is slow enough, the system will end up with the final hamiltonian ground state. If the initial hamiltonian is set to a hamiltonian having a known ground state, and the final hamiltonian is set to a problem hamiltonian, the ground state represents a solution to the optimization problem for which a solution is desired, and a calculation using this theorem can obtain a desired result. The annealing time scale (the expected time required for a single run to reach the solution) is defined by the inverse of the minimum energy gap between the ground state and the first excited state encountered during adiabatic evolution.
Referring to fig. 3, various steps, flowcharts, and diagrams of fig. 1-2 are described in greater detail.
According to the channel and the internal connection, a horizontal constraint graph (horizontal constraint graph) is constructed, see contents such as schematic diagram 1 and schematic diagram 2, each connection line (net) in the channel is regarded as a node (node/vertex) of a graph, so that 5 lines correspond to 5 nodes, if two connection lines are placed in the same track, the respective horizontal line segments can overlap, which means that the two connection lines cannot be placed in the same track, and the nodes corresponding to the two connection lines are connected by one edge (edge) and finally form an HCG such as the schematic diagram 2. This is the first step.
The channel wiring problem CRP is mathematically equivalent to coloring with the least color type HCG, wherein the initial value interval of the color type number is 2.ltoreq.M.ltoreq.delta+1, and the midpoint M is taken in the first iteration 0 = (2+Δ+1)/2 constructs the corresponding Xin Hami ton of i-ray for this graph coloring problem, which is the second step:
in a preferred embodiment, a mathematical calculation is allowed to be performed to reduce the Xin Hami ton of i.e. to a standard form of the Xin Hami ton of i.e. H ising ＝-∑ i<j J ij s i s j -∑ i h i s i Parameter J in standard form ij And h i And inputting I Xin Ji, and starting quantum annealing evolution. This is the third step.
Referring to fig. 3, nodes V, u and connecting edges (uv), weights of edges, and the like together construct a directed graph g= (V, E). For example, it can be assumed that the graph g= (V, E) has N totalNodes, V represents the set of all nodes, and E represents the set of all connecting edges. Again as commonly available (uv) represents the directed edge pointing from node u to node v, the weight of the edge W uv ＝S(u,v)。
The simplified I Xin Hami ton amount is obtained as an I Xin Hami ton amount in a standard form, and after evolution is finished, the new value interval is updated according to whether a solution exists or not. This is the fourth step. The content of the quantum annealing has been described in detail in the foregoing, for example, the ground state of the i Xin Hami ton metric represents a solution to the optimization problem that is desired to be solved, and the i Xin Hami ton metric calculation is performed based on this theorem to obtain the desired result. Updating the interval as follows:
2≤M≤M 0
and updating the interval as follows if the result of the quantum annealing is not solved:
M 0 ≤M≤Δ+1
referring to fig. 3, in combination with the contents of fig. 1, the midpoint M is again taken at a new interval 1 Repeating the second to fourth steps and continuously circularly updating the interval to obtain a midpoint M 2 、M 3 Until after a number of iterations, until the interval is small enough to enable one M to be found, M colors can be colored, while M-1 colors cannot be colored. M is the minimum number of color types needed, and is also the minimum track number needed for channel wiring, and M color coloring solutions { x } v,i The solution of the channel routing problem. The step S15 of finally obtaining the solution can obtain a ground state solution.
Referring to fig. 3, the channel routing problem can be solved by the above steps using the i Xin Ji quantum annealing. For example, the condition that "M colors are coloring of each node, M-1 colors cannot complete coloring of each node" is satisfied, and the condition that "M colors are coloring of each node, M-1 colors cannot complete coloring of each node" is not satisfied. More strictly speaking, "if the result of quantum annealing is H ising When=0, there is a solution, if H ising >0 then there is no solution).
Referring to FIG. 3, the kth iteration M k The coloring problem of the one color requires that the i Xin Hami ton be so constructed. Let the node number in the graph be N, overlapAfter k generations, i=1, 2, …, M k At M k And obtaining a ground state solution under the condition. Notably, quantum annealing and simulated annealing of the ton of i Xin Hami are alternatives.
Referring to fig. 3, a channel routing problem solution based on the i Xin Ji quantum anneal. This scheme is used for distributing the wires to each horizontal track (track) given a channel and a channel internal wire (net), and requires that horizontal line segment parts of different wires in the same track (track) are non-overlapping, i.e. horizontally constrained. The objective is to solve how to allocate so as to minimize the number of track tracks used, and the scheme comprises the following steps in connection with fig. 1.
S10, constructing a horizontal constraint map (horizontal constraint graph) according to the channel and the internal connection line of the channel.
S11, the channel routing problem CRP is mathematically equivalent to "coloring with the least color class being HCG", making the degree (degree) of the nodes in the horizontal constraint graph maximum Δ, it is easy to know that Δ+1 colors must be able to color HCG, which is equivalent to giving such an interval: m is more than or equal to 2 and less than or equal to delta+1; m is found in this interval so that M colors can be colored and so that M-1 colors cannot be colored. Preferably with the middle point of the interval being M 0 Construction of M 0 The graph coloring problem of the color corresponds to the i Xin Hami ton.
S12, mathematically calculating the simplified I Xin Hami ton to obtain the standard type I Xin Hami ton, and inputting the standard type parameter into the I Xin Ji to start quantum annealing evolution.
S13, outputting and judging whether a solution exists or not by the I Xin Ji after evolution: if the solution exists, the interval is updated to be 2-M and M 0 Updating the interval to M without solution 0 ≤M≤Δ+1。
S14, an iteration process: taking the midpoint of the interval as M 1 Returning to S11 to construct M 1 And repeating S11-S13 according to the corresponding I Xin Hami ton amount of the graph coloring problem of the seed color. The process is iterated continuously, which is equivalent to a binary search process, the interval range is continuously narrowed until M is found, the M colors can be colored, and the M-1 colors cannot be colored. The M colors are the minimum required colors, whichThe output of i Xin Ji is a coloring scheme of M colors.
Referring to fig. 1, the scheme disclosed herein is characterized by using an i Xin Ji quantum anneal to solve the problem of channel routing optimization in integrated circuit design, rather than using conventional genetic algorithms, ant colony algorithms, etc., and an i Xin Ji quantum anneal is more efficient with large circuit scale and many wires. And the present solution is applicable to a variety of different physical system implementations of i Xin Ji, such as i Xin Ji, regardless of the particular implementation of the scheme, which may be mapped onto without obstruction. Specific implementations of i Xin Ji include light quanta i Xin Ji and electrical i Xin Ji, superconductivity, ion trap i Xin Ji, and the like. Other names of additional wiring in the chip design section include metal interconnect lines or wires, and the like. The important function of the wiring is to couple and connect different channels with electrical connection relation.
The foregoing description and drawings set forth exemplary embodiments of the specific structure of the embodiments, and the above disclosure presents presently preferred embodiments, but is not intended to be limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (9)
1. A method of routing a very large scale integrated circuit channel, comprising:
establishing a horizontal constraint graph of the connection according to the connection condition of a given channel, wherein the horizontal constraint graph is used for constructing an I Xin Hami ton amount in a graph coloring mode, and distributing the connection to different horizontal trend tracks according to the annealing evolution result of the I Xin Hami ton amount, and the method for establishing the horizontal constraint graph comprises the following steps: and taking each connecting line as a node, and connecting the nodes corresponding to the two connecting lines by using one edge if the two connecting lines arranged in the same wiring track are overlapped.
2. The method according to claim 1, characterized in that:
on the premise of defining that horizontal line segments of different connecting lines on the same wiring track are not overlapped, the number of the wiring tracks is minimized according to annealing evolution results.
3. The method according to claim 1, characterized in that:
searching the numerical value of M in the graph coloring mode, and coloring each node of the graph by using M colors as horizontal constraint, wherein M colors are required to be colored for each node, but M-1 colors cannot be used for coloring each node: the M colors are defined at this time as the minimum color category required and equivalent to the number of track traces with the minimum number of track traces.
4. A method according to claim 3, characterized in that:
the maximum degree of the nodes in the horizontal constraint graph is delta, M is found in the range of the initial value interval 2 which is more than or equal to M and less than or equal to delta+1 of the color category number, and the initial midpoint of the interval is M 0 ＝(2+Δ+1)/2。
5. The method according to claim 4, wherein:
if the annealing evolution of the I Xin Hami ton quantity has a solution, updating to obtain a new value interval of the color category number and updating the interval to be 2-M 0 。
6. The method according to claim 4, wherein:
if the annealing evolution of the I Xin Hami ton quantity is not solved, updating to obtain a new value interval of the color category number and updating the interval to M 0 ≤M≤Δ+1。
7. The method according to claim 6, wherein:
through k timesIterating to obtain a new interval M k-1 M is more than or equal to delta+1, wherein M is more than or equal to k-1 Is the midpoint of the new interval obtained from the k-1 th iteration.
8. The method according to claim 7, wherein:
midpoint M of the new interval of the kth iteration k ＝(M k-1 +delta+1)/2, each iteration solving M by the annealing evolution of the I Xin Hami ton quantity k Whether the coloring problem of the colors is solved or not, and iterating for a plurality of times until a situation that M colors can be colored for each node, but M-1 colors cannot be colored for each node is found.
9. A method for routing a very large scale integrated circuit channel, comprising the steps of:
s10, constructing a horizontal constraint graph according to the connecting lines of the channels;
s11, constructing an I Xin Hami ton amount by a value interval of the color category number corresponding to the node in the horizontal constraint graph;
s12, annealing evolution is carried out on the I Xin Hami ton quantity;
s13, judging whether the annealing evolution result has a solution, if not, executing the step S14, otherwise, executing the step S15;
s14, iterating out a new value interval, and repeatedly executing the steps S11-S13;
s15, finding out the minimum color types required by the coloring of the graph, and minimizing the number of the wiring tracks according to the minimum color types on the premise that horizontal line segments of different connecting lines on the same wiring track are not overlapped.
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