CN114970440A - Wiring method for VLSI channel - Google Patents
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Abstract
The invention relates to a wiring method of a very large scale integrated circuit channel. A brand-new and efficient Italian quantum annealing solution is provided for the problem of channel wiring. The problem of channel wiring of the integrated circuit can be equivalent to a graph coloring problem for searching the minimum color category in the application, the graph coloring problem can be efficiently solved by using an Itanium machine quantum annealing, and based on the thought, a scheme for solving the channel wiring problem by using the Itanium machine is provided.
Description
Technical Field
The invention relates to the technical field of integrated circuit design and manufacture, in particular to a wiring method of a very large scale integrated circuit channel.
Background
In the integrated circuit design, an integrated circuit layout is designed by an Electronic Design Automation (EDA) tool, delivered to an integrated circuit manufacturer, and transferred onto a wafer through a series of manufacturing processes such as circuit mask preparation, oxidation, doping, photoetching and the like, so that the circuit integration function is realized. For digital circuit design, the layout design process comprises the steps of behavioral level synthesis, logic synthesis, physical design, layout optimization and the like. The physical design is the most time-consuming step which has the greatest influence on the performance of the chip, and the physical design is divided into the steps of layout planning, layout, clock tree synthesis, wiring and the like, and channel wiring refers to the stage of distributing wiring channels in wiring unit rows before detailed wiring after overall wiring determines the topological structure of a wire net and the distribution of wiring layers in the wiring process. The good channel wiring can not only accelerate the convergence of the detailed wiring, but also optimize the length of the chip wiring.
In engineering applications where reliability techniques are throughout various stages and aspects of VLSI demand analysis, product design, manufacturing processes, test inspection, and application processes, the development of conventional electronics and aerospace technologies has placed increasingly higher reliability demands on VLSI and has driven the continued development of VLSI reliability techniques. The reliability of the VLSI is ensured by controlling the reliability of the final product mainly through reliability test and screening in the past, the coordination of strengthening the process control, strengthening the reliability design and the function design is turned to, when the process capability and the function design are considered, a countermeasure is provided aiming at a main failure mechanism, and the reliability index and the cost of the VLSI in the whole life cycle and under specific environmental conditions are comprehensively balanced, so that a proper reliability technology balance mechanism is introduced in the links of circuit design, structural design and layout, material selection, process flow and parameter selection, process control, design verification and evaluation, product reliability test evaluation and screening and the like, and the reliability level of the product is ensured and improved.
In chip manufacturing, node development of mainstream ultraviolet lithography line widths such as 65nm/45nm and 28nm/22nm and the number of transistors that can be accommodated on a chip increases due to the reduction of feature size, and the scale and complexity of circuit design are also increasing, which makes the conventional wiring tool have to have the capability of dealing with larger scale and complex problems.
Further, at the manufacturing process node where the width of the lithography line is, for example, 65nm and below, the time delay on the metal interconnection line accounts for more than seventy percent of the time delay of the whole circuit, and the problem of crosstalk between the interconnection lines becomes an important factor influencing the time delay performance of the chip. Therefore, conventional routing tools must strictly consider cross-talk optimization when dealing with the circuit design of these manufacturing processes. As integrated circuit fabrication processes continue to increase and feature sizes decrease rapidly, the number of transistors that can be housed on a chip increases accordingly, and circuit design complexity also continues to increase.
In a conventional channel wiring method based on linear distribution, for example, each section of wiring after global wiring is divided into a series of continuous unit wirings, the unit wirings are distributed one by one and then merged, and the unit wirings with the same channel number are distributed each time, so that the obtained local reasonable design may slow or even not converge subsequent detailed wiring. The application provides a better solution to the wiring related problems of the VLSI channel.
Disclosure of Invention
The application discloses a wiring method of a very large scale integrated circuit channel, which comprises the following steps:
and establishing a horizontal constraint map of the connection according to the connection condition of a given channel, wherein the horizontal constraint map is used for constructing the Iloctyl Hamiltonian, and the connection is distributed to different horizontal trend orbits according to the annealing evolution result of the Iloctyl Hamiltonian.
The method described above, wherein:
on the premise of limiting that the horizontal line segments of different connecting lines on the same routing track are not overlapped, the number of the routing tracks is minimum according to an annealing evolution result.
The method described above, wherein:
the mode for establishing the horizontal constraint graph comprises the following steps: and taking each connecting line as a node, and if two connecting lines arranged in the same routing track are overlapped, connecting the nodes corresponding to the two connecting lines by using one edge.
The method described above, wherein:
finding the numerical value of M in a graph coloring mode and coloring each node of the horizontal constraint graph by using M colors, and meanwhile, requiring that the M colors can color each node but M-1 colors cannot finish coloring each node: the M colors are then defined as the minimum color type required and equivalent to the number of trace tracks with the minimum number of trace tracks.
The method described above, wherein:
the maximum degree of the nodes in the horizontal constraint graph is delta, M is searched in the range that the initial value interval of the color category number is more than or equal to 2 and less than or equal to delta +1, and the initial midpoint of the interval is M 0 ＝(2+Δ+1)/2。
The method described above, wherein:
if the annealing evolution of the Itani Hamilton quantity has a solution, updating to obtain a value interval of a new color variety number and updating the interval to be more than or equal to 2 and less than or equal to M 0 。
The method described above, wherein:
if the annealing evolution of the Itani Hamiltonian is not solved, updating to obtain a value interval of a new color variety number and updating the interval to M 0 ≤M≤Δ+1。
The method described above, wherein:
obtaining a new interval M over k iterations k-1 M is not less than M and not more than delta +1, wherein M k-1 Is the midpoint of the new interval obtained from the (k-1) th iteration.
The method described above, wherein:
midpoint M of new interval of kth iteration k ＝(M k-1 + Δ +1)/2, each iteration solving for M by the annealing evolution of the Exin Hamiltonian k And (4) judging whether the coloring problem of the colors has a solution or not, and repeating the iteration for a plurality of times until the condition that M colors can color each node but M-1 colors cannot finish coloring each node is found.
The application discloses another wiring method of a very large scale integrated circuit channel, which comprises the following steps:
s10, constructing a horizontal constraint graph according to the channels and the connecting lines of the channels;
s11, constructing an Exihamilton according to the value interval of the color variety number corresponding to the node in the horizontal constraint graph;
s12, annealing evolution is carried out on the Iloctyl Hamiltonian;
s13, judging whether the annealing evolution result has a solution, if not, executing a step S14, otherwise, executing a step S15;
s14, iterating a new value interval, and repeatedly executing the steps S11-S13;
s15, finding out the minimum color type required by graph coloring, and on the premise that the horizontal line segments of different connecting lines on the same trace track are not overlapped, minimizing the number of trace tracks according to the minimum color type.
The channel wiring problem is a sub-problem of the wiring of the integrated circuit, and belongs to the field of integrated circuit design. The Italian quantum annealing method in the quantum physics leading edge field is applied to the wiring of the integrated circuit.
Regarding the Channel Routing Problem (CRP), given a channel and a channel interconnection (net), the interconnection is allocated to each horizontal track (track), requiring that the horizontal segments of different interconnections within the same track (track) are partially non-overlapping (this constraint is called horizontal constraint). The problem of solving how to allocate to minimize the number of track tracks (tracks) used is mathematically equivalent to a similar graph coloring problem requiring minimal color variety.
With respect to the graph coloring problem, given an undirected graph, given n colors, it is required to color each node in the graph and the coloring rules require that the colors of the nodes at both ends of each edge necessarily differ. The problem of how much minimum of colors are needed to color a graph and how it is, is a NP-complete problem (Non-deterministic polymeric).
The Esin machine refers to a physical system constructed and the Hamiltonian H of the Esin machine ising Has the following form:
in Hamiltonian s i And s j Is an ising spin: the value is +/-1. The final result of the evolution of the IlCinciator quantum annealing corresponds to a solution to the graph coloring problem, provided that the corresponding IlCinciator Hamiltonian is constructed for the graph coloring problem and various constraints and various optimization objectives are embodied in the IlCinciator Hamiltonian. The graph coloring assignment problem can then be solved efficiently using an yincin machine.
While solutions such as genetic algorithms and ant colony algorithms have been developed for such wiring problems, these algorithms often do not work well in the face of large-scale (meaning many connections in a channel) wiring situations. The channel wiring problem of the integrated circuit can be equivalent to a graph coloring problem for searching the minimum color category, and the graph coloring problem can be efficiently solved by using an Itanium quantum annealing, and based on the thought, the application provides a scheme for solving the channel wiring problem by using the Itanium machine: the method can be applied to the Channel Routing Problem (CRP) in the field of very large scale integrated circuit routing.
The channel wiring problem is a sub-problem of the wiring of the integrated circuit, and belongs to the field of integrated circuit design. The Italian quantum annealing method in the quantum physics leading edge field can be applied to integrated circuit wiring.
Drawings
In order that the above objects, features and advantages will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to the appended drawings, which are illustrated in the appended drawings.
FIG. 1 is an alternative exemplary diagram for converting a via routing problem of an integrated circuit into a map coloring problem.
FIG. 2 is an example of each line in a channel as a graph node, such as five lines corresponding to five nodes.
FIG. 3 is a diagram construction diagram of EsinoHamiltonian quantities corresponding to a graph coloring problem for constructing multiple colors.
Detailed Description
The present invention will be described more fully hereinafter with reference to the accompanying examples, which are intended to illustrate and not to limit the invention, but those skilled in the art, on the basis of which they may obtain without inventive faculty, without departing from the scope of the invention.
Referring to FIG. 1, the present application is directed in context to a Very Large Scale Integration (VLSI) circuit channel routing problem solution based on Isning machine quantum annealing. The term via in the integrated circuit industry refers to, for example, a lateral routing area with top and bottom regions that are populated with tiles or areas that need to be connected, requiring metal lines to connect the corresponding pins or areas together. Integrated circuit designs consist of a chrome plating stage, where the important design stages are physical design such as placing devices in place and making electrical connections with metal wire connectors, where the latter is called routing and it is a problem that electronic design automation EDA tools need to solve. A channel is a term of art referred to in the context of this application at the routing design stage.
Referring to FIG. 1, a solution to the channel wiring problem for the Itanium quantum annealing is shown as steps S10-S15. This solution, for example given a channel and a channel internal connection (net), is a chip-related link, distributing the connection to each horizontal track (track), requiring that horizontal segments of different connections within the same track (track) are partially non-overlapping (this type of constraint is called horizontal constraint). In the transistor metal interconnection layer of the chip, if the traces are overlapped or touched or overlapped or contacted in the same horizontal plane, short (short) and other unexpected situations can be caused, so that the horizontal line segments of different connecting lines on the same trace track can not be overlapped or crossed.
Referring to fig. 1, a horizontal constraint map is constructed from channels and their connecting lines. One of the objectives is to solve how to allocate to minimize the number of tracks (tracks) used, and the main solution includes the following points (steps), which will be described in detail below.
Referring to fig. 1, a horizontal constraint map (HCG) is constructed according to the channels and their interconnects at the first point of relation that minimizes the number of track tracks (tracks) used, and the specific construction process can be seen in the relevant explanation part of the following description. The first point is embodied in step S10.
Referring to fig. 1, the second point of interest, which minimizes the number of track tracks (tracks) used, the channel routing problem CRP is mathematically equivalent to "coloring HCG with the least number of color types", making the number of nodes (tree) in HCG the largest Δ so easy to know that Δ +1 colors must be possible to color HCG, and certain conditions are satisfied in the following intervals:
2≤M≤Δ+1
for example, M is sought within the interval so that M colors can be colored while M-1 colors cannot. If the middle point of the interval is M 0 Construction of M 0 The plot coloring problem for a color corresponds to the quantity of EsinoHamilton. The second point of the isooctane hamilton problem is embodied in step S11: determining the type of color from the value-taking interval according to the horizontal constraint mapTo construct a reasonable Esinhamiltonian H ising 。
Referring to fig. 1, a third point of correlation that minimizes the number of track tracks (tracks) used, a mathematical calculation reduces the yinxhamiltonian to obtain a standard form yinxhamiltonian, inputs the standard form parameters into an yinxin machine and performs a quantum annealing evolution, and the third point is embodied in step S12.
Referring to fig. 1, after the evolution is finished, a fourth point related to the minimum number of used track tracks (tracks) is judged whether a solution exists according to the output of the yixinji, and if the solution exists, the interval is updated to be:
2≤M≤M 0
in the opposite case, the interval is updated without solution as:
M 0 ≤M≤Δ+1
the fourth step of determining whether or not there is a solution is embodied in step S13: when the annealing is finished, the yixin machine outputs the result and judges whether a solution exists according to the annealing result, and then the step S14 can call back the situation of the interval or jump to the step S15. The figure shows the main contents of step S14: for example, the value range is updated according to the output result of the last round of the yixinji. The figure shows the main contents of step S15: if the value-taking interval is small enough after the step S13, the minimum color category required for coloring can be found, the output can be ended at this time, and the output result is the solution of the channel wiring problem.
The preferred option for the solution is to take the midpoint of the interval as M 1 Returning to step S11, M is constructed 1 And E, according to the quantity of the Ithachi corresponding to the color chart coloring problem of the variety of colors, and then the steps S11-S12-S13 are repeated. After the first round of the cycle, it is still possible to go back to repeat the steps S11-S12-S13 after performing the step S14 if necessary, i.e., the second round of the cycle. It is still possible to go back to repeat steps S11-S12-S13, i.e., the third cycle, after performing step S14 if necessary. The process can be iterated continuously, which is equivalent to a binary search process, the range of the interval is reduced continuously until M is found, and the condition that M colors can be colored and M-1 colors cannot be colored is met. M colors are the minimum color types required, in this case of YixinjiThe output is: i.e., a scheme of coloring of M colors.
Referring to fig. 2, regarding the horizontal constraint graph HCG construction: firstly, each connecting line (net) in the channel is taken as a node (node or vertex) of a graph, if two connecting lines are placed in the same routing track (track), respective horizontal line segments can be overlapped (which means that the two connecting lines cannot be placed in the same track), and the nodes corresponding to the two connecting lines can be connected by using a single edge (edge) or an edge. Thereby constructing a horizontal constraint graph HCG.
Referring to fig. 2, a graph (graph) does not refer to a graphic image (image) or a map (map). Generally speaking, the industry views a graph as an abstract network of "vertices," where the vertices in the network can be connected to each other by "edges" and represent that two vertices are related. Note the two keywords in the graph definition here, thus we get the two concepts we are most basic, namely vertex (vertex) and edge (edge). The above are the most central items of the graph theory. Therefore, in the present application, the drawings refer to drawings in the Graph theory (Graph theory) field, and the concepts such as the horizontal constraint drawings and the like are naturally also included in the drawings in the Graph theory field. A graph consists of vertices, nodes, or points/vertices connected by edges, arcs, or lines.
Referring to fig. 2, a vertex describes something or an object. Since the terminology of the graph is not standardized, it may be said that vertices are points or nodes or endpoints, etc. The same applies to the term vertex as referred to in the context of the application.
Referring to fig. 2, edges represent objects and relationships between objects. Edges represent the logical relationship between vertices.
Referring to FIG. 2, a Directed/Undirected Graph (Directed Graph/Undirected Graph). The most basic graph is usually defined as an undirected graph and the corresponding one is called a directed graph. The difference is that the edges in the directed graph are directional.
Referring to fig. 2, the weight (weight) is a weight, a cost, and a length, and each edge has a corresponding value. For example, when a vertex represents some physical location or the like, the weight of an edge between two vertices may be set as the distance in the road network. Sometimes to cope with special cases, the weight of an edge may be zero or a negative number.
Referring to fig. 2, regarding the horizontal constraint graph HCG construction: each line (net1-net12, etc.) in a channel is regarded as a node (node or vertex) of a graph, and if two lines are placed in the same track (track), respective horizontal segments of the two lines overlap (which means that the two lines, such as net1/net2, cannot be placed in the same track), and a node corresponding to the two lines in the graph can be connected by an edge (edge). Similarly, there is also an edge (edge) connection between net2 and a node corresponding to the two-by-two connection between net3-net 4. As an opposite example, the connection lines of net1-net2 and net5 are not overlapped when placed in the same track. Thereby constructing a horizontal constraint map. Of course, the actual design of an integrated circuit has many more channels and connections than the example shown in the figure.
Referring to fig. 3, a horizontal constraint graph of the links is established based on the link conditions (see fig. 2) for a given channel.
Referring to FIG. 2, a graph (graph) is a strong framework in data structure and algorithms. The map can be used to represent almost all types of structures or systems, and has wide application from the fields of traffic network to communication network, chess game to optimal process solution, task distribution to interpersonal interaction network and the like. With respect to the world of graph theory, a clear, accurate basic concept is a necessary premise and foundation. The concept of the graph theory is remarkable, and the vertex and the edge are the most core contents of the graph theory.
Referring to fig. 2, the development of quantum computers is gradually mature and scaled at present, for example, a simulation system with a quantum computing function is constructed based on a traditional computer, and a development approach and a tool of a quantum algorithm are provided. The existing quantum simulation system is mainly deployed on a supercomputer and a cloud computing platform, and the quantum computer has exponential computing acceleration compared with the traditional computer. A mode based on Itanium quantum annealing is sought, which not only realizes Itanium problem solving, but also considers the channel wiring problem.
Referring to fig. 3, the connecting edge (uv) assigns a weight W uv S (u, V) is as in graph neural network G (V, E). The vertexes or points or nodes or endpoints in the graph represent connecting lines in the circuit channels,And the connecting edges (belonging to edge) represent the connection relationship and the weight relationship between the vertexes. The wires are also called routing wires, and the difference between the wires and the edges of the graph is noted.
Referring to fig. 2, since the integration of very large scale integrated circuits has increased dramatically at a rate doubling every 18 months following moore's law, the number of integrated circuit elements on a chip is now well in excess of one hundred million, the trend is moving the role of very large scale integrated circuits in electronic devices from device chips to System On Chip (SOC), meanwhile, the process characteristic dimension of deep submicron large scale integrated circuit reaches below a few nanometers, under the conditions of continuously reduced feature size and continuously increased integration level, chip area and actual power consumption, the approaching of physical limits enhances the sensitivity of various failure mechanism effects affecting the reliability of VLSI, the factors to be considered and balanced in design and process are greatly increased, and the residual reliability tolerance tends to disappear, so that the guarantee and improvement of the reliability of VLSI face huge challenges.
Referring to fig. 2, the larger the scale of a large scale integrated circuit, the more pronounced the channel routing problem, and solutions based on the use of an illite quantum anneal may face circuit channel routing concerns for Very Large Scale Integration (VLSI). The current industry is separated from wafer fabrication and chip design in most cases, i.e. the fab/fables industry is divided into how a wafer manufacturer can flexibly configure the channel routing of various chips, which is very important because different chip design companies need not only different process nodes but also different channel routing for circuits. The present application provides this flexibility. Various related reliability technologies are comprehensively applied to the research and development and production processes of circuit channel wiring in a targeted and quantitative manner, and a guarantee system of the quality and the reliability of a large-scale integrated circuit is constructed from the aspects of technology and management so as to meet the increasingly high requirements of users on reducing the failure rate of the channel wiring and improving the reliability level of the channel wiring. The via routing addressed by the graph coloring can satisfy this requirement.
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 1 to node 2 can be represented by (1,2) and the weight W on this edge 12 S (1, 2); correspond toThe horizontal segment overlap relationship between the connection net1 and the connection net2 in the same track in fig. 3, so that the nodes (1,2) corresponding to the two connections are connected by an edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 2 to node 3 and the weight W on this edge can be represented by (2,3) 23 S (2, 3); the node (2,3) corresponding to the horizontal segment overlapping relationship between the connection net2 and the connection net3 in the same track in fig. 3 is connected by an edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 3 to node 4 can be represented by (3,4) and the weight W on this edge 34 S (3, 4); the horizontal line segment overlapping relationship between the connection net3 and the connection net4 in the same track corresponds to fig. 3, so that the nodes (3,4) corresponding to the two connections are connected by one edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 4 to node 5 can be represented by (4,5) and the weight W on this edge 45 S (4, 5); corresponding to the horizontal segment overlap relationship between the connection net4 and the connection net5 in the same track in fig. 3, the nodes (4,5) corresponding to these two connections are connected by one edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 5 to node 2 and the weight W on this edge can be represented by (5,2) 52 S (5, 2); corresponding to the horizontal segment overlap relationship between line net5 and line net2 in the same track in fig. 3, so that the nodes (5,2) corresponding to these two lines are connected by an edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 5 to node 3 can be represented by (5,3) and the weight W on this edge 53 S (5, 3); corresponding to the horizontal segment overlap relationship between the connection net5 and the connection net3 in the same track in fig. 3, the nodes (5,3) corresponding to these two connections are connected by one edge (edge).
Referring to FIG. 3, in the example of the explanation of the connecting edge, the connecting edge pointing from node 4 to node 2 and the weight on this edge can be represented by (4,2)W 42 S (4, 2); corresponding to the horizontal segment overlap relationship between line net4 and line net2 in the same track in fig. 3, so that the nodes (4,2) corresponding to these two lines are connected by an edge (edge).
Referring to fig. 3, there is again no overlap and no connecting edge between the connection net1 and the connection net 5. The vertex represented by the connection net1 and the vertex represented by the connection net5 are nodes (1,5), respectively, and the nodes (5,1) are not connected by any edge (edge).
Referring to fig. 3, the coloring problem of the horizontal constraint graph HCG with the least variety of colors is solved, which is equivalent to the channel wiring problem using the least track (track). Each line (net) corresponds to a node of the horizontal constraint graph HCG, and if the lines corresponding to two nodes (nodes) cannot be placed in the same track, the two nodes are connected by using an edge, so that the equivalent expression that "two lines cannot be placed in the same track" corresponds to "the nodes at both ends of each edge cannot necessarily be in the same color" can be considered in the present application, so that "allocating a track to a line" is equivalent to "allocating a color to each node of the HCG"; further, the "wiring scheme using the least track" is equivalent to the "HCG coloring scheme using the least color kind". This is a unique design of the present application.
Referring to fig. 3, the vertices in the graph may be colored with different colors.
Referring to fig. 3, based on the teachings presented herein, the subject matter relates to quantum computing or quantum processing that allows operations to be performed on quantum devices, the hamiltonian of which can be designed to meet at least the following objectives: the Yixin Hamiltonian operation comprises various annealing and evolution processes such as quantum annealing or simulated annealing.
Referring to fig. 3, the conventional unitary quantity of isooctane hamiltonian can be described as:
wherein J ij Representing the ith spin x in the Esinhamilton quantity i And the jth spinx j The coupling strength of (2).
Result x of each spin i Composed of binary values-1 and 1, the objective of solving the isooctane problem is to minimize the quantity of isooctane Hamiltonian and obtain x under the condition of minimum Hamiltonian i Corresponding to a value of 1 or-1.
As related to quantum herein, the following is relevant with respect to quantum devices and quantum data:
the term "quantum device" as used herein includes known quantum computing devices, quantum chips, and the like, and quantum hardware may be used instead of such terms. Typical "quantum devices" include, but are not limited to: quantum computers, quantum information processing systems or quantum cryptography systems, quantum simulators, all kinds of devices, apparatuses and machines that process quantum data.
"quantum data" as used herein encompasses information or data carried, held or stored by a quantum system, the smallest nontrivial system being a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" includes all quantum systems that can be appropriately approximated as two-level systems in the respective context. Such quantum systems typically include, for example, typical atomic, electronic, photonic, ionic, or superconducting qubits, and the like.
Referring to fig. 3, the isooctane hamiltonian is constructed for solving the coloring scheme for horizontal constraint graph HCG color minimization, for example, using a binary search method. First, let the degree (degree) in HCG be Δ maximum, and attention is a concept of graph theory, which indicates how many edges (edges) a node (node) in the graph is connected to, i.e. each node has its own degree. Then easy values with a +1 color must be good for coloring the graph. Therefore, the target value which meets the condition that M colors can be colored and M-1 colors cannot be colored can be found by continuously iterating a binary search method or an equivalent search method within the range that M is more than or equal to 2 and less than or equal to delta + 1. The number of characterizing colors, M, is a positive integer. Degree of vertex or node: the degree of a vertex is the number of edges connected to the vertex or node, and there must be a maximum degree for all nodes, for example, the number of edges connected to the node or vertex with the maximum degree is the maximum of all vertices.
Referring to fig. 3, an alternative iteration rule is as follows: the initial value interval is more than or equal to 2 and less than or equal to delta +1, and then M is taken 0 Solving for M by using Yixinji for interval midpoint 0 If the coloring problem of the seed color has a solution, updating the interval to be M is more than or equal to 2 and less than or equal to M if the solution exists 0 And updating the interval to M if there is no solution 0 M is more than or equal to and less than or equal to delta +1, and the middle point of the interval is taken as M again in the new interval 1 (ii) a Solving M by using Yixin machine simultaneously 1 If the coloring problem of the color has a solution, the interval is updated to be more than or equal to 2 and less than or equal to M according to the same principle 1 And updating the interval to M if there is no solution 1 M is more than or equal to and less than or equal to delta +1, and the middle point of the interval is taken as M again in the new interval 2 (ii) a Solving M simultaneously with an Isci machine 2 And (4) judging whether the coloring problem of the colors has a solution, updating the interval again, … …, and continuously iterating until M is found to satisfy that M colors can be colored, and M-1 colors can not be colored. The middle point of the interval is the sum of the upper and lower interval limits and divided by 2, e.g. M 1 ＝(M 0 + Delta +1)/2 and M 2 ＝(M 1 +Δ+1)/2。
Referring to FIG. 3, iteration K M k The coloring problem of a seed color requires that the quantity of isooctane hamilton be constructed in this way. Firstly, the number of nodes in the graph is N, and a binary variable x is taken v,i Subscript value range: v 1,2, …, N, i 1,2, …, M k If the value relation x is satisfied v,i 1 means that the vth node is colored in the ith color, and since one node can only be colored in one color, the following constraint 1 holds:
a penalty function corresponding to the quantity of isooctanes Hamiltonian:
the penalty function means that the value of the penalty function increases if a constraint is violated, e.g. if the color bit x of the v-th node is greater here v,i ＝x v,j For 1, which corresponds to one lighting of two colors, the amount of iyxin hamilton increases the energy of a and a can be defined as a first predetermined coefficient term. The machine is characterized in physical evolution by finding and stabilizing the ground state with the lowest energy. The penalty function in the hamiltonian is at least guaranteed that the iton machine does not evolve to violate the constraint or the result. Note that k and N are both positive integers.
Referring to fig. 3, also constraint 2 conditions, i.e. coloring rules, the color of the two end nodes of each edge must not be the same and this requires a second penalty function, corresponding to the constraint 2 condition:
the term of constraint 2 means that if the nodes at both ends of an edge have the same color, B will be given an energy rise to the inchamiltonian and B here can be defined as a first predetermined coefficient term. This term (constraint 2) exists to avoid this violation of coloring rules in the epoch evolution.
With reference to fig. 3, the final quantity of isooctane is then obtained:
requirement A in the quantity of Yixin Hamilton>B>0 because constraint 1 is required to be more stringent than constraint 2. If the result of quantum annealing is H ising If 0 indicates that there is a solution, then H ising >0 indicates no solution at this time. Note that, if the coefficient of the quantity of the ixinghamiltonian is simultaneously expanded or reduced by several times, the ground state of the quantity of the ixinghamiltonian does not change, so that the specific value of A, B may not be particularly limited as long as a is satisfied>B>0, the selection can be flexible.
Referring to FIG. 3, after all iterations are finished, the final output { x } v,i Which tells each node what color to color and which colors to use in total, i.e. the least needed colors.
Referring to fig. 3, a graph neural network G ═ (V, E) is a definition method of set theory, and the expression may be summarized as that a graph is a set of vertices and edges. V is the Vertex (Vertex) and E is the Edge (Edge). Other expressions of interferograms in the present application are graph neural networks, and therefore interferograms belong to graph neural networks.
As related herein to quantum, the relevant matters regarding quantum machines and quantum data are as follows:
the term "quantum machine" as used herein encompasses known quantum computing devices, quantum chips, and the like, and quantum hardware may be used instead of such terms as quantum devices. Typical "quantum machines" include, but are not limited to: quantum computers, quantum information processing systems or quantum cryptography systems, quantum simulators, all kinds of devices, apparatuses and machines that process quantum data.
Commercial applications for quantum annealing-most typically quantum annealers, such as D-Wave, a quantum computer specialty company in canada. The quantum computer principle of D-Wave commercial sale is that a quantum bit is formed by a tiny current loop made of niobium metal, the quantum annealing phenomenon is realized, and the effect of storing a large number of numerical values by bit data in quantum computation can be simulated.
It is worth noting that in the field of commercial application, the quantum annealing method can effectively solve the optimization problem by searching various possibilities through using the superposition state, and effectively meets the current efficiency improvement and acceleration requirements of the actual working scheme.
Up to now, quantum annealing has constructed a variety of early application programs in various fields such as logistics, artificial intelligence, material science, drug discovery, network security and fault detection, and financial modeling. The currently common annealing algorithm is divided into two types of simulation annealing and quantum annealing, and quantum annealing is superior.
Annealing is essentially a heat treatment process of a metal by slowly heating the metal to a temperature and for a sufficient time and then cooling at a suitable rate. For example, in the case of a semiconductor, annealing is required after ion implantation because when impurity ions are implanted into the semiconductor, the high energy incident ions collide with atoms on the semiconductor lattice to displace the lattice atoms and annealing restores the crystal structure and eliminates defects. The actual annealing solves the problem of unstable hardware process of the material in the development process, and the simulated annealing and the quantum annealing solve the non-optimal solution of mathematical calculation such as combination optimization.
Quantum annealing is a form of Adiabatic Quantum Computing (AQC). Informally, the adiabatic theorem states that if a quantum mechanical system starts from the ground state of a certain hamilton and the speed of changing the hamilton is slow enough, the system will end up with the ground state of the final hamilton. If the initial Hamiltonian is set to a Hamiltonian with a known ground state, and the final Hamiltonian is set to a problem Hamiltonian, the ground state represents the solution of the optimization problem that is desired to be solved, and calculations using this theorem can yield the desired result. The annealing time scale (the expected time required for a single run to reach the solution) is defined by the inverse of the minimum energy gap between the ground state and the first excited state encountered during adiabatic evolution.
Referring to fig. 3, the steps, flowcharts, and schematic diagrams of fig. 1-2 will be described in more detail.
According to the method, a Horizontal Constraint Graph (HCG) is constructed according to channels and internal connecting lines, and as shown in schematic diagrams 1 and 2, each connecting line (net) in a channel is used as a node (node/vertex) of a graph, so 5 lines correspond to 5 nodes, if two connecting lines are placed in the same track, the respective horizontal line segments overlap, which means that the two connecting lines cannot be placed in the same track, and the nodes corresponding to the two connecting lines are connected by an edge (edge) to finally form the HCG, such as schematic diagram 2. This is the first step.
The channel routing problem CRP is mathematically equivalent to "coloring HCG with the least color class", the initial span of the number of color classes is 2-M +1, and the midpoint M is taken in the first iteration 0 The corresponding isooctane hamilton for this graph coloring problem was constructed as (2+ Δ +1)/2, which is the second step:
in a preferred embodiment, it is allowed to perform a mathematical calculation for reducing the quantity of Isuzin to obtain the quantity of Isuzin H in standard form ising ＝-∑ i<j J ij s i s j -∑ i h i s i The parameter J in the standard form ij And h i And inputting an Itanium machine, and starting quantum annealing evolution. This is the third step.
Referring to fig. 3, nodes V and u together with a connection edge (uv), a weight of the edge, and the like construct a directed graph G ═ V, E. For example, it may be assumed that graph G ═ V, E has N nodes in common, V represents the set of all nodes, and E represents the set of all connected edges. Further, as is commonly available, (uv) represents a directed edge pointing from node u to node v, the weight W of the edge uv ＝S(u,v)。
And obtaining the simplified isooctane Hamiltonian in a standard form, and updating a new value interval according to whether a solution exists or not after the evolution of the simplified isooctane Hamiltonian. This is the fourth step. The description of quantum annealing has been presented in detail above, for example, that the ground state of the quantity of evan hamilto represents the solution of the desired optimization problem, and that the calculation of the quantity of evan hamilto based on this theorem yields the desired result. If the solution exists, the interval is updated as follows:
2≤M≤M 0
the result of quantum annealing without solution updates the interval to:
M 0 ≤M≤Δ+1
referring to FIG. 3, in conjunction with the description of FIG. 1, the midpoint M is again taken at a new interval 1 Repeating the second to fourth steps without stopping the cycle updating interval, and taking the midpoint M 2 、M 3 A.. until after a number of iterations, until the interval shrinks small enough to enable one M to be found, it is satisfied that M colors can be colored, and M-1 colors cannot be colored. M is the minimum number of color types needed and the minimum number of tracks needed for time channel wiring, and the solution { x ] of M color coloring v,i And solving the channel wiring problem. Step S15 of finally obtaining a solution may obtain a baseAnd (5) performing state solution.
Referring to fig. 3, the channel wiring problem can be solved by using the above steps with the use of the izod quantum annealing. If there is a solution, for example, the conditions of "M colors coloring each node, and M-1 colors failing to complete coloring each node" are satisfied, and if there is no solution, the conditions of "M colors coloring each node, and M-1 colors failing to complete coloring each node" are not satisfied. And more strictly said "if the quantum annealing result is H ising If H is 0, then there is a solution ising >And 0 has no solution.
Referring to FIG. 3, iteration K M k The coloring problem of a seed color requires that the quantity of isooctane hamilton be constructed in this way. Let N be the number of nodes in the graph, after k iterations, i equals 1,2, …, M k At M, in k Obtaining the ground state solution under the condition. It is noted that quantum annealing and simulated annealing of the Esin Hamiltonian amount are alternatives.
Referring to fig. 3, a channel routing problem solution based on izod quantum annealing. The scheme is used for distributing the connecting lines to each horizontal routing track (track) under the condition of giving one channel and the connecting lines (net) inside the channel, and the horizontal line segments of different connecting lines in the same routing track (track) are required to be partially non-overlapped, namely horizontally restrained. The objective is to solve how to allocate to minimize the number of tracks (tracks) used, and in conjunction with fig. 1, the scheme includes the following steps.
S10, constructing a horizontal constraint graph (horizontal constraint graph) according to the channels and the internal connecting lines thereof.
S11, the channel routing problem CRP is mathematically equivalent to "coloring HCG with the fewest color classes", making the degree (degree) of the node in the level constraint graph a maximum Δ, it is easy to know that Δ +1 colors can certainly color HCG, which is equivalent to first giving such an interval: m is more than or equal to 2 and less than or equal to delta + 1; m is sought within this interval so that M colors can be colored and so that M-1 colors cannot be colored. Preferably, the midpoint of the interval is M 0 Construction of M 0 The plot coloring problem for a color corresponds to the quantity of EsinoHamilton.
S12, simplifying the Ilaceous Hamiltonian by mathematical calculation to obtain the Ilaceous Hamiltonian in a standard form, and inputting the parameters in the standard form into an Ilaceous machine to start quantum annealing evolution.
S13, outputting by an Yixinji after evolution to judge whether a solution exists: if the solution exists, the interval is updated to be M is more than or equal to 2 and less than or equal to M 0 And updating the interval to M without solution 0 ≤M≤Δ+1。
S14, iteration process: taking the midpoint of the interval as M 1 Returning to S11 to construct M 1 The number of Esinohamiltonian for the color chart coloring problem is repeated from S11 to S13. The process is iterated continuously, namely a binary search process, the range of the interval is reduced continuously until M is found, the condition that M colors can be colored is met, and M-1 colors cannot be colored. The M colors are the minimum color types required, and the output of the Itanium machine is the coloring scheme of the M colors.
Referring to fig. 1, the scheme disclosed in the present application is characterized in that the problem of channel wiring optimization in integrated circuit design is solved by using the izod quantum annealing, rather than using the conventional genetic algorithm, ant colony algorithm, etc., and the izod quantum annealing is more efficient in the case of large circuit scale and many wires. And the solution is suitable for various different physical system implemented Italian machines, for example, no matter what the specific implementation scheme of the Italian machine is, the scheme can be mapped without obstacles. The concrete implementation scheme of the Isimmer comprises a photon Isimmer, an electric Isimmer, a superconductor, an ion trap Isimmer and the like. Other names of additional wires in the chip design link include metal interconnects or metal wires, etc. The important role of the wiring is to couple different channels having electrical connection relationship.
While the above specification teaches the preferred embodiments with a certain degree of particularity, there is shown in the drawings and will herein be described in detail a presently preferred embodiment with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific embodiment illustrated. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims (10)
1. A method of routing a channel of a very large scale integrated circuit, comprising:
and establishing a horizontal constraint map of the connecting lines according to the connecting line condition of a given channel, wherein the horizontal constraint map is used for constructing the Einchamiltonian quantity, and the connecting lines are distributed to different horizontal trend orbits according to the annealing evolution result of the Einchamiltonian quantity.
2. The method of claim 1, wherein:
on the premise of limiting that the horizontal line segments of different connecting lines on the same routing track are not overlapped, the number of the routing tracks is minimum according to an annealing evolution result.
3. The method of claim 1, wherein:
the manner of establishing the horizontal constraint map comprises: and taking each connecting line as a node, and if two connecting lines arranged in the same routing track are overlapped, connecting the nodes corresponding to the two connecting lines by using one edge.
4. The method of claim 1, wherein:
finding the numerical value of M in a graph coloring mode and coloring each node of the horizontal constraint graph by using M colors, and meanwhile, requiring that the M colors can color each node but M-1 colors cannot finish coloring each node: the M colors are then defined as the minimum color type required and equivalent to the number of trace tracks with the minimum number of trace tracks.
5. The method of claim 4, wherein:
the maximum degree of the nodes in the horizontal constraint graph is delta, M is searched in the range that the initial value interval of the color category number is more than or equal to 2 and less than or equal to delta +1, and the initial midpoint of the interval is M 0 ＝(2+Δ+1)/2。
6. The method of claim 5, wherein:
if the annealing evolution of the Itani Hamilton quantity has a solution, updating to obtain a value interval of a new color variety number and updating the interval to be more than or equal to 2 and less than or equal to M 0 。
7. The method of claim 5, wherein:
if the annealing evolution of the Itani Hamiltonian is not solved, updating to obtain a value interval of a new color variety number and updating the interval to M 0 ≤M≤Δ+1。
8. The method of claim 7, wherein:
obtaining a new interval M over k iterations k-1 M is not less than M and not more than delta +1, wherein M k-1 Is the midpoint of the new interval obtained from the (k-1) th iteration.
9. The method of claim 8, wherein:
midpoint M of new interval of kth iteration k ＝(M k-1 + Δ +1)/2, each iteration solving for M by the annealing evolution of the Itani Hamilton quantity k And (4) judging whether the coloring problem of the colors has a solution or not, and repeating the iteration for a plurality of times until the condition that M colors can color each node but M-1 colors cannot finish coloring each node is found.
10. A method for routing a VLSI channel, comprising the steps of:
s10, constructing a horizontal constraint graph according to the channels and the connecting lines of the channels;
s11, constructing an Exihamilton according to the value interval of the color variety number corresponding to the node in the horizontal constraint graph;
s12, carrying out annealing evolution on the Ilaceous Hamiltonian;
s13, judging whether the annealing evolution result has a solution, if not, executing a step S14, otherwise, executing a step S15;
s14, iterating to obtain a new value interval, and repeatedly executing the steps S11-S13;
s15, finding out the minimum color type required by graph coloring, and on the premise that the horizontal line segments of different connecting lines on the same trace track are not overlapped, minimizing the number of trace tracks according to the minimum color type.
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