KR102430482B1 - Method for placement semiconductor device based on prohibited area information - Google Patents

Abstract

Disclosed is a method for disposing a semiconductor device performed by a computing device according to one embodiment of the present disclosure. The method may comprise: a step of receiving the information for a designated prohibited area wherein the semiconductor device is not disposed; and a step of training a neural network model so as to dispose the semiconductor device, based on the characteristic information of the semiconductor device and the information for the prohibited area. Therefore, the present invention is capable of improving a training speed.

Description

Method for placing semiconductor devices based on forbidden area information

The present invention relates to a semiconductor design method, and more specifically, to an artificial intelligence technology for solving and optimizing problems occurring in a semiconductor design process.

This study was carried out as part of the private intelligent information service expansion project of the Ministry of Science and ICT and the Information and Communication Industry Promotion Agency (A0903-21-1021, AI-based semiconductor design automation system development).

Despite technological advances, the reality is that the logical design of semiconductors, which can be viewed as an integral part of the high-tech industry, is generally performed by engineers using rule-based software. Therefore, the logical design of semiconductors has to be performed based on the engineer's experience, and the design speed is inevitably different depending on the skill level of the engineer. In addition, it is practically very difficult for an engineer to efficiently arrange the connections between tens to millions of semiconductor devices in mind. That is, since the current semiconductor design process depends on the experience and intuition of an engineer, it is difficult to maintain a consistent design quality, and the time and money that must be invested for the design are inevitably required.

Korean Patent Registration No. 10-0296183 (October 22, 2001) discloses a method for designing a semiconductor integrated circuit.

The present disclosure is devised in response to the above-described background technology, provides a tool to increase the convenience of experts, and uses the expert's knowledge and experience as a heuristic to reduce the search space for the arrangement of semiconductor devices, thereby speeding up learning An object of the present invention is to provide a method of arranging a semiconductor device based on forbidden region information that can improve .

Disclosed is a method performed by a computing device according to an embodiment of the present disclosure for realizing the above-described task. The method includes the steps of: receiving information about a designated forbidden region in which a semiconductor device is not disposed; and training a neural network model to arrange the semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region.

Alternatively, the feature information may include: size information including at least one of a width or a height of the semiconductor device; Alternatively, it may include at least one of type information indicating whether the semiconductor device is a macro cell.

Alternatively, the step of receiving the information on the prohibited area includes receiving the information on the prohibited area based on a user interface, wherein the user interface is a canvas divided by a grid. ) a first area representing a space; and a second region for selecting a semiconductor device to which the forbidden region is to be applied.

Alternatively, the method may further include, when input information of a user selecting at least one space of the canvas displayed in the first area is received, designating the corresponding area as a prohibited area.

Alternatively, the training of the neural network model may include training the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region.

Alternatively, the training of the neural network model may include: when user input information for selecting a semiconductor device to be applied to the forbidden region is received through the second region, the neural network may include such that the selected semiconductor device is not placed in the forbidden region. It may include training the model.

Alternatively, in the method, a plurality of semiconductor devices may be simultaneously selected as an application target of the forbidden region through the user interface, and the step of training the neural network model includes: The method may further include training a neural network model so that the plurality of semiconductor devices are not all disposed.

Alternatively, the training of the neural network model may include, through the neural network model, arranging the semiconductor device based on a state including the feature information and information on the forbidden region. performing the steps; estimating a reward for the action; returning the reward to the neural network model, and performing reinforcement learning on the neural network model.

Disclosed is a computer program stored in a computer-readable storage medium according to an embodiment of the present disclosure for realizing the above-described problems. When the computer program is executed on one or more processors, the computer program performs the following operations for disposing a semiconductor device, the operations comprising: receiving information about a designated forbidden region in which a semiconductor device is not disposed; and training the neural network model to arrange the semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region.

Disclosed is a computing device according to an embodiment of the present disclosure for realizing the above-described problems. The apparatus includes: a processor including at least one core; a memory containing program codes executable by the processor; and a network unit configured to receive information on a forbidden region designated so that a semiconductor device is not disposed, wherein the processor learns a neural network model to place a semiconductor device based on characteristic information of the semiconductor device and information on the forbidden region. can do it

The present disclosure may provide a method of arranging a semiconductor device based on user input information, which can improve a learning speed by reducing a search space for disposing a semiconductor device by using the expert's knowledge and experience as a heuristic.

1 is a conceptual diagram illustrating a basic semiconductor design process.
2 is a block diagram of a computing device according to an embodiment of the present disclosure.
3 is a conceptual diagram illustrating a neural network according to an embodiment of the present disclosure.
4 to 5 are diagrams illustrating a process of receiving information on a forbidden area based on a user interface according to an embodiment of the present disclosure.
6 is a conceptual diagram illustrating a reinforcement learning process.
7 is a conceptual diagram illustrating a preprocessing process for a state of a neural network model according to an embodiment of the present disclosure.
8 to 16 are conceptual diagrams illustrating a process of estimating a reward for a behavior of a neural network model according to an embodiment of the present disclosure.
17 is a flowchart illustrating a method of disposing a semiconductor device based on user input information according to an additional exemplary embodiment of the present disclosure.
18 is a conceptual diagram of a computing environment according to an embodiment of the present disclosure.

Various embodiments are now described with reference to the drawings. In this specification, various descriptions are presented to provide an understanding of the present disclosure. However, it is apparent that these embodiments may be practiced without these specific descriptions.

The terms “component,” “module,” “system,” and the like, as used herein, refer to a computer-related entity, hardware, firmware, software, a combination of software and hardware, or execution of software. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, a thread of execution, a program, and/or a computer. For example, both an application running on a computing device and the computing device may be a component. One or more components may reside within a processor and/or thread of execution. A component may be localized within one computer. A component may be distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored therein. Components may communicate via a network such as the Internet with another system, for example via a signal having one or more data packets (eg, data and/or signals from one component interacting with another component in a local system, distributed system, etc.) may communicate via local and/or remote processes depending on the data being transmitted).

In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from context, "X employs A or B" is intended to mean one of the natural implicit substitutions. That is, X employs A; X employs B; or when X employs both A and B, "X employs A or B" may apply to either of these cases. It should also be understood that the term “and/or” as used herein refers to and includes all possible combinations of one or more of the listed related items.

Also, the terms "comprises" and/or "comprising" should be understood to mean that the feature and/or element in question is present. However, it should be understood that the terms "comprises" and/or "comprising" do not exclude the presence or addition of one or more other features, elements and/or groups thereof. Also, unless otherwise specified or unless it is clear from context to refer to a singular form, the singular in the specification and claims should generally be construed to mean “one or more”.

And, the term "at least one of A or B" should be interpreted to mean "when including only A", "when including only B", and "when combined with the configuration of A and B".

Those skilled in the art will further appreciate that the various illustrative logical blocks, configurations, modules, circuits, means, logics, and algorithm steps described in connection with the embodiments disclosed herein may be implemented in electronic hardware, computer software, or combinations of both. It should be recognized that they can be implemented with To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, means, logics, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application. However, such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Descriptions of the presented embodiments are provided to enable those skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art of the present disclosure. The generic principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Thus, the present invention is not limited to the embodiments presented herein. This invention is to be construed in its widest scope consistent with the principles and novel features presented herein.

1 is a conceptual diagram illustrating a basic semiconductor design process.

In order to design a semiconductor, netlist information defining characteristics of semiconductor devices and a connection relationship between the devices is required. In the netlist information, semiconductor devices are divided into a macro cell having a relatively large size and a standard cell having a relatively small size. A macro cell does not have a separate specification for its size, and it is characterized by a larger size than a standard cell because it is sometimes composed of millions of transistors. For example, macro cells include SRAM or CPU Core. A standard cell is a small unit that performs basic functions, consisting of one or more transistors. Standard cells provide simple logical operations (e.g. AND, OR, XOR) or storage functions such as flip-flops, and more complex functions such as 2-bit full adders or multiple D-input flip-flops. Unlike a macro cell, a standard cell has a size specification.

The netlist information can be viewed as a set of nets indicating connectivity of semiconductor devices. The netlist information generally represents the properties and connection relationships of hundreds of macro cells and hundreds of thousands to millions of standard cells as data of a hypergraph structure. A hypergraph is a graph in which one edge can express a connection relationship to a plurality of nodes, unlike an ordinary graph in which one edge shows a connection relationship to two nodes.

Referring to FIG. 1 , a process for designing a semiconductor may be divided into three steps. First, a floorplan step 11 in which a macro cell, which is an element having a relatively large size, is arranged on an empty canvas is performed. Next, a placement step 12 of arranging macro cells of the canvas and placing standard cells in the remaining space is performed. Finally, the macro cell and the standard cell arranged on the canvas through a wire are physically connected and a routing step 13 is performed.

Whether a good design is achieved through the above-described process is evaluated through a metric called PPA. PPA represents power, performance, and area. According to PPA, semiconductor design aims to have low production cost with small area, ie, high integration, while exhibiting low power consumption and high performance. In order to optimize the PPA according to this goal, it is necessary to reduce the length of the wire connecting the semiconductor devices. When the length of the wire connecting the elements is shortened, the arrival of the electric signal may be accelerated. And, if the arrival of the electric signal is accelerated, the performance of the semiconductor is inevitably increased. In addition, by transmitting an electrical signal within a short time, power consumption is reduced. In addition, when the overall use of wires is reduced, the degree of integration is increased and the area occupied by the devices is inevitably reduced.

According to the above point of view, it may be considered simply to place all the elements close together for good design. However, since a routing resource representing a resource capable of allocating a wire for each canvas is limited, it is practically impossible to simply arrange all the elements close to each other. For example, when another wire already exists in a path through which a wire for connecting two elements passes, a wire for connecting two elements has no choice but to bypass the other wire and be disposed through another canvas area. In this case, as the wire is circumvented, the length of the wire is inevitably increased, and inevitably affects the arrangement of the wire for connection of subsequent elements. That is, since routing resources, which are resources that can physically allocate wires to each area of the canvas, are limited, when devices are arranged without considering routing resources, the design result is inevitably deteriorated.

Therefore, for good design, it is important to consider the overall connectivity including the standard cell from the floor plan stage 11 in which a macro cell having a relatively large size and a lot of connectivity is disposed. Currently, the floor plan stage 11 is mainly performed manually by an engineer. For example, in the floor plan step 11, macro cells are arranged according to the engineer's intuition. Engineers often place macro cells on the edges of the canvas, leaving the center space for standard cells. After the macro cell is placed, the engineer places the standard cell using the functions provided by the existing rule-based tool. In other words, the logical design process of semiconductors is currently being performed depending on the experience of engineers to a large extent. In this method, it is practically very difficult to arrange in consideration of the connection relationship of several hundred to several million devices, so there is a problem in that the speed of work or the quality of the result is inevitably different depending on the skill of the engineer. In addition, the design process (12, 13) following the floor plan step (11) sometimes takes several days or more, and when the quality of the final design result is not good, the process ( 12, 13) must be performed again. Repeating this cycle several times is inevitably costly. Accordingly, there is a need for a method capable of reducing variations in design quality while performing fast and accurate design from the logical design stage of semiconductors.

In addition, semiconductor devices with strong connectivity should be disposed adjacent to each other. In the arrangement of the semiconductor device, the connectivity between the macro cell and the standard cell and the connectivity between the macro cells should be taken into consideration. For example, standard cells should be arranged to be relatively close to each other. Engineers tend to place macros on the outside of their initial semiconductor device placement. Efforts should be made to improve the learning speed by reducing the search space in the arrangement of semiconductor devices by using the knowledge and experience of these experts as heuristics. An object of the present disclosure is to make a tool that enhances the convenience of the expert rather than completely replacing the expert. Also, the present disclosure may provide a user interface based on domain knowledge. In the present disclosure, optimization through reinforcement learning can be performed by designating a desired location region of a semiconductor device on a canvas.

Hereinafter, the method of the present disclosure devised based on the above-described problem will be described in detail with reference to FIGS. 2 to 18 .

2 is a block diagram of a computing device for disposing a semiconductor device based on user input information according to an embodiment of the present disclosure.

The configuration of the computing device 100 shown in FIG. 2 is only a simplified example. In an embodiment of the present disclosure, the computing device 100 may include other components for performing the computing environment of the computing device 100 , and only some of the disclosed components may configure the computing device 100 .

The computing device 100 may include a processor 110 , a memory 130 , and a network unit 150 .

The processor 110 may include one or more cores, and a central processing unit (CPU) of a computing device, a general purpose graphics processing unit (GPGPU), and a tensor processing unit (TPU). unit) and the like, and may include a processor for data analysis and deep learning. The processor 110 may read a computer program stored in the memory 130 to perform data processing for machine learning according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the processor 110 may perform an operation for learning the neural network. The processor 110 for learning of the neural network, such as processing input data for learning in deep learning (DL), extracting features from the input data, calculating an error, updating the weight of the neural network using backpropagation calculations can be performed. At least one of a CPU, a GPGPU, and a TPU of the processor 110 may process learning of a network function. For example, the CPU and the GPGPU can process learning of a network function and data classification using the network function. Also, in an embodiment of the present disclosure, learning of a network function and data classification using the network function may be processed by using the processors of a plurality of computing devices together. In addition, the computer program executed in the computing device according to an embodiment of the present disclosure may be a CPU, GPGPU or TPU executable program.

According to an embodiment of the present disclosure, the processor 110 may train a neural network model for logically designing a semiconductor. The processor 110 may train a neural network model for arranging the semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region. For example, the processor 110 may train the neural network model to arrange the semiconductor device on the canvas based on the characteristic information of the semiconductor device and the information on the forbidden region. The feature information may include size information including at least one of a width or a height of the semiconductor device or type information indicating whether the semiconductor device is a macro cell. The information on the forbidden area may be user input information that selects at least one area of a canvas space divided by a grid based on the user interface. That is, the neural network model may be trained to place the semiconductor device on the canvas by receiving information about the properties of the semiconductor device itself and the forbidden region designated so that the semiconductor device is not disposed.

Meanwhile, the logical design information may include index information regarding an arrangement order of semiconductor devices and netlist information indicating a connection relationship between semiconductor devices. The neural network model may be trained to receive information on a connection relationship between semiconductor devices and arrange the semiconductor devices on the canvas by further considering logical design information. In this case, the neural network model may be trained such that the PPA is optimized in consideration of the length of the wires of the elements, and the routing resources of the canvas and the elements.

The processor 110 may perform logical design of the semiconductor using the neural network model trained in advance as described above. For example, the processor 110 may arrange the semiconductor device on the canvas based on characteristic information of the semiconductor device and information on the forbidden region using the learned neural network model. The neural network model may arrange the semiconductor elements on the canvas so that all the semiconductor elements are connected and at the same time the density and density of the semiconductor elements on the canvas are distributed as evenly as possible. This arrangement process corresponds to the floor plan corresponding to the logical design of the semiconductor. That is, the processor 110 can effectively improve problems in terms of cost and quality of the existing floor plan method through the learned neural network model.

According to an embodiment of the present disclosure, the memory 130 may store any type of information generated or determined by the processor 110 and any type of information received by the network unit 150 .

According to an embodiment of the present disclosure, the memory 130 is a flash memory type, a hard disk type, a multimedia card micro type, and a card type memory (eg, For example, SD or XD memory), Random Access Memory (RAM), Static Random Access Memory (SRAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Programmable Read (PROM) -Only Memory), a magnetic memory, a magnetic disk, and an optical disk may include at least one type of storage medium. The computing device 100 may operate in relation to a web storage that performs a storage function of the memory 130 on the Internet. The description of the above-described memory is only an example, and the present disclosure is not limited thereto.

The network unit 150 according to an embodiment of the present disclosure may use any type of known wired/wireless communication system.

The network unit 150 may receive information for semiconductor design from an external system. For example, the network unit 150 may receive characteristic information and logical design information of a semiconductor device from a semiconductor-related database. In this case, the feature information and logical design information received from the database may be data for training or inference of the neural network model. The characteristic information and logical design information of the semiconductor device may include the information of the above-described examples, but are not limited to the above-described examples, and may be variously configured within a range that can be understood by those skilled in the art.

Also, the network unit 150 may receive information on a prohibited area designated so that a semiconductor device is not disposed on the canvas. The network unit 150 may transmit and receive information processed by the processor 110 , a user interface, and the like through communication with other terminals. For example, the network unit 150 may provide a user interface generated by the processor 110 to a client (e.g. a user terminal). Also, the network unit 150 may receive an external input of a user authorized as a client and transmit it to the processor 110 . In this case, the processor 110 may process an operation of outputting, modifying, changing, or adding information provided through the user interface based on the user's external input received from the network unit 150 .

Meanwhile, the computing device 100 according to an embodiment of the present disclosure may include a server as a computing system for transmitting and receiving information through communication with a client. In this case, the client may be any type of terminal that can access the server. For example, the computing device 100 as a server may receive information for semiconductor design from an external database, generate a logical design result, and provide a user interface related to the logical design result to the user terminal. In this case, the user terminal may output a user interface received from the computing device 100 which is a server, and may receive or process information through interaction with the user.

In an additional embodiment, the computing device 100 may include any type of terminal that receives a data resource generated by an arbitrary server and performs additional information processing.

3 is a conceptual diagram illustrating a neural network according to an embodiment of the present disclosure.

A neural network model according to an embodiment of the present disclosure may include a neural network for disposing a semiconductor device. A neural network may be composed of a set of interconnected computational units, which may generally be referred to as nodes. These nodes may also be referred to as neurons. A neural network is configured to include at least one or more nodes. Nodes (or neurons) constituting the neural networks may be interconnected by one or more links.

In the neural network, one or more nodes connected through a link may relatively form a relationship between an input node and an output node. The concepts of an input node and an output node are relative, and any node in an output node relationship with respect to one node may be in an input node relationship in a relationship with another node, and vice versa. As described above, an input node-to-output node relationship may be created around a link. One or more output nodes may be connected to one input node through a link, and vice versa.

In the relationship between the input node and the output node connected through one link, the value of the data of the output node may be determined based on data input to the input node. Here, a link interconnecting the input node and the output node may have a weight. The weight may be variable, and may be changed by the user or algorithm in order for the neural network to perform a desired function. For example, when one or more input nodes are interconnected to one output node by respective links, the output node sets values input to input nodes connected to the output node and links corresponding to the respective input nodes. An output node value may be determined based on the weight.

As described above, in a neural network, one or more nodes are interconnected through one or more links to form an input node and an output node relationship in the neural network. The characteristics of the neural network may be determined according to the number of nodes and links in the neural network, the correlation between the nodes and the links, and the value of a weight assigned to each of the links. For example, when the same number of nodes and links exist and there are two neural networks having different weight values of the links, the two neural networks may be recognized as different from each other.

A neural network may consist of a set of one or more nodes. A subset of nodes constituting the neural network may constitute a layer. Some of the nodes constituting the neural network may configure one layer based on distances from the initial input node. For example, a set of nodes having a distance n from the initial input node may constitute n layers. The distance from the initial input node may be defined by the minimum number of links that must be traversed to reach the corresponding node from the initial input node. However, the definition of such a layer is arbitrary for description, and the order of the layer in the neural network may be defined in a different way from the above. For example, a layer of nodes may be defined by a distance from the final output node.

The initial input node may mean one or more nodes to which data is directly input without going through a link in a relationship with other nodes among nodes in the neural network. Alternatively, in a relationship between nodes based on a link in a neural network, it may mean nodes that do not have other input nodes connected by a link. Similarly, the final output node may refer to one or more nodes that do not have an output node in relation to other nodes among nodes in the neural network. In addition, the hidden node may mean nodes constituting the neural network other than the first input node and the last output node.

The neural network according to an embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be the same as the number of nodes in the output layer, and the number of nodes decreases and then increases again as the input layer progresses to the hidden layer. can In addition, the neural network according to another embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be less than the number of nodes in the output layer, and the number of nodes decreases as the number of nodes progresses from the input layer to the hidden layer. have. In addition, the neural network according to another embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be greater than the number of nodes in the output layer, and the number of nodes increases as the number of nodes progresses from the input layer to the hidden layer. can The neural network according to another embodiment of the present disclosure may be a neural network in a combined form of the aforementioned neural networks.

A deep neural network (DNN) may refer to a neural network including a plurality of hidden layers in addition to an input layer and an output layer. Deep neural networks can be used to identify the latent structures of data. In other words, it can identify the potential structure of photos, texts, videos, voices, and music (e.g., what objects are in the photos, what the text and emotions are, what the texts and emotions are, etc.) . Deep neural networks include convolutional neural networks (CNNs), recurrent neural networks (RNNs), auto encoders, generative adversarial networks (GANs), restricted boltzmann machines (RBMs), It may include a deep belief network (DBN), a Q network, a U network, a Siamese network, and the like. The description of the deep neural network described above is only an example, and the present disclosure is not limited thereto.

In an embodiment of the present disclosure, the neural network may include an autoencoder. The auto-encoder may be a kind of artificial neural network for outputting output data similar to input data. The auto encoder may include at least one hidden layer, and an odd number of hidden layers may be disposed between the input/output layers. The number of nodes in each layer may be reduced from the number of nodes in the input layer to an intermediate layer called the bottleneck layer (encoding), and then expanded symmetrically with reduction from the bottleneck layer to the output layer (symmetrical to the input layer). Autoencoders can perform non-linear dimensionality reduction. The number of input layers and output layers may correspond to a dimension after preprocessing the input data. In the auto-encoder structure, the number of nodes of the hidden layer included in the encoder may have a structure that decreases as the distance from the input layer increases. If the number of nodes in the bottleneck layer (the layer with the fewest nodes between the encoder and decoder) is too small, a sufficient amount of information may not be conveyed, so a certain number or more (e.g., more than half of the input layer, etc.) ) may be maintained.

The neural network may be trained by at least one of teacher learning, unsupervised learning, semi-supervised learning, and reinforcement learning. Learning of a neural network may be a process of applying knowledge for performing a specific operation to the neural network.

Neural networks can be trained in a way that minimizes errors in output. In neural network learning, iteratively input the training data to the neural network, calculate the output and target errors of the neural network for the training data, and backpropagate the neural network error from the output layer of the neural network to the input layer in the direction to reduce the error ( It is the process of updating the weight of each node of the neural network by backpropagation. In the case of teacher learning, learning data in which the correct answer is labeled in each learning data is used (ie, labeled learning data), and in the case of comparative learning, the correct answer may not be labeled in each learning data. That is, for example, the learning data in the case of teacher learning regarding data classification may be data in which categories are labeled for each of the learning data. The labeled training data is input to the neural network, and an error can be calculated by comparing the output (category) of the neural network with the label of the training data. As another example, in the case of comparison learning about data classification, an error may be calculated by comparing the input training data with the neural network output. The calculated error is back propagated in the reverse direction (ie, from the output layer to the input layer) in the neural network, and the connection weight of each node of each layer of the neural network may be updated according to the back propagation. A change amount of the connection weight of each node to be updated may be determined according to a learning rate. The computation of the neural network on the input data and the backpropagation of errors can constitute a learning cycle (epoch). The learning rate may be applied differently depending on the number of repetitions of the learning cycle of the neural network. For example, in the early stage of learning of a neural network, a high learning rate can be used to enable the neural network to quickly obtain a certain level of performance, thereby increasing efficiency, and using a low learning rate in the late learning period to increase accuracy.

In the training of neural networks, in general, the training data may be a subset of the actual data (that is, the data to be processed using the learned neural network), and thus the error on the training data decreases but the error on the real data increases. A learning cycle may exist. Overfitting is a phenomenon in which errors on actual data increase by over-learning on training data as described above. For example, a phenomenon in which a neural network that has learned a cat by showing a yellow cat does not recognize that it is a cat when it sees a cat other than yellow may be a type of overfitting. Overfitting can act as a cause of increasing errors in machine learning algorithms. In order to prevent such overfitting, various optimization methods can be used. In order to prevent overfitting, methods such as increasing the training data, regularization, and dropout that deactivate some of the nodes of the network in the process of learning, and the use of a batch normalization layer are applied. can

4 to 5 are diagrams illustrating a process of receiving information on a forbidden area based on a user interface according to an embodiment of the present disclosure. 4 to 5 are diagrams illustrating results of arranging semiconductor devices in a neural network model based on characteristic information of the semiconductor device and information on forbidden regions.

The processor 110 according to an embodiment of the present disclosure may receive information on a forbidden region designated so that a semiconductor device is not disposed. The processor 110 may receive information on the prohibited area based on the user interface (UI). The forbidden region may be a region designated so that a semiconductor device of a specific type or a specific size is not disposed on the grid-divided canvas. Meanwhile, the processor 110 may receive information on an allowable region designated to place a semiconductor device. The processor 110 may receive information on the allowed area based on the user interface (UI). The allowable area may be an area designated so that a semiconductor device of a specific type or a specific size is disposed on a canvas divided by a grid.

The user interface (UI) may include a first area 310 displaying a canvas space divided by a grid. The first area 310 may include a canvas space divided by a grid of N*N (N is a natural number). A plurality of semiconductor devices may be disposed in the canvas space. Also, the user interface UI may include a second region 320 for selecting a semiconductor device to which the forbidden region is to be applied. The second region 320 may include items corresponding to semiconductor devices disposed on the canvas. A semiconductor device may be divided into a macro cell having a relatively large size and a standard cell having a relatively small size.

When user input information for selecting at least one space of the canvas displayed in the first area 310 is received, the processor 110 according to an embodiment of the present disclosure may designate the corresponding area as a prohibited area. Exemplarily, referring to FIG. 4 , the processor 110 receives first user input information selecting (0, 2), (0, 3), (1, 2), (1, 3) of a grid cell. can do. The processor 110 may designate a corresponding region as the first forbidden region 330a in which a semiconductor device of a specific type or a specific size cannot be disposed in consideration of the first user input information. Also, the processor 110 may receive second user input information for selecting (2, 1) and (3, 2) of the grid cell. The processor 110 may designate the corresponding region as the second forbidden region 330b in which a semiconductor device of a specific type or a specific size cannot be disposed in consideration of the second user input information.

The processor 110 according to an embodiment of the present disclosure may train a neural network model to arrange the semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region. The processor 110 may train the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region. The characteristic information of the semiconductor device may include size information including at least one of a width or a height of the semiconductor device. Also, the characteristic information may include type information indicating whether the semiconductor device is a macro cell. Meanwhile, the processor 110 may train the neural network model to arrange the semiconductor device based on the characteristic information of the semiconductor device and the information on the allowable region. The processor 110 may train the neural network model so that a semiconductor device of a specific type or a specific size is disposed in the allowable region.

For example, referring to FIG. 4 , the processor 110 may train the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in a region designated as the first forbidden region 330a. Here, the semiconductor device of a specific type or a specific size may be a relatively large macro cell, but is not limited thereto. Also, the processor 110 may train the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in an area designated as the second forbidden area 330b. Here, the semiconductor device of a specific type or a specific size may be a relatively large macro cell, but is not limited thereto. That is, the processor 110 may train the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the first forbidden region 330a and the second forbidden region 330b.

As a result of training the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region, the processor 110 arranges a relatively small standard cell #7 in the 1-1 forbidden region 340a. can do. Also, as a result of training the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region, the processor 110 generates a standard cell (#8) having a relatively small size in the 2-1 forbidden region 340b. can be placed. The processor 110 considers the user input information, and the macro cells #1, #2, and #3, which are semiconductor devices having relatively large sizes, are disposed outside, and the semiconductor devices that are relatively small in size and should be disposed close to each other. By arranging the in-standard cells (#4, #5, #6, #7, #8, #9, #10) in the center, optimization through reinforcement learning can be performed.

According to an embodiment of the present disclosure, when user input information for selecting a semiconductor device to be applied to the forbidden region is received through the second region 320 , the processor 110 prevents the selected semiconductor device from being placed in the forbidden region. A neural network model can be trained. The second region 320 may include a plurality of items associated with a semiconductor device to which the forbidden region is applied. A plurality of semiconductor devices may be simultaneously selected as an application target of the forbidden region through the user interface (UI). For example, referring to FIG. 5 , the processor 110 may receive user input information for selecting at least one of a plurality of items included in the second area 320 . The processor 110 may receive third user input information for selecting the semiconductor devices Macro3 , StdCell3 , and StdCell4 to be applied to the forbidden region through the second region 320 . The elements of Macro3, StdCell3, and StdCell4 included in the third user input information will be referred to as a non-disposable element 320a for convenience of description. The processor 110 may receive first user input information for selecting (0, 2), (0, 3), (1, 2), and (1, 3) of the grid cell. The processor 110 may designate a corresponding region as the first forbidden region 330a in which a semiconductor device of a specific type or a specific size cannot be disposed in consideration of the first user input information. Also, the processor 110 may receive second user input information for selecting (2, 1) and (3, 2) of the grid cell. The processor 110 may designate the corresponding region as the second forbidden region 330b in which a semiconductor device of a specific type or a specific size cannot be disposed in consideration of the second user input information.

The processor 110 according to an embodiment of the present disclosure may train a neural network model to arrange the semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region. The processor 110 may train the neural network model so that the plurality of semiconductor devices selected as application targets are not all disposed in the forbidden region. The processor 110 may train the neural network model so that the non-placeable element 320a is not disposed in the area designated as the first forbidden area 330a. Also, the processor 110 may train the neural network model so that the non-placeable element 320a is not disposed in the area designated as the second forbidden area 330b. As a result of training the neural network model so that non-placeable elements are not disposed in the forbidden region, the processor 110 may arrange the disposable elements (#4, #1) in the 1-2-th forbidden region 341a. In addition, as a result of training the neural network model so that non-placeable elements are not disposed in the forbidden region, the processor 110 may arrange the deployable elements (#5, #9) in the 2-2th forbidden region 341b. .

6 to 16 are conceptual diagrams for explaining a reinforcement learning process of a neural network model according to an embodiment of the present disclosure.

Reinforcement learning is a learning method of learning a neural network model based on a reward calculated for an action selected by the neural network model so that the neural network model can determine a better action based on a state. A state is a set of values indicating what the situation is at the present time, and can be understood as an input to a neural network model. Behavior refers to a decision based on the options that a neural network model can take, and can be understood as an output of a neural network model. The reward refers to the benefit that the neural network model performs when it performs a certain action, and represents the immediate value that the neural network model evaluates for the current state and action. Reinforcement learning can be understood as learning through trial and error in that decisions (i.e. actions) are rewarded. The reward given to the neural network model in the reinforcement learning process may be a reward that accumulates the results of several actions. Through reinforcement learning, it is possible to create a neural network model that maximizes the return such as the reward itself or the sum of the rewards by considering the rewards according to various states and actions. In the present disclosure, the neural network model may be used interchangeably with the term agent, which is a subject that determines what action to take depending on the surrounding state. Referring to FIG. 6 , in reinforcement learning, an environment 220 to which the agent 210 belongs exists. The environment 220 may be understood to mean the setting itself for reinforcement learning of the agent 210 . When the agent 210 takes action, the state changes through the environment 220 , and the agent 210 may receive a reward. The goal of reinforcement learning is to train the agent 210 to receive as much reward as possible in a given environment 220 .

According to an embodiment of the present disclosure, the processor 110 includes a state including characteristic information of a semiconductor device and information on a forbidden region, an action of arranging the semiconductor device on a canvas, and a reward ( Through reinforcement learning based on reward), a neural network model can be trained. The processor 110 causes the neural network model to perform an action of placing one semiconductor device on the canvas per cycle, and returns a reward according to the action along with the state so that the neural network model performs the action according to the next cycle, Reinforcement learning can be performed on neural network models. For example, the processor 110 may perform an action at a specific time t of disposing the semiconductor device on the canvas based on the state of the specific time t through the neural network model. The processor 110 may estimate a reward at a next time t+1 for an action at a specific time t, and return the estimated reward to the neural network model. The processor 110 may perform the action of the next time t+1 by inputting the state and reward of the next time t+1 to the neural network model. The processor 110 may repeat this cycle to train the neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region.

According to an embodiment of the present disclosure, the state to be input to the neural network model may include characteristic information indicating characteristics of the semiconductor device itself. For example, the feature information may include size information including the width and height of the semiconductor device. The feature information may include type information indicating whether the semiconductor device is a macro cell. Since the neural network model arranges semiconductor elements on the canvas in order of increasing size, the neural network model can be trained to arrange semiconductor elements on the canvas in order from macro cells to standard cells through type information. The characteristic information may include numerical information indicating the number of other devices connected to the semiconductor device. The characteristic information of this example may be understood as information for allowing the neural network model to identify a semiconductor device to be disposed at a specific time.

According to another embodiment of the present disclosure, the state to be input to the neural network model may include logical design information regarding the arrangement between semiconductor devices. For example, the logical design information may include index information regarding an arrangement order of the semiconductor devices. The neural network model can arrange semiconductor devices on the canvas in order of size through index information. The logical design information may include netlist information indicating a connection relationship between semiconductor devices. In this case, the netlist information may be data of a hypergraph structure. Since the data in the hypergraph structure is phenotypic data in a many-to-many relationship, the data itself has a fairly complex structure to analyze. Accordingly, the processor 110 may pre-process the netlist information of the hypergraph structure so that the neural network model can effectively process it.

Specifically, the processor 110 may convert the netlist information of the hypergraph structure into a universal graph structure in which the connection relationship between semiconductor devices is expressed one-to-one. For example, referring to FIG. 7 , the processor 110 may convert netlist information having a hypergraph structure 21 into netlist information having a universal graph structure 22 . In the case of the hypergraph structure 21, a drive cell 23 corresponding to an input device and a load cell 24 corresponding to an output device are all connected by one edge. to-many) structure. Conversely, the universal graph structure 22 corresponds to a structure in which the drive cell 23 and the load cell 24 have a one-to-one relationship such that two devices are connected to one edge. That is, the processor 110 may convert the netlist information of the hypergraph structure 21 into the universal graph structure 22 so that the drive cell 23 and the load cell 24 have a one-to-one relationship. The processor 110 may perform reinforcement learning by inputting a state including netlist information of the universal graph structure 22 generated through this transformation into the neural network model.

According to an embodiment of the present disclosure, the processor 110 may perform an action of arranging the semiconductor device on the canvas by inputting a state including the feature information and the information on the forbidden region to the neural network model. In this case, the act of disposing the semiconductor device on the canvas may include disposing a mask on the canvas and disposing the semiconductor device in one area of the canvas area where the mask is not disposed. For example, when performing an action of arranging a semiconductor device based on a state including characteristic information of the semiconductor device and information on the forbidden region, the processor 110 performs a grid of N*N (N is a natural number). You can apply a mask to the canvas space separated by ). The mask may include a first mask corresponding to a region in which the semiconductor device can leave the canvas, and a second mask corresponding to a region overlapping the semiconductor device already disposed on the canvas. When the mask is applied to the canvas, the processor 110 may perform an action of distributing the semiconductor device to the remaining area of the canvas to which the mask is not applied through the neural network model.

According to an embodiment of the present disclosure, the processor 110 may estimate a reward based on the behavior of the neural network model based on a state including the feature information and the information on the forbidden region. In this case, the reward may include a length of a wire connecting the semiconductor devices disposed on the canvas through the action, and the density of the semiconductor devices disposed on the canvas through the action. For example, the compensation may be calculated as a weighted sum of the length and density of the wire. The compensation calculated by the weighted sum of the length and density of the wire can be expressed as [Equation 1] as follows.

Here, p denotes a batch and g denotes a graph. And, R _p,g is compensation, α and β are coefficients for adjusting the overall scale, W(p,g) is the length of the wire, and C(p,g) is the density. As shown in [Equation 1], the compensation of the present disclosure may be derived through a weighted sum that flexibly controls the length of the wire and the size of the density through coefficients.

According to an embodiment of the present disclosure, the length of the wire may be calculated as half the circumference of a region in which elements having a connection relationship are disposed. For example, if it is assumed that there is one net (i.e. devices that have been arranged in a certain area of the canvas) in one rectangular area, half of the perimeter of the rectangular area encompassing the four is estimated as the length of the wire can be The processor 110 may estimate the total as the length of the wire after performing the above-described operation on all nets.

According to an embodiment of the present disclosure, the density is a first routing resource indicating a supply resource to which a wire can be allocated for each area of the canvas. A required resource for connecting semiconductor devices disposed on the canvas with a wire It may be calculated as a ratio of the second routing resource representing For example, the density may be expressed as [Equation 2] as follows.

Here, v denotes a grid cell, which is the basic unit of the canvas area. And, C(v) is a density, supply(v) is a first routing resource provided by a grid cell of the canvas, and demand(v) is a second routing resource required to connect semiconductor devices with wires. According to [Equation 2], since the density is proportional to the second routing resource, it can be expected that the overall density can be lowered by reducing the second routing resource.

The calculation process for estimating the above-described density will be described in more detail below with reference to FIGS. 8 to 16 .

The processor 110 according to an embodiment of the present disclosure may generate a complete graph indicating a state in which all the semiconductor devices disposed on the canvas are interconnected through an action. The processor 110 may transform the complete graph into a minimal spanning tree. The processor 110 converts the connection relationship of the complete graph into a minimum spanning tree, so that all elements are directly or indirectly connected with the minimum number of edges. Considering the PPA, since it can be assumed that the final routing result corresponding to the physical design of semiconductor devices approximately follows the shape of the minimum spanning tree, the processor 110 converts the complete graph into the minimum spanning tree to estimate the density can do. For example, if there are four semiconductor elements 51 , 52 , 53 , 54 disposed on the canvas 31 through an action, the processor 110 performs the four semiconductor elements 51 , 52 , 53, 54) can be created to create a complete graph. The processor 110 may convert the fully connected graph into a minimum spanning tree as shown in FIG. 9 . Here, the minimum spanning tree may be understood as a graph in which all four semiconductor devices 51 , 52 , 53 , and 54 are connected and the number and length of edges are minimized.

The processor 110 may calculate a routing resource for each edge constituting the minimum spanning tree. Here, the routing resource may be understood as a resource required for the connection of devices with a defined connection relationship to the edge. In detail, the processor 110 may calculate the number of cases in which the semiconductor devices are connected by wires on the canvas in consideration of the arrangement of the semiconductor devices corresponding to the nodes of the edge. The processor 110 may calculate an expected value of the shape in which the wire will be arranged on the canvas for each grid cell in consideration of the number of cases. In this case, the expected value for the shape in which the wire will be arranged on the canvas may include a first expected value at which the wire will be arranged vertically in a grid cell of the canvas, and a second expected value at which the wire will be arranged horizontally in the grid cell of the canvas. can The processor 110 may calculate a routing resource for each edge based on the calculated number of cases and the calculated expected value.

For example, referring to FIG. 9 , the processor 110 may divide the area of the grid cell necessary for calculating the routing resources of each of the three edges constituting the minimum spanning tree into areas ①, ②, and ③. have. The processor 110 may calculate a routing resource of each of the three edges based on each area. That is, the processor 110 may calculate a routing resource required for connection of devices whose connection relationship is defined as an edge for each of the regions ①, the regions ②, and the regions ③.

Looking at the region ①, the number of cases in which the two elements 51 and 52 present in the region ① can be connected with a wire can exist in six types, from (1-1) to (1-6) as shown in FIG. 10 . have. That is, the processor 110 may calculate the number of cases for physically connecting the elements based on the region ① into six types. Then, the processor 110 may calculate an expected value for the shape in which the wire is to be arranged on the canvas individually for the grid cells constituting the area ①. Referring to FIG. 11 , in the case of a grid cell (0,1), the number of cases for connecting two elements 51 and 52 is (1-1), (1-2), and (1-3). ) may be applicable. Therefore, for the grid cell (0,1), the processor 110 considers the number of three cases of (1-1), (1-2), and (1-3) to determine when the wire will be vertically placed. A first expected value that is an expected value and a second expected value that is an expected value at which the wires are horizontally arranged may be calculated. The processor 110 calculates and sums the result of calculating the probability of selecting each of the three cases and the routing resource related to the shape in which the wire is to be arranged in the grid cell (0,1) according to the number of the three cases, the first Each of the expected value and the second expected value may be calculated. At this time, the probability of selecting the number of each of the three cases is 1/6, which is the probability that one of the six paths for connecting the two elements 51 and 52 is randomly selected based on the region ①. Accordingly, the first expected value may be calculated as (1/6*1.0)+(1/6*0.5)+(1/6*0.5)=4/12. Also, the second expected value may be calculated as (0)+(1/6*0.5)+(1/6*0.5)=2/12. The processor 110 sets the first expected value and the second expected value calculated based on the grid cell (0,1) to the first expected value map 61 and the second expected value map ( 62) can be stored at the (0,1) position, respectively.

Referring to FIG. 11 , in the case of a grid cell (1,1), the number of cases for connecting two elements 51 and 52 is (1-2), (1-3), (1-5) and (1-6). Therefore, for the grid cell (1,1), the processor 110 considers the number of four cases: (1-2), (1-3), (1-5) and (1-6) to wire A first expected value, which is an expected value to be vertically arranged, and a second expected value, which is an expected value, to which the wire is horizontally arranged may be calculated. The processor 110 calculates and sums the result of calculating and summing the product of the routing resource regarding the shape in which the wire is to be arranged in the grid cell (1,1) according to the number of each of the four cases and the number of the three cases, the first Each of the expected value and the second expected value may be calculated. At this time, the probability of selecting the number of each of the four cases is 1/6, which is the probability that one of the six paths for connecting the two devices 51 and 52 is randomly selected based on the region ①. Accordingly, the first expected value may be calculated as (1/6*0.5)+(0)+(1/6*1.0)+(1/6*0.5)=4/12. Also, the second expected value may be calculated as (1/6*0.5)+(1/6*1.0)+(0)+(1/6*0.5)=4/12. The processor 110 sets the first expected value and the second expected value calculated based on the grid cell (1,1) to the first expected value map 61 and the second expected value map ( 62) can be stored at the position of (1,1), respectively.

The processor 110 calculates each expected value for all regions of the first expected value map 61 and the second expected value map 62 by performing the same operation as the above-described example for all grid cells in region ①. It can be stored as shown in FIG. 15 . In addition, the processor 110 performs the same operation as in the above-described example not only for the region ① but also for the region ② and the region ③, so that the first expected value map and the second expected value map for all three regions in which edges exist can create In this case, the first expected value map and the second expected value map of each region may correspond to each routing resource of the edge.

The processor 110 may accumulate the routing resources for each edge, and estimate the density based on a result value derived through the accumulated sum. Specifically, the processor 110 may estimate the second routing resource by averaging the values of the upper N% (N is a natural number) among the result values derived through the cumulative sum. The processor 110 may calculate a ratio with the first routing resource using the estimated second routing resource and estimate the density. The processor 110 may prevent a very high second routing resource from appearing in a specific area of the canvas by reflecting the value of the top N% of the accumulated sum of edge routing resources in estimating the density. That is, the processor 110 may allow the second routing resource to be evenly distributed in all canvas areas, so that the density of the entire canvas area may be appropriately reflected in the compensation.

For example, referring to FIG. 16 , the processor 110 applies the first expected value map and the second expected value map generated for all three regions in which an edge exists to a global map 81 indicating the entire canvas area. 82) can be reflected. In the process of reflecting each expected value map, the processor 110 may perform a cumulative sum on a region where each expected value map overlaps. That is, the expected values of the grid cells 3 and 7 in which the expected value maps 61 and 62 of the region ① and the expected value maps 71 and 72 of the region ② are overlapped are summed up in the global maps 81 and 82, respectively. It can be saved as 3/12 or 9/12. The processor 110 may update the global maps 81 and 82 for all edge regions as described above, and may use the highest 10% value as an estimate of the density by averaging the whole.

17 is a flowchart illustrating a method of disposing a semiconductor device based on user input information according to an embodiment of the present disclosure.

Referring to FIG. 17 , the computing device 100 according to an embodiment of the present disclosure may receive information on a forbidden region designated so that a semiconductor device is not disposed from a user interface ( S110 ). Also, the computing device 100 may receive characteristic information of the semiconductor device from an external system. The computing device 100 may use information received from a user interface and an external system as input data for learning a neural network model for disposing a semiconductor device. The computing device 100 may use the user interface and information received from the external system as input data for operation (inference) of a neural network model for disposing a semiconductor device. The usage mode of such information may be changed according to the purpose of learning or operation (inference) of the neural network model.

The computing device 100 may train the neural network model to arrange the semiconductor device based on the feature information and the information on the forbidden region ( S120 ). In this case, learning of the neural network model may be performed based on reinforcement learning. For example, the computing device 100 inputs the feature information and the information on the forbidden region to the neural network model to perform an action to place the semiconductor device on the canvas, and returns a reward according to the action to the neural network model for the neural network model. Reinforcement learning can be performed.

On the other hand, a computer-readable medium storing a data structure according to an embodiment of the present disclosure is disclosed.

The data structure may refer to the organization, management, and storage of data that enables efficient access and modification of data. A data structure may refer to an organization of data to solve a specific problem (eg, data retrieval, data storage, and data modification in the shortest time). A data structure may be defined as a physical or logical relationship between data elements designed to support a particular data processing function. The logical relationship between data elements may include a connection relationship between user-defined data elements. Physical relationships between data elements may include actual relationships between data elements physically stored on a computer-readable storage medium (eg, persistent storage). A data structure may specifically include a set of data, relationships between data, and functions or instructions applicable to data. Through an effectively designed data structure, a computing device can perform an operation while using the computing device's resources to a minimum. Specifically, the computing device may increase the efficiency of operations, reads, insertions, deletions, comparisons, exchanges, and retrievals through effectively designed data structures.

A data structure may be classified into a linear data structure and a non-linear data structure according to the type of the data structure. The linear data structure may be a structure in which only one piece of data is connected after one piece of data. The linear data structure may include a list, a stack, a queue, and a deck. A list may mean a set of data in which an order exists internally. The list may include a linked list. The linked list may be a data structure in which data is linked in such a way that each data is linked in a line with a pointer. In a linked list, a pointer may contain information about a link with the next or previous data. A linked list may be expressed as a single linked list, a doubly linked list, or a circularly linked list according to a shape. A stack can be a data enumeration structure with limited access to data. A stack can be a linear data structure in which data can be processed (eg, inserted or deleted) at only one end of the data structure. The data stored in the stack may be a data structure LIFO-Last in First Out. A queue is a data listing structure that allows limited access to data, and unlike a stack, it may be a data structure that comes out later (FIFO-First in First Out) as data stored later. A deck can be a data structure that can process data at either end of the data structure.

The nonlinear data structure may be a structure in which a plurality of data is connected after one data. The nonlinear data structure may include a graph data structure. A graph data structure may be defined as a vertex and an edge, and the edge may include a line connecting two different vertices. A graph data structure may include a tree data structure. The tree data structure may be a data structure in which one path connects two different vertices among a plurality of vertices included in the tree. That is, it may be a data structure that does not form a loop in the graph data structure.

The data structure may include a neural network. And the data structure including the neural network may be stored in a computer-readable medium. Data structures including neural networks also include preprocessed data for processing by the neural network, data input to the neural network, weights of the neural network, hyperparameters of the neural network, data obtained from the neural network, activation functions associated with each node or layer of the neural network, neural networks It may include a loss function for learning of . A data structure comprising a neural network may include any of the components disclosed above. That is, the data structure including the neural network includes preprocessed data for processing by the neural network, data input to the neural network, weights of the neural network, hyperparameters of the neural network, data obtained from the neural network, an activation function associated with each node or layer of the neural network, and a neural network. It may be configured to include all or any combination thereof, such as a loss function for learning of. In addition to the above-described configurations, a data structure including a neural network may include any other information that determines a characteristic of the neural network. In addition, the data structure may include all types of data used or generated in the operation process of the neural network, and is not limited thereto. Computer-readable media may include computer-readable recording media and/or computer-readable transmission media. A neural network may be composed of a set of interconnected computational units, which may generally be referred to as nodes. These nodes may also be referred to as neurons. A neural network is configured by including at least one or more nodes.

The data structure may include data input to the neural network. A data structure including data input to the neural network may be stored in a computer-readable medium. The data input to the neural network may include learning data input in a neural network learning process and/or input data input to the neural network in which learning is completed. Data input to the neural network may include pre-processing data and/or pre-processing target data. The preprocessing may include a data processing process for inputting data into the neural network. Accordingly, the data structure may include data to be pre-processed and data generated by pre-processing. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

The data structure may include the weights of the neural network. (In this specification, a weight and a parameter may be used interchangeably.) And a data structure including a weight of a neural network may be stored in a computer-readable medium. The neural network may include a plurality of weights. The weight may be variable, and may be changed by the user or algorithm in order for the neural network to perform a desired function. For example, when one or more input nodes are interconnected to one output node by respective links, the output node sets values input to input nodes connected to the output node and links corresponding to the respective input nodes. A data value output from the output node may be determined based on the weight. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

By way of example and not limitation, the weight may include a weight variable in a neural network learning process and/or a weight in which neural network learning is completed. The variable weight in the neural network learning process may include a weight at the start of the learning cycle and/or a variable weight during the learning cycle. The weight for which neural network learning is completed may include a weight for which a learning cycle is completed. Accordingly, the data structure including the weights of the neural network may include a data structure including the weights that vary in the neural network learning process and/or the weights on which the neural network learning is completed. Therefore, it is assumed that the above-described weights and/or combinations of weights are included in the data structure including the weights of the neural network. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

The data structure including the weights of the neural network may be stored in a computer-readable storage medium (eg, memory, hard disk) after being serialized. Serialization can be the process of converting a data structure into a form that can be reconstructed and used later by storing it on the same or a different computing device. The computing device may serialize the data structure to send and receive data over a network. A data structure including weights of the serialized neural network may be reconstructed in the same computing device or in another computing device through deserialization. The data structure including the weight of the neural network is not limited to serialization. Furthermore, the data structure including the weights of the neural network is a data structure to increase the efficiency of computation while using the resources of the computing device to a minimum (e.g., B-Tree, Trie, m-way search tree, AVL tree, Red-Black Tree). The foregoing is merely an example, and the present disclosure is not limited thereto.

The data structure may include hyper-parameters of the neural network. In addition, the data structure including the hyperparameters of the neural network may be stored in a computer-readable medium. The hyper parameter may be a variable variable by a user. Hyperparameters are, for example, learning rate, cost function, number of iterations of the learning cycle, weight initialization (e.g., setting the range of weight values subject to weight initialization), hidden unit The number (eg, the number of hidden layers, the number of nodes of the hidden layer) may be included. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

18 is a simplified, general conceptual diagram of an example computing environment in which embodiments of the present disclosure may be implemented.

Although the present disclosure has been described above generally as being capable of being implemented by a computing device, those skilled in the art will appreciate that the present disclosure is a combination of hardware and software and/or in combination with computer-executable instructions and/or other program modules that may be executed on one or more computers. It will be appreciated that it can be implemented as a combination.

Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In addition, those skilled in the art will appreciate that the methods of the present disclosure can be applied to single-processor or multiprocessor computer systems, minicomputers, mainframe computers as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and the like. It will be appreciated that each of these may be implemented in other computer system configurations, including those capable of operating in connection with one or more associated devices.

The described embodiments of the present disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

Computers typically include a variety of computer-readable media. Any medium accessible by a computer can be a computer-readable medium, and such computer-readable media includes volatile and nonvolatile media, transitory and non-transitory media, removable and non-transitory media. including removable media. By way of example, and not limitation, computer-readable media may include computer-readable storage media and computer-readable transmission media. Computer-readable storage media includes volatile and non-volatile media, temporary and non-transitory media, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. includes media. A computer-readable storage medium may be RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital video disk (DVD) or other optical disk storage device, magnetic cassette, magnetic tape, magnetic disk storage device, or other magnetic storage device. device, or any other medium that can be accessed by a computer and used to store the desired information.

Computer readable transmission media typically embodies computer readable instructions, data structures, program modules or other data, etc. in a modulated data signal such as a carrier wave or other transport mechanism, and Includes any information delivery medium. The term modulated data signal means a signal in which one or more of the characteristics of the signal is set or changed so as to encode information in the signal. By way of example, and not limitation, computer-readable transmission media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media. Combinations of any of the above are also intended to be included within the scope of computer-readable transmission media.

An exemplary environment 1100 implementing various aspects of the disclosure is shown including a computer 1102 , the computer 1102 including a processing unit 1104 , a system memory 1106 , and a system bus 1108 . do. A system bus 1108 couples system components, including but not limited to system memory 1106 , to the processing device 1104 . The processing device 1104 may be any of a variety of commercially available processors. Dual processor and other multiprocessor architectures may also be used as processing unit 1104 .

The system bus 1108 may be any of several types of bus structures that may further be interconnected to a memory bus, a peripheral bus, and a local bus using any of a variety of commercial bus architectures. System memory 1106 includes read only memory (ROM) 1110 and random access memory (RAM) 1112 . A basic input/output system (BIOS) is stored in non-volatile memory 1110, such as ROM, EPROM, EEPROM, etc., the BIOS is the basic input/output system (BIOS) that helps transfer information between components within computer 1102, such as during startup. contains routines. RAM 1112 may also include high-speed RAM, such as static RAM, for caching data.

The computer 1102 may also be configured for external use within an internal hard disk drive (HDD) 1114 (eg, EIDE, SATA) - this internal hard disk drive 1114 may also be configured for external use within a suitable chassis (not shown). Yes-, magnetic floppy disk drive (FDD) 1116 (eg, for reading from or writing to removable diskette 1118), and optical disk drive 1120 (eg, CD-ROM) for reading from, or writing to, disk 1122, or other high capacity optical media such as DVD. The hard disk drive 1114 , the magnetic disk drive 1116 , and the optical disk drive 1120 are connected to the system bus 1108 by the hard disk drive interface 1124 , the magnetic disk drive interface 1126 , and the optical drive interface 1128 , respectively. ) can be connected to The interface 1124 for implementing an external drive includes at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.

These drives and their associated computer readable media provide non-volatile storage of data, data structures, computer executable instructions, and the like. For computer 1102, drives and media correspond to storing any data in a suitable digital format. Although the description of computer readable media above refers to HDDs, removable magnetic disks, and removable optical media such as CDs or DVDs, those skilled in the art will use zip drives, magnetic cassettes, flash memory cards, cartridges, etc. It will be appreciated that other tangible computer-readable media such as etc. may also be used in the exemplary operating environment and any such media may include computer-executable instructions for performing the methods of the present disclosure.

A number of program modules may be stored in the drive and RAM 1112 , including an operating system 1130 , one or more application programs 1132 , other program modules 1134 , and program data 1136 . All or portions of the operating system, applications, modules, and/or data may also be cached in RAM 1112 . It will be appreciated that the present disclosure may be implemented in various commercially available operating systems or combinations of operating systems.

A user may enter commands and information into the computer 1102 via one or more wired/wireless input devices, for example, a pointing device such as a keyboard 1138 and a mouse 1140 . Other input devices (not shown) may include a microphone, IR remote control, joystick, game pad, stylus pen, touch screen, and the like. Although these and other input devices are often connected to the processing unit 1104 through an input device interface 1142 that is connected to the system bus 1108, parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, It may be connected by other interfaces, etc.

A monitor 1144 or other type of display device is also coupled to the system bus 1108 via an interface, such as a video adapter 1146 . In addition to the monitor 1144, the computer typically includes other peripheral output devices (not shown), such as speakers, printers, and the like.

Computer 1102 may operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) 1148 via wired and/or wireless communications. Remote computer(s) 1148 may be workstations, computing device computers, routers, personal computers, portable computers, microprocessor-based entertainment devices, peer devices, or other common network nodes, and are typically connected to computer 1102 . Although it includes many or all of the components described for it, only memory storage device 1150 is shown for simplicity. The logical connections shown include wired/wireless connections to a local area network (LAN) 1152 and/or a larger network, eg, a wide area network (WAN) 1154 . Such LAN and WAN networking environments are common in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which can be connected to a worldwide computer network, for example, the Internet.

When used in a LAN networking environment, the computer 1102 is connected to the local network 1152 through a wired and/or wireless communication network interface or adapter 1156 . Adapter 1156 may facilitate wired or wireless communication to LAN 1152 , which also includes a wireless access point installed therein for communicating with wireless adapter 1156 . When used in a WAN networking environment, the computer 1102 may include a modem 1158, be connected to a communications computing device on the WAN 1154, or establish communications over the WAN 1154, such as over the Internet. have other means. A modem 1158 , which may be internal or external and a wired or wireless device, is coupled to the system bus 1108 via a serial port interface 1142 . In a networked environment, program modules described for computer 1102 or portions thereof may be stored in remote memory/storage device 1150 . It will be appreciated that the network connections shown are exemplary and other means of establishing a communication link between the computers may be used.

Computer 1102 may be associated with any wireless device or object that is deployed and operates in wireless communication, eg, printers, scanners, desktop and/or portable computers, portable data assistants (PDAs), communication satellites, wireless detectable tags. It operates to communicate with any device or place, and phone. This includes at least Wi-Fi and Bluetooth wireless technologies. Accordingly, the communication may be a predefined structure as in a conventional network or may simply be an ad hoc communication between at least two devices.

Wi-Fi (Wireless Fidelity) makes it possible to connect to the Internet, etc. without a wire. Wi-Fi is a wireless technology such as cell phones that allows these devices, eg, computers, to transmit and receive data indoors and outdoors, ie anywhere within the coverage area of a base station. Wi-Fi networks use a radio technology called IEEE 802.11 (a, b, g, etc) to provide secure, reliable, and high-speed wireless connections. Wi-Fi can be used to connect computers to each other, to the Internet, and to wired networks (using IEEE 802.3 or Ethernet). Wi-Fi networks may operate in unlicensed 2.4 and 5 GHz radio bands, for example, at 11 Mbps (802.11a) or 54 Mbps (802.11b) data rates, or in products that include both bands (dual band). .

One of ordinary skill in the art of this disclosure will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, instructions, information, signals, bits, symbols, and chips that may be referenced in the above description are voltages, currents, electromagnetic waves, magnetic fields or particles, optical field particles or particles, or any combination thereof.

Those of ordinary skill in the art of the present disclosure will recognize that the various illustrative logical blocks, modules, processors, means, circuits and algorithm steps described in connection with the embodiments disclosed herein include electronic hardware, (convenience For this purpose, it will be understood that it may be implemented by various forms of program or design code (referred to herein as software) or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. A person skilled in the art of the present disclosure may implement the described functionality in various ways for each specific application, but such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

The various embodiments presented herein may be implemented as methods, apparatus, or articles of manufacture using standard programming and/or engineering techniques. The term article of manufacture includes a computer program, carrier, or media accessible from any computer-readable storage device. For example, computer-readable storage media include magnetic storage devices (eg, hard disks, floppy disks, magnetic strips, etc.), optical disks (eg, CDs, DVDs, etc.), smart cards, and flash drives. memory devices (eg, EEPROMs, cards, sticks, key drives, etc.). Also, various storage media presented herein include one or more devices and/or other machine-readable media for storing information.

It is understood that the specific order or hierarchy of steps in the presented processes is an example of exemplary approaches. Based on design priorities, it is to be understood that the specific order or hierarchy of steps in the processes may be rearranged within the scope of the present disclosure. The appended method claims present elements of the various steps in a sample order, but are not meant to be limited to the specific order or hierarchy presented.

The description of the presented embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments presented herein, but is to be construed in the widest scope consistent with the principles and novel features presented herein.

Claims (10)

A method of disposing a semiconductor device, performed by a computing device comprising at least one processor, the method comprising:
receiving information on a designated forbidden region in which a semiconductor device is not disposed; and
training a neural network model to arrange a semiconductor device based on the characteristic information of the semiconductor device and the information on the forbidden region;
including,
Receiving the information on the prohibited area comprises:
Receiving information on the prohibited area based on a user interface,
The user interface is
a first area displaying a canvas space divided by a grid; and
a second region for selecting a semiconductor device to which the forbidden region is to be applied;
comprising,
Way.
The method of claim 1,
The characteristic information is
size information including at least one of a width or a height of the semiconductor device; or
type information indicating whether the semiconductor device is a macro cell;
comprising at least one of
Way.
delete The method of claim 1,
designating the area as a prohibited area when input information of a user for selecting at least one space of the canvas displayed in the first area is received;
further comprising,
Way.
5. The method of claim 4,
The step of training the neural network model comprises:
training a neural network model so that a semiconductor device of a specific type or a specific size is not disposed in the forbidden region;
containing,
Way.
5. The method of claim 4,
The step of training the neural network model comprises:
when user input information for selecting a semiconductor device to be applied to the forbidden region is received through the second region, training a neural network model so that the selected semiconductor device is not placed in the forbidden region;
containing,
Way.
7. The method of claim 6,
Through the user interface, a plurality of semiconductor devices may be simultaneously selected as an application target of the forbidden region,
The step of training the neural network model comprises:
training a neural network model so that the plurality of semiconductor devices selected as the application target are not all disposed in the forbidden region;
further comprising,
Way.
The method of claim 1,
The step of training the neural network model comprises:
performing, through the neural network model, an action of arranging the semiconductor device based on a state including the feature information and information on the forbidden region;
estimating a reward for the action; and
performing reinforcement learning on the neural network model by returning the reward to the neural network model;
containing,
Way.
A computer program stored in a computer readable storage medium, wherein the computer program, when executed on one or more processors, performs the following operations for disposing a semiconductor device, the operations comprising:
receiving information on a designated forbidden region in which a semiconductor device is not disposed; and
training a neural network model to arrange a semiconductor device based on characteristic information of the semiconductor device and information on the forbidden region;
including,
The operation of receiving information on the prohibited area includes:
Receiving information on the prohibited area based on a user interface,
The user interface is
a first area displaying a canvas space divided by a grid; and
a second region for selecting a semiconductor device to which the forbidden region is to be applied;
containing,
A computer program stored on a computer-readable storage medium.
A computing device for disposing a semiconductor device, comprising:
a processor including at least one core;
a memory containing program codes executable by the processor; and
a network unit configured to receive information on a prohibited area designated so that semiconductor devices are not disposed;
including,
The network unit,
Receive information on the forbidden area based on the user interface,
The processor trains a neural network model to arrange a semiconductor device based on characteristic information of the semiconductor device and information on the forbidden region,
The user interface may include: a first area displaying a canvas space divided by a grid; and
a second region for selecting a semiconductor device to which the forbidden region is to be applied;
containing,
Device.

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