KR102440629B1 - Method for training a neural network model for semiconductor design - Google Patents

Abstract

According to one embodiment of the present disclosure, a method for semiconductor design performed by one or more processors of a computing device is disclosed. The method includes the steps of: identifying a region in which a semiconductor element cannot be placed based on information on the semiconductor element to be placed using a neural network model; and calculating a reward for the neural network model based on a region in which the semiconductor element cannot be placed.

Description

How to train a neural network model for semiconductor design

The present disclosure relates to a method of learning a neural network model for semiconductor design, and more particularly, to a method of determining a reward related to learning of a neural network model for semiconductor design.

This study was carried out as part of the private intelligent information service expansion project of the Ministry of Science and ICT and the Information and Communication Industry Promotion Agency (A0903-21-1021, AI-based semiconductor design automation system development).

Despite technological advances, the reality is that the logical design of semiconductors, which can be viewed as an integral part of the high-tech industry, is generally performed by engineers using rule-based software. Therefore, the logical design of semiconductors has to be performed based on the engineer's experience, and the design speed is inevitably different depending on the skill level of the engineer. In addition, it is practically very difficult for an engineer to efficiently arrange the connections between tens to millions of semiconductor devices in mind. That is, since the current semiconductor design process depends on the experience and intuition of an engineer, it is difficult to maintain a consistent design quality, and the time and money that must be invested for the design are inevitably required.

In addition, evaluation performed on tens to millions of disposed semiconductor devices also has high complexity. Since it takes a lot of time to evaluate each arrangement of several tens to millions of semiconductor elements, it is necessary to study a method for evaluating the arrangement of semiconductor elements that can reduce computational complexity.

Republic of Korea No. 10-0296183 (October 22, 2001) discloses a method for designing a semiconductor integrated circuit.

It is an object of the present disclosure to provide a method for determining a reward in connection with the training of a neural network model for semiconductor design.

Disclosed is a method performed by a computing device according to an embodiment of the present disclosure for realizing the above-described task. The method may include: using a neural network model, identifying a region in which the semiconductor device cannot be disposed based on information on a semiconductor device to be disposed; and calculating a reward for the neural network model based on a region in which the semiconductor device cannot be disposed.

Alternatively, the information on the semiconductor device may include: size information including at least one of a width or a height of the semiconductor device; type information indicating whether the semiconductor device is a macro cell; may include.

Alternatively, the information on the semiconductor device may include: index information on an arrangement order of the semiconductor device; may include.

Alternatively, the neural network model is based on a state including information on semiconductor devices, an action of arranging the semiconductor devices on the canvas in a predetermined order, and a reward for the action. It can be learned through reinforcement learning.

Alternatively, the neural network model may identify a region in which the semiconductor device cannot be disposed based on disposition information of one or more semiconductor devices disposed before the semiconductor device and an arrangement order of the semiconductor device.

Alternatively, the reward for the neural network model may include a negative reward determined in proportion to a size of an area in which the semiconductor device cannot be disposed.

Alternatively, the compensation for the neural network model may include: a first negative compensation determined based on a size of a region in which the first semiconductor device cannot be disposed; and a second negative compensation determined based on a size of a region in which a second semiconductor device to be disposed after the first semiconductor device cannot be disposed.

Alternatively, the reward for the neural network model may include a reward corresponding to a lower limit value of a negative reward when the region in which the semiconductor device cannot be disposed corresponds to the entire region.

Alternatively, the neural network model may end the collection of information on the reinforcement learning path when the region in which the semiconductor device cannot be disposed corresponds to the entire region.

Disclosed is a computer program stored in a computer-readable storage medium according to an embodiment of the present disclosure for realizing the above-described problems. When the computer program is executed in one or more processors, the one or more processors cause the one or more processors to perform operations for designing a semiconductor, wherein the operations are performed on the semiconductor device based on information about a semiconductor device to be deployed using a neural network model. identifying an area in which a device cannot be placed; and calculating a reward for the neural network model based on a region in which the semiconductor device cannot be disposed.

Disclosed is a computing device according to an embodiment of the present disclosure for realizing the above-described problems. The apparatus includes at least one processor; and a memory, wherein the processor is configured to: identify a region in which the semiconductor device cannot be disposed based on information on a semiconductor device to be disposed using a neural network model; And it may be configured to calculate a compensation for the neural network model based on a region in which the semiconductor device cannot be disposed.

The present disclosure may provide a method for determining a reward in relation to learning of a neural network model for semiconductor design, and through this, an optimized semiconductor design technology utilizing a neural network model may be provided.

1 is a block diagram of a computing device for setting reinforcement learning compensation of a neural network model according to an embodiment of the present disclosure.
2 is a schematic diagram illustrating a network function according to an embodiment of the present disclosure;
3 is a conceptual diagram illustrating a reinforcement learning process of a neural network model according to an embodiment of the present disclosure.
4 is a flowchart illustrating a method for learning a neural network model for semiconductor design according to an embodiment of the present disclosure.
5 is a flowchart illustrating a method of evaluating the arrangement of a semiconductor device according to an embodiment of the present disclosure.
6 is an algorithm flowchart illustrating step A among the steps of calculating and providing a reward for a neural network model according to an embodiment of the present disclosure.
7 is an algorithm flowchart illustrating step B among the steps of calculating and providing a reward for a neural network model according to an embodiment of the present disclosure.
8 is a simplified, general schematic diagram of an exemplary computing environment in which embodiments of the present disclosure may be implemented.

Various embodiments are now described with reference to the drawings. In this specification, various descriptions are presented to provide an understanding of the present disclosure. However, it is apparent that these embodiments may be practiced without these specific descriptions.

The terms “component,” “module,” “system,” and the like, as used herein, refer to a computer-related entity, hardware, firmware, software, a combination of software and hardware, or execution of software. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, a thread of execution, a program, and/or a computer. For example, both an application running on a computing device and the computing device may be a component. One or more components may reside within a processor and/or thread of execution. A component may be localized within one computer. A component may be distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored therein. Components may communicate via a network such as the Internet with another system, for example via a signal having one or more data packets (eg, data and/or signals from one component interacting with another component in a local system, distributed system, etc.) may communicate via local and/or remote processes depending on the data being transmitted).

In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from context, "X employs A or B" is intended to mean one of the natural implicit substitutions. That is, X employs A; X employs B; or when X employs both A and B, "X employs A or B" may apply to either of these cases. It should also be understood that the term “and/or” as used herein refers to and includes all possible combinations of one or more of the listed related items.

Also, the terms "comprises" and/or "comprising" should be understood to mean that the feature and/or element in question is present. However, it should be understood that the terms "comprises" and/or "comprising" do not exclude the presence or addition of one or more other features, elements and/or groups thereof. Also, unless otherwise specified or unless it is clear from context to refer to a singular form, the singular in the specification and claims should generally be construed to mean “one or more”.

And, the term "at least one of A or B" should be interpreted to mean "when including only A", "when including only B", and "when combined with the configuration of A and B".

Those skilled in the art will further appreciate that the various illustrative logical blocks, configurations, modules, circuits, means, logics, and algorithm steps described in connection with the embodiments disclosed herein may be implemented in electronic hardware, computer software, or combinations of both. It should be recognized that they can be implemented with To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, means, logics, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application. However, such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Descriptions of the presented embodiments are provided to enable those skilled in the art to use or practice the present invention. Various modifications to these embodiments will be apparent to those skilled in the art of the present disclosure. The generic principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Thus, the present invention is not limited to the embodiments presented herein. The invention is to be construed in its widest scope consistent with the principles and novel features presented herein.

In the present disclosure, a network function, an artificial neural network, and a neural network may be used interchangeably.

1 is a block diagram of a computing device for setting reinforcement learning compensation of a neural network model for semiconductor design according to an embodiment of the present disclosure.

The configuration of the computing device 100 shown in FIG. 1 is only a simplified example. In an embodiment of the present disclosure, the computing device 100 may include other components for performing the computing environment of the computing device 100 , and only some of the disclosed components may configure the computing device 100 .

The computing device 100 may include a processor 110 , a memory 130 , and a network unit 150 .

The processor 110 may include one or more cores, and a central processing unit (CPU) of a computing device, a general purpose graphics processing unit (GPGPU), and a tensor processing unit (TPU). unit) and the like, and may include a processor for data analysis and deep learning. The processor 110 may read a computer program stored in the memory 130 to perform data processing for machine learning according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the processor 110 may perform an operation for learning the neural network. The processor 110 for learning of the neural network, such as processing input data for learning in deep learning (DL), extracting features from the input data, calculating an error, updating the weight of the neural network using backpropagation calculations can be performed. At least one of a CPU, a GPGPU, and a TPU of the processor 110 may process learning of a network function. For example, the CPU and the GPGPU can process learning of a network function and data classification using the network function. Also, in an embodiment of the present disclosure, learning of a network function and data classification using the network function may be processed by using the processors of a plurality of computing devices together. In addition, the computer program executed in the computing device according to an embodiment of the present disclosure may be a CPU, GPGPU or TPU executable program.

The processor 110 according to an embodiment of the present disclosure recognizes information about a semiconductor device for semiconductor design, identifies a placeable region of the device, and compensates for reinforcement learning of a neural network model based on the identified region. Calculation operations may be performed. In this case, the information about the semiconductor device may be information about the device itself or information about the arrangement order of the device. For example, the processor 110 may use a neural network model to identify a region in which the semiconductor device cannot be disposed, based on information about a semiconductor device to be disposed. In this case, the information about the device may be at least one of size information including at least one of a width or a height of the semiconductor device, or type information of the semiconductor device. In addition, the information on the device may be index information regarding an arrangement order of the semiconductor device.

According to an embodiment of the present disclosure, the processor 110 is configured to generate a state including information on a semiconductor device, an action for arranging the semiconductor device in a predetermined order, and a reward for the action. Through reinforcement learning, a neural network model can be trained.

In addition, the processor 110 uses a neural network model to identify a region in which the semiconductor device cannot be disposed based on information about the semiconductor device to be disposed, and a region in which the semiconductor device cannot be disposed. It is possible to calculate a reward for the neural network model based on , and return it along with the state. Through this, reinforcement learning can be performed on the neural network model by allowing the neural network model to perform an action according to the next cycle.

According to an embodiment of the present disclosure, the memory 130 may store any type of information generated or determined by the processor 110 and any type of information received by the network unit 150 .

According to an embodiment of the present disclosure, the memory 130 is a flash memory type, a hard disk type, a multimedia card micro type, and a card type memory (eg, For example, SD or XD memory), Random Access Memory (RAM), Static Random Access Memory (SRAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Programmable Read (PROM) -Only Memory), a magnetic memory, a magnetic disk, and an optical disk may include at least one type of storage medium. The computing device 100 may operate in relation to a web storage that performs a storage function of the memory 130 on the Internet. The description of the above-described memory is only an example, and the present disclosure is not limited thereto.

The network unit 150 according to an embodiment of the present disclosure may use any type of known wired/wireless communication system.

For example, the network unit 150 may receive information about the semiconductor device from an external system. In this case, the information received from the database may be data for training or data for inference of a neural network model. The information on the semiconductor device may include the information of the above-described examples, but is not limited to the above-described examples, and may be variously configured within a range that can be understood by those skilled in the art.

In addition, the network unit 150 may transmit and receive information processed by the processor 110 , a user interface, and the like through communication with another terminal. For example, the network unit 150 may provide a user interface generated by the processor 110 to a client (e.g. a user terminal). Also, the network unit 150 may receive an external input of a user authorized as a client and transmit it to the processor 110 . In this case, the processor 110 may process an operation of outputting, modifying, changing, or adding information provided through the user interface based on the user's external input received from the network unit 150 .

Meanwhile, the computing device 100 according to an embodiment of the present disclosure may include a server as a computing system for transmitting and receiving information through communication with a client. In this case, the client may be any type of terminal that can access the server. For example, the computing device 100 as a server may receive information for semiconductor design from an external database, generate a logical design result, and provide a user interface related to the logical design result to the user terminal. In this case, the user terminal may output a user interface received from the computing device 100 which is a server, and may receive or process information through interaction with the user.

In an additional embodiment, the computing device 100 may include any type of terminal that receives a data resource generated by an arbitrary server and performs additional information processing.

2 is a schematic diagram illustrating a network function according to an embodiment of the present disclosure;

Throughout this specification, computational model, neural network, network function, and neural network may be used interchangeably. A neural network may be composed of a set of interconnected computational units, which may generally be referred to as nodes. These nodes may also be referred to as neurons. A neural network is configured to include at least one or more nodes. Nodes (or neurons) constituting the neural networks may be interconnected by one or more links.

In the neural network, one or more nodes connected through a link may relatively form a relationship between an input node and an output node. The concepts of an input node and an output node are relative, and any node in an output node relationship with respect to one node may be in an input node relationship in a relationship with another node, and vice versa. As described above, an input node-to-output node relationship may be created around a link. One or more output nodes may be connected to one input node through a link, and vice versa.

In the relationship between the input node and the output node connected through one link, the value of the data of the output node may be determined based on data input to the input node. Here, a link interconnecting the input node and the output node may have a weight. The weight may be variable, and may be changed by the user or algorithm in order for the neural network to perform a desired function. For example, when one or more input nodes are interconnected to one output node by respective links, the output node sets values input to input nodes connected to the output node and links corresponding to the respective input nodes. An output node value may be determined based on the weight.

As described above, in a neural network, one or more nodes are interconnected through one or more links to form an input node and an output node relationship in the neural network. The characteristics of the neural network may be determined according to the number of nodes and links in the neural network, the correlation between the nodes and the links, and the value of a weight assigned to each of the links. For example, when the same number of nodes and links exist and there are two neural networks having different weight values of the links, the two neural networks may be recognized as different from each other.

A neural network may consist of a set of one or more nodes. A subset of nodes constituting the neural network may constitute a layer. Some of the nodes constituting the neural network may configure one layer based on distances from the initial input node. For example, a set of nodes having a distance n from the initial input node may constitute n layers. The distance from the initial input node may be defined by the minimum number of links that must be traversed to reach the corresponding node from the initial input node. However, the definition of such a layer is arbitrary for description, and the order of the layer in the neural network may be defined in a different way from the above. For example, a layer of nodes may be defined by a distance from the final output node.

The initial input node may mean one or more nodes to which data is directly input without going through a link in a relationship with other nodes among nodes in the neural network. Alternatively, in a relationship between nodes based on a link in a neural network, it may mean nodes that do not have other input nodes connected by a link. Similarly, the final output node may refer to one or more nodes that do not have an output node in relation to other nodes among nodes in the neural network. In addition, the hidden node may mean nodes constituting the neural network other than the first input node and the last output node.

The neural network according to an embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be the same as the number of nodes in the output layer, and the number of nodes decreases and then increases again as the input layer progresses to the hidden layer. can In addition, the neural network according to another embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be less than the number of nodes in the output layer, and the number of nodes decreases as the number of nodes progresses from the input layer to the hidden layer. have. In addition, the neural network according to another embodiment of the present disclosure may be a neural network in which the number of nodes in the input layer may be greater than the number of nodes in the output layer, and the number of nodes increases as the number of nodes progresses from the input layer to the hidden layer. can The neural network according to another embodiment of the present disclosure may be a neural network in a combined form of the aforementioned neural networks.

A deep neural network (DNN) may refer to a neural network including a plurality of hidden layers in addition to an input layer and an output layer. Deep neural networks can be used to identify the latent structures of data. In other words, it can identify the potential structure of photos, texts, videos, voices, and music (e.g., what objects are in the photos, what the text and emotions are, what the texts and emotions are, etc.) . Deep neural networks include convolutional neural networks (CNNs), recurrent neural networks (RNNs), auto encoders, generative adversarial networks (GANs), and restricted boltzmann machines (RBMs). machine), a deep belief network (DBN), a Q network, a U network, a Siamese network, and a Generative Adversarial Network (GAN). The description of the deep neural network described above is only an example, and the present disclosure is not limited thereto.

In an embodiment of the present disclosure, the network function may include an autoencoder. The auto-encoder may be a kind of artificial neural network for outputting output data similar to input data. The auto encoder may include at least one hidden layer, and an odd number of hidden layers may be disposed between the input/output layers. The number of nodes in each layer may be reduced from the number of nodes in the input layer to an intermediate layer called the bottleneck layer (encoding), and then expanded symmetrically with reduction from the bottleneck layer to the output layer (symmetrical to the input layer). Autoencoders can perform non-linear dimensionality reduction. The number of input layers and output layers may correspond to a dimension after preprocessing the input data. In the auto-encoder structure, the number of nodes of the hidden layer included in the encoder may have a structure that decreases as the distance from the input layer increases. If the number of nodes in the bottleneck layer (the layer with the fewest nodes between the encoder and decoder) is too small, a sufficient amount of information may not be conveyed, so a certain number or more (e.g., more than half of the input layer, etc.) ) may be maintained.

The neural network may be trained using at least one of supervised learning, unsupervised learning, semi-supervised learning, and reinforcement learning. Learning of the neural network may be a process of applying knowledge for the neural network to perform a specific operation to the neural network.

A neural network can be trained in a way that minimizes output errors. In the training of a neural network, iteratively input the training data into the neural network, calculate the output of the neural network and the target error for the training data, and calculate the error of the neural network from the output layer of the neural network to the input layer in the direction to reduce the error. It is the process of updating the weight of each node of the neural network by backpropagation in the direction. In the case of teacher learning, learning data in which the correct answer is labeled in each learning data is used (ie, labeled learning data), and in the case of comparative learning, the correct answer may not be labeled in each learning data. That is, for example, the learning data in the case of teacher learning regarding data classification may be data in which categories are labeled for each of the learning data. Labeled training data is input to the neural network, and an error can be calculated by comparing the output (category) of the neural network with the label of the training data. As another example, in the case of comparison learning about data classification, an error may be calculated by comparing the input training data with the output of the neural network. The calculated error is back propagated in the reverse direction (ie, from the output layer to the input layer) in the neural network, and the connection weight of each node of each layer of the neural network may be updated according to the back propagation. A change amount of the connection weight of each node to be updated may be determined according to a learning rate. The computation of the neural network on the input data and the backpropagation of errors can constitute a learning cycle (epoch). The learning rate may be applied differently depending on the number of repetitions of the learning cycle of the neural network. For example, in the early stage of learning of a neural network, a high learning rate can be used to enable the neural network to quickly acquire a certain level of performance, thereby increasing efficiency, and using a low learning rate at the end of learning can increase accuracy.

In training of a neural network, in general, the training data may be a subset of real data (that is, data to be processed using the trained neural network), and thus the error on the training data is reduced, but the error on the real data is reduced. There may be increasing learning cycles. Overfitting is a phenomenon in which errors on actual data increase by over-learning on training data as described above. For example, a phenomenon in which a neural network that has learned a cat by seeing a yellow cat does not recognize that it is a cat when it sees a cat other than yellow may be a type of overfitting. Overfitting can act as a cause of increasing errors in machine learning algorithms. In order to prevent such overfitting, various optimization methods can be used. In order to prevent overfitting, methods such as increasing the training data, regularization, and dropout that deactivate some of the nodes of the network in the process of learning, and the use of a batch normalization layer are applied. can

3 to 7 are conceptual diagrams for explaining a reinforcement learning process of a neural network model according to an embodiment of the present disclosure.

Reinforcement learning is a learning method of learning a neural network model based on a reward calculated for an action selected by the neural network model so that the neural network model can determine a better action based on a state. A state is a set of values indicating what the situation is at the present time, and can be understood as an input to a neural network model. Behavior refers to a decision based on the options that a neural network model can take, and can be understood as an output of a neural network model. The reward refers to the gain that follows when the neural network model performs a certain action, and represents the value evaluated for the current state and action. Reinforcement learning can be understood as learning through trial and error in that actions are rewarded. The reward given to the neural network model in the reinforcement learning process may be a reward that accumulates the results of several actions. Through reinforcement learning, it is possible to create a neural network model that maximizes the return such as the reward itself or the sum of the rewards by considering the rewards according to various states and actions.

Referring to FIG. 3 , in reinforcement learning, there are a neural network model 210 and a result 220 of the model's behavior. The action result 220 may be understood as meaning information necessary for reinforcement learning of the neural network model 210 . When the neural network model 210 performs an action, the state of the result is changed to the result 220 for the action, and the model 210 may receive a reward for the action. The goal of reinforcement learning is to train the neural network model 210 to receive as many rewards as possible from the results 220 for actions.

According to an embodiment of the present disclosure, the processor 110 is configured to generate a state including information on a semiconductor device, an action for arranging the semiconductor device in a predetermined order, and a reward for the action. Through reinforcement learning, a neural network model can be trained.

The processor 110 uses the neural network model to identify a region in which the semiconductor device cannot be disposed based on information about the semiconductor device to be disposed, and based on the region in which the semiconductor device cannot be disposed. Thus, the reward for the neural network model can be calculated and returned along with the state. Through this, reinforcement learning can be performed on the neural network model by allowing the neural network model to perform an action according to the next cycle.

For example, the processor 110 may perform an n-th action of arranging the semiconductor device on the canvas through the neural network model. The processor 110 may estimate a reward Rn for an n-th action in a specific order, and return a state Sn and an estimated reward Rn of a result of the action to the neural network model. The processor 110 may perform the n+1-th action at the next time point by inputting the result state and reward for the n-th action in a specific order into the neural network model. The processor 110 may repeat this cycle to perform reinforcement learning on the neural network model to optimize the design of the semiconductor.

4 is a flowchart illustrating a method for learning a neural network model for semiconductor design according to an embodiment of the present disclosure.

Referring to FIG. 4 , the computing device 100 according to an embodiment of the present disclosure may receive information on a semiconductor device from an external system ( S110 ). The external system may be a server, a database, or the like that stores and manages information for logical design of a semiconductor. The computing device 100 may use information received from an external system as input data for learning a neural network model for semiconductor design. The computing device 100 may use information received from an external system as input data for operation (inference) of a neural network model for semiconductor design. The usage mode of such information may be changed according to the purpose of learning or operation (inference) of the neural network model.

The computing device 100 may train the neural network model to arrange the semiconductor devices on the canvas in a predetermined order based on the information on the semiconductor devices ( S120 ). In this case, learning of the neural network model may be performed based on reinforcement learning. For example, the computing device 100 inputs information about semiconductor devices into the neural network model, performs an action of arranging semiconductor devices on the canvas in a predetermined order, and returns a reward according to the behavior to the neural network model to model the neural network model. can perform reinforcement learning.

The computing device 100 uses the neural network model learned through step S120 to generate the devices in a predetermined order based on the arrangement information of one or more semiconductor devices disposed before the semiconductor device and the arrangement order of the semiconductor devices. When disposing on the canvas, an area in which a semiconductor device cannot be disposed may be identified ( S130 ). The computing device 100 may effectively place the semiconductor device on the canvas by learning the neural network model through one of A and B neural network model compensation granting steps based on the region identified in step S130 . The computing device 100 may reduce variations in design cost and design quality, which are problems with the existing design method, by using the neural network model learned through reinforcement learning.

According to an embodiment of the present disclosure, the state to be input to the neural network model may include information indicating characteristics of the semiconductor device itself. For example, the information indicating the characteristics of the device itself may include size information including the width and height of the semiconductor device. The information indicating the characteristic may include type information indicating whether the semiconductor device is a macro cell. The information in this example may be understood as information for allowing the neural network model to identify a semiconductor device to be disposed at a specific point in time.

According to an embodiment of the present disclosure, the state to be input to the neural network model may include information about the arrangement between semiconductor devices. For example, the information regarding the arrangement may include index information regarding the arrangement order of the semiconductor devices. The neural network model may be trained to arrange semiconductor devices on the canvas in a predetermined order through index information.

According to an embodiment of the present disclosure, the processor 110 may input a state including information of the semiconductor device to the neural network model and perform an action of arranging the semiconductor device on the canvas in a predetermined order. At this time, the action of arranging the semiconductor elements on the canvas is to apply a mask to the canvas in the area where the semiconductor elements up to the previous order are already located or there is not enough space to place the elements in a specific order. place it, The method may include disposing a semiconductor device on a canvas area where a mask is not disposed. Specifically, referring to FIG. 5 , when performing an action of arranging a semiconductor device based on a state including information on the semiconductor device, the processor 110 generates a grid of N*N (N is a natural number). A mask can be applied to the separated canvas space. The mask may include a region in which the semiconductor device may leave the canvas and a region 21 overlapping the semiconductor device already disposed on the canvas. When the mask is applied to the canvas, the processor 110 may perform an action of disposing the semiconductor device in the remaining area 31 of the canvas to which the mask is not applied through the neural network model. For example, when the device 51 of the following order is disposed in the canvas space in which two devices are disposed, the neural network model of the processor 110 includes the masks 21 based on the state including the information of the semiconductor device. An action of arranging the elements 51 in the following order in the region 31 other than the region to be used can be performed. By applying such a mask, the neural network model can perform efficient and accurate actions in consideration of the physical environment of the canvas.

Additionally, when the devices are disposed according to a predetermined order, the size of a region in which the semiconductor device 51 of the next sequence can be disposed varies according to the position of the device 41 disposed in the immediately preceding sequence. At this time, depending on the position of the elements arranged in the previous order, a case 61 (that is, the case of the All Zero Mask) may occur where an area in which the elements of the next order cannot be arranged corresponds to the entire canvas space. When such a case (61) occurs, since the device cannot be disposed any more, in order to increase the semiconductor design efficiency, the neural network model must be trained to exclude the case (61) in which the entire region in which the device cannot be disposed is the entirety.

According to an embodiment of the present disclosure, the processor 110 may estimate the reward based on the behavior of the neural network model based on the state including the information of the semiconductor device.

In this case, the step of calculating and providing a reward to the neural network model includes either step A corresponding to FIG. 6 or step B corresponding to FIG. 7 , but is not limited thereto.

According to an embodiment of the present disclosure, the reward for the neural network model may include a reward corresponding to a lower limit value of a negative reward when the region in which the semiconductor device cannot be disposed corresponds to the entire region. . In addition, the neural network model may stop collecting information on reinforcement learning when the region in which the semiconductor device cannot be disposed corresponds to the entire region.

Referring to FIGS. 5 and 6 , FIG. 6 is an algorithm flow chart 210 illustrating step A among the steps of calculating and providing a reward for the neural network model.

Specifically, the processor 110 identifies a region in which a semiconductor device cannot be disposed based on the arrangement information and the arrangement order of the semiconductor device, and the order of the devices initially disposed in the step of providing a compensation for the neural network model is set to 1. is granted (211) Next, the first element is placed in an area other than the identified non-placeable area. (212) At this time, the neural network model determines whether an area in which the elements of the next order cannot be disposed corresponds to the entire area. (213)

After determining the correspondence, if the region in which the semiconductor element cannot be arranged is not the entire region, the order of the arranged elements is assigned to 2. (214) This process is repeated until the area in which the elements of the next order cannot be placed corresponds to the entire area.

If the area in which the next element cannot be arranged corresponds to the entire area, a negative compensation of the lower limit may be given to the neural network model. (215) In this case, the compensation may include a length of a wire connecting the semiconductor devices disposed on the canvas through the action, and congestion of the semiconductor devices disposed on the canvas through the action. For example, the compensation may be calculated as a weighted sum of the length of the wire and the degree of congestion. Specifically, as for the negative compensation of the lower limit, the lower limit of the negative compensation may be given as -2 from the lower limit of -1 of the half-perimeter wirelength ( HPWL) compensation and the lower limit of -1 of the congestion compensation. When the non-placeable region is the whole, the case of the entire non-placeable region can be induced to be excluded from the reinforcement learning process by giving a negative compensation of the lower limit to the neural network model. Additionally, when the non-placeable region is the whole, the neural network model may include collecting information about the reinforcement learning path and terminating reinforcement learning. (216) It is possible to increase the semiconductor design efficiency by inducing that the case where the next semiconductor device cannot be arranged is excluded from the reinforcement learning process.

Referring to FIGS. 5 and 7 , FIG. 7 is an algorithm flowchart 310 illustrating step B among the steps of calculating and providing a reward for the neural network model.

Specifically, the processor 110 identifies a region in which a semiconductor device cannot be disposed based on the arrangement information and the arrangement order of the semiconductor device, and the order of the devices initially disposed in the step of providing a compensation for the neural network model is set to 1. is granted (311) Next, the first element is placed in an area other than the identified non-placeable area. (312) In this case, the reward for the neural network model may include a negative reward determined in proportion to the size of a region in which the semiconductor device cannot be disposed. (313) Specifically, the compensation for the neural network model includes an nth negative compensation determined based on the size of a region in which an nth semiconductor device cannot be disposed, and an n+th compensation to be disposed after the nth semiconductor device. An n+1th negative reward determined based on the size of a region in which the first semiconductor device cannot be disposed may be included. For example, the negative reward determined in proportion to the size of the region in which the semiconductor device cannot be disposed includes a case where it is calculated as one of the following equations. The expressed equations are only examples, and the negative compensation is not limited thereto.

[Equation 1]

[Equation 2]

Thereafter, the neural network model determines whether an area in which elements of the next order cannot be placed corresponds to the entire area. (314) After determining whether or not the semiconductor device is not disposed, the order of the devices is given as 2 if the area in which the semiconductor device cannot be disposed is not the entire area. (315) This process is repeated until the area in which the elements of the next order cannot be placed corresponds to the entire area. If the region in which the next device cannot be arranged corresponds to the entire region, the method may include terminating the training of the neural network model. (316) The semiconductor design efficiency can be improved by learning the neural network model in the direction of expanding the size of the area where the next element can be placed whenever semiconductor elements in a specific order are arranged.

A computer-readable medium storing a data structure is disclosed according to an embodiment of the present disclosure.

The data structure may refer to the organization, management, and storage of data that enables efficient access and modification of data. A data structure may refer to an organization of data to solve a specific problem (eg, data retrieval, data storage, and data modification in the shortest time). A data structure may be defined as a physical or logical relationship between data elements designed to support a particular data processing function. The logical relationship between data elements may include a connection relationship between user-defined data elements. Physical relationships between data elements may include actual relationships between data elements physically stored on a computer-readable storage medium (eg, persistent storage). A data structure may specifically include a set of data, relationships between data, and functions or instructions applicable to data. Through an effectively designed data structure, a computing device can perform an operation while using the computing device's resources to a minimum. Specifically, the computing device may increase the efficiency of operations, reads, insertions, deletions, comparisons, exchanges, and retrievals through effectively designed data structures.

A data structure may be classified into a linear data structure and a non-linear data structure according to the type of the data structure. The linear data structure may be a structure in which only one piece of data is connected after one piece of data. The linear data structure may include a list, a stack, a queue, and a deck. A list may mean a set of data in which an order exists internally. The list may include a linked list. The linked list may be a data structure in which data is linked in such a way that each data is linked in a line with a pointer. In a linked list, a pointer may contain information about a link with the next or previous data. A linked list may be expressed as a single linked list, a doubly linked list, or a circularly linked list according to a shape. A stack can be a data enumeration structure with limited access to data. A stack can be a linear data structure in which data can be processed (eg, inserted or deleted) at only one end of the data structure. The data stored in the stack may be a data structure LIFO-Last in First Out. A queue is a data listing structure that allows limited access to data, and unlike a stack, it may be a data structure that comes out later (FIFO-First in First Out) as data stored later. A deck can be a data structure that can process data at either end of the data structure.

The nonlinear data structure may be a structure in which a plurality of data is connected after one data. The nonlinear data structure may include a graph data structure. A graph data structure may be defined as a vertex and an edge, and the edge may include a line connecting two different vertices. A graph data structure may include a tree data structure. The tree data structure may be a data structure in which one path connects two different vertices among a plurality of vertices included in the tree. That is, it may be a data structure that does not form a loop in the graph data structure.

Throughout this specification, computational model, neural network, network function, and neural network may be used interchangeably. Hereinafter, the neural network is unified and described. The data structure may include a neural network. And the data structure including the neural network may be stored in a computer-readable medium. Data structures, including neural networks, also include preprocessed data for processing by the neural network, data input to the neural network, weights of the neural network, hyperparameters of the neural network, data obtained from the neural network, activation functions associated with each node or layer of the neural network, and the neural network. It may include a loss function for learning of . A data structure comprising a neural network may include any of the components disclosed above. That is, the data structure including the neural network includes preprocessed data for processing by the neural network, data input to the neural network, weights of the neural network, hyperparameters of the neural network, data obtained from the neural network, activation functions associated with each node or layer of the neural network, and the neural network It may be configured to include all or any combination thereof, such as a loss function for learning of . In addition to the above-described configurations, a data structure including a neural network may include any other information that determines a characteristic of the neural network. In addition, the data structure may include all types of data used or generated in the operation process of the neural network, and is not limited thereto. Computer-readable media may include computer-readable recording media and/or computer-readable transmission media. A neural network may be composed of a set of interconnected computational units, which may generally be referred to as nodes. These nodes may also be referred to as neurons. A neural network is configured to include at least one or more nodes.

The data structure may include data input to the neural network. A data structure including data input to the neural network may be stored in a computer-readable medium. The data input to the neural network may include learning data input in a neural network learning process and/or input data input to the neural network in which learning is completed. Data input to the neural network may include pre-processing data and/or pre-processing target data. The preprocessing may include a data processing process for inputting data into the neural network. Accordingly, the data structure may include data to be pre-processed and data generated by pre-processing. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

The data structure may include the weights of the neural network. (In this specification, a weight and a parameter may be used interchangeably.) And a data structure including a weight of a neural network may be stored in a computer-readable medium. The neural network may include a plurality of weights. The weight may be variable, and may be changed by the user or algorithm in order for the neural network to perform a desired function. For example, when one or more input nodes are interconnected to one output node by respective links, the output node sets values input to input nodes connected to the output node and links corresponding to the respective input nodes. A data value output from the output node may be determined based on the weight. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

By way of example and not limitation, the weight may include a weight variable in a neural network learning process and/or a weight in which neural network learning is completed. The variable weight in the neural network learning process may include a weight at the start of the learning cycle and/or a variable weight during the learning cycle. The weight for which neural network learning is completed may include a weight for which a learning cycle is completed. Accordingly, the data structure including the weights of the neural network may include a data structure including the weights that vary in the neural network learning process and/or the weights on which the neural network learning is completed. Therefore, it is assumed that the above-described weights and/or combinations of weights are included in the data structure including the weights of the neural network. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

The data structure including the weights of the neural network may be stored in a computer-readable storage medium (eg, memory, hard disk) after being serialized. Serialization can be the process of converting a data structure into a form that can be reconstructed and used later by storing it on the same or a different computing device. The computing device may serialize the data structure to send and receive data over a network. A data structure including weights of the serialized neural network may be reconstructed in the same computing device or in another computing device through deserialization. The data structure including the weight of the neural network is not limited to serialization. Furthermore, the data structure including the weights of the neural network is a data structure to increase the efficiency of computation while using the resources of the computing device to a minimum (e.g., B-Tree, Trie, m-way search tree, AVL tree, Red-Black Tree). The foregoing is merely an example, and the present disclosure is not limited thereto.

The data structure may include hyper-parameters of the neural network. In addition, the data structure including the hyperparameters of the neural network may be stored in a computer-readable medium. The hyper parameter may be a variable variable by a user. Hyperparameters are, for example, learning rate, cost function, number of iterations of the learning cycle, weight initialization (e.g., setting the range of weight values to be initialized for weights), Hidden Unit The number (eg, the number of hidden layers, the number of nodes of the hidden layer) may be included. The above-described data structure is merely an example, and the present disclosure is not limited thereto.

8 is a simplified, general schematic diagram of an exemplary computing environment in which embodiments of the present disclosure may be implemented.

Although the present disclosure has been described above generally as being capable of being implemented by a computing device, those skilled in the art will appreciate that the present disclosure is a combination of hardware and software and/or in combination with computer-executable instructions and/or other program modules that may be executed on one or more computers. It will be appreciated that it can be implemented as a combination.

Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In addition, those skilled in the art will appreciate that the methods of the present disclosure can be applied to single-processor or multiprocessor computer systems, minicomputers, mainframe computers as well as personal computers, handheld computing devices, microprocessor-based or programmable consumer electronics, and the like. It will be appreciated that each of these may be implemented in other computer system configurations, including those capable of operating in connection with one or more associated devices.

The described embodiments of the present disclosure may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

Computers typically include a variety of computer-readable media. Any medium accessible by a computer can be a computer readable medium, and such computer readable media includes volatile and nonvolatile media, transitory and non-transitory media, removable and non-transitory media. including removable media. By way of example, and not limitation, computer-readable media may include computer-readable storage media and computer-readable transmission media. Computer-readable storage media includes volatile and non-volatile media, temporary and non-transitory media, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. includes media. A computer-readable storage medium may be RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital video disk (DVD) or other optical disk storage device, magnetic cassette, magnetic tape, magnetic disk storage device, or other magnetic storage device. device, or any other medium that can be accessed by a computer and used to store the desired information.

Computer readable transmission media typically embodies computer readable instructions, data structures, program modules or other data, etc. in a modulated data signal such as a carrier wave or other transport mechanism, and Includes any information delivery medium. The term modulated data signal means a signal in which one or more of the characteristics of the signal is set or changed so as to encode information in the signal. By way of example, and not limitation, computer-readable transmission media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media. Combinations of any of the above are also intended to be included within the scope of computer-readable transmission media.

An exemplary environment 1100 implementing various aspects of the disclosure is shown including a computer 1102 , the computer 1102 including a processing unit 1104 , a system memory 1106 , and a system bus 1108 . do. A system bus 1108 couples system components, including but not limited to system memory 1106 , to the processing device 1104 . The processing device 1104 may be any of a variety of commercially available processors. Dual processor and other multiprocessor architectures may also be used as processing unit 1104 .

The system bus 1108 may be any of several types of bus structures that may be further interconnected to a memory bus, a peripheral bus, and a local bus using any of a variety of commercial bus architectures. System memory 1106 includes read only memory (ROM) 1110 and random access memory (RAM) 1112 . A basic input/output system (BIOS) is stored in non-volatile memory 1110, such as ROM, EPROM, EEPROM, etc., which BIOS is the basic input/output system (BIOS) that helps transfer information between components within computer 1102, such as during startup. contains routines. RAM 1112 may also include high-speed RAM, such as static RAM, for caching data.

The computer 1102 may also be configured with an internal hard disk drive (HDD) 1114 (eg, EIDE, SATA) - this internal hard disk drive 1114 may also be configured for external use within a suitable chassis (not shown). Yes-, magnetic floppy disk drive (FDD) 1116 (eg, for reading from or writing to removable diskette 1118), and optical disk drive 1120 (eg, CD-ROM) for reading from, or writing to, disk 1122, or other high capacity optical media such as DVD. The hard disk drive 1114 , the magnetic disk drive 1116 , and the optical disk drive 1120 are connected to the system bus 1108 by the hard disk drive interface 1124 , the magnetic disk drive interface 1126 , and the optical drive interface 1128 , respectively. ) can be connected to The interface 1124 for implementing an external drive includes at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.

These drives and their associated computer readable media provide non-volatile storage of data, data structures, computer executable instructions, and the like. In the case of computer 1102, drives and media correspond to storing any data in a suitable digital format. Although the description of computer readable media above refers to HDDs, removable magnetic disks, and removable optical media such as CDs or DVDs, those skilled in the art will use zip drives, magnetic cassettes, flash memory cards, cartridges, etc. It will be appreciated that other tangible computer-readable media such as etc. may also be used in the exemplary operating environment and any such media may include computer-executable instructions for performing the methods of the present disclosure.

A number of program modules may be stored in the drive and RAM 1112 , including an operating system 1130 , one or more application programs 1132 , other program modules 1134 , and program data 1136 . All or portions of the operating system, applications, modules, and/or data may also be cached in RAM 1112 . It will be appreciated that the present disclosure may be implemented in various commercially available operating systems or combinations of operating systems.

A user may enter commands and information into the computer 1102 via one or more wired/wireless input devices, for example, a pointing device such as a keyboard 1138 and a mouse 1140 . Other input devices (not shown) may include a microphone, IR remote control, joystick, game pad, stylus pen, touch screen, and the like. Although these and other input devices are often connected to the processing unit 1104 through an input device interface 1142 that is connected to the system bus 1108, parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, It may be connected by other interfaces, etc.

A monitor 1144 or other type of display device is also coupled to the system bus 1108 via an interface, such as a video adapter 1146 . In addition to the monitor 1144, the computer typically includes other peripheral output devices (not shown), such as speakers, printers, and the like.

Computer 1102 may operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) 1148 via wired and/or wireless communications. Remote computer(s) 1148 may be workstations, computing device computers, routers, personal computers, portable computers, microprocessor-based entertainment devices, peer devices, or other common network nodes, and are typically connected to computer 1102 . Although it includes many or all of the components described for it, only memory storage device 1150 is shown for simplicity. The logical connections shown include wired/wireless connections to a local area network (LAN) 1152 and/or a larger network, eg, a wide area network (WAN) 1154 . Such LAN and WAN networking environments are common in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which can be connected to a worldwide computer network, for example, the Internet.

When used in a LAN networking environment, the computer 1102 is connected to the local network 1152 through a wired and/or wireless communication network interface or adapter 1156 . Adapter 1156 may facilitate wired or wireless communication to LAN 1152 , which also includes a wireless access point installed therein for communicating with wireless adapter 1156 . When used in a WAN networking environment, the computer 1102 may include a modem 1158, be connected to a communication computing device on the WAN 1154, or establish communications over the WAN 1154, such as over the Internet. have other means. A modem 1158 , which may be internal or external and a wired or wireless device, is coupled to the system bus 1108 via a serial port interface 1142 . In a networked environment, program modules described for computer 1102 or portions thereof may be stored in remote memory/storage device 1150 . It will be appreciated that the network connections shown are exemplary and other means of establishing a communication link between the computers may be used.

Computer 1102 may be associated with any wireless device or object that is deployed and operates in wireless communication, for example, printers, scanners, desktop and/or portable computers, portable data assistants (PDAs), communication satellites, wireless detectable tags. It operates to communicate with any device or place, and phone. This includes at least Wi-Fi and Bluetooth wireless technologies. Accordingly, the communication may be a predefined structure as in a conventional network or may simply be an ad hoc communication between at least two devices.

Wi-Fi (Wireless Fidelity) makes it possible to connect to the Internet, etc. without a wire. Wi-Fi is a wireless technology such as cell phones that allows these devices, eg, computers, to transmit and receive data indoors and outdoors, ie anywhere within range of a base station. Wi-Fi networks use a radio technology called IEEE 802.11 (a, b, g, etc) to provide secure, reliable, and high-speed wireless connections. Wi-Fi can be used to connect computers to each other, to the Internet, and to wired networks (using IEEE 802.3 or Ethernet). Wi-Fi networks may operate in unlicensed 2.4 and 5 GHz radio bands, for example, at 11 Mbps (802.11a) or 54 Mbps (802.11b) data rates, or in products that include both bands (dual band). .

One of ordinary skill in the art of this disclosure will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, instructions, information, signals, bits, symbols, and chips that may be referenced in the above description are voltages, currents, electromagnetic waves, magnetic fields or particles, optical field particles or particles, or any combination thereof.

A person of ordinary skill in the art of the present disclosure will recognize that the various illustrative logical blocks, modules, processors, means, circuits and algorithm steps described in connection with the embodiments disclosed herein include electronic hardware, (convenience For this purpose, it will be understood that it may be implemented by various forms of program or design code (referred to herein as software) or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. A person skilled in the art of the present disclosure may implement the described functionality in various ways for each specific application, but such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

The various embodiments presented herein may be implemented as methods, apparatus, or articles of manufacture using standard programming and/or engineering techniques. The term article of manufacture includes a computer program, carrier, or media accessible from any computer-readable storage device. For example, computer-readable storage media include magnetic storage devices (eg, hard disks, floppy disks, magnetic strips, etc.), optical disks (eg, CDs, DVDs, etc.), smart cards, and flash drives. memory devices (eg, EEPROMs, cards, sticks, key drives, etc.). Also, various storage media presented herein include one or more devices and/or other machine-readable media for storing information.

It is understood that the specific order or hierarchy of steps in the presented processes is an example of exemplary approaches. Based on design priorities, it is to be understood that the specific order or hierarchy of steps in the processes may be rearranged within the scope of the present disclosure. The appended method claims present elements of the various steps in a sample order, but are not meant to be limited to the specific order or hierarchy presented.

The description of the presented embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments presented herein, but is to be construed in the widest scope consistent with the principles and novel features presented herein.

Claims (11)

A method for semiconductor design, performed by one or more processors of a computing device, comprising:
using a neural network model to identify a region in which the semiconductor device cannot be disposed based on information about a semiconductor device to be disposed; and
calculating a reward for the neural network model based on a region in which the semiconductor device cannot be disposed
including,
The compensation for the neural network model includes a compensation corresponding to a lower limit value of a negative reward when the area in which the semiconductor device cannot be disposed corresponds to the entire area,
Way.
The method of claim 1,
Information about the semiconductor device,
size information including at least one of a width or a height of the semiconductor device; or
information on the type of the semiconductor device;
comprising at least one of
Way.
The method of claim 1,
Information about the semiconductor device,
index information on the arrangement order of the semiconductor devices;
containing,
Way.
The method of claim 1,
The neural network model is
It is learned through reinforcement learning based on a state including information on the semiconductor device, an action of arranging the semiconductor device in a predetermined order, and a reward for the action,
Way.
5. The method of claim 4,
The neural network model is
identifying a region in which the semiconductor device cannot be disposed based on disposition information of at least one semiconductor device disposed before the semiconductor device and an arrangement order of the semiconductor device;
Way.
6. The method of claim 5,
The reward for the neural network model is,
Including a negative reward determined in proportion to the size of the region in which the semiconductor device cannot be disposed,
Way.
7. The method of claim 6,
The reward for the neural network model is,
a first negative compensation determined based on a size of a region in which the first semiconductor element cannot be disposed; and
A second negative compensation determined based on a size of a region in which a second semiconductor device to be disposed after the first semiconductor device cannot be disposed
containing,
Way.
delete The method of claim 1,
In the neural network model, when the region in which the semiconductor device cannot be arranged corresponds to the entire region, the collection of information on the reinforcement learning path is terminated.
Way.
A computer program stored in a computer readable storage medium, wherein the computer program, when executed by one or more processors, causes the one or more processors to perform operations for semiconductor design, the operations comprising:
identifying a region in which the semiconductor device cannot be disposed based on information on a semiconductor device to be disposed by using a neural network model; and
Calculating a reward for the neural network model based on a region in which the semiconductor device cannot be disposed
including,
The compensation for the neural network model includes a compensation corresponding to a lower limit value of a negative reward when the area in which the semiconductor device cannot be disposed corresponds to the entire area,
A computer program stored on a computer-readable storage medium.
A computing device comprising:
at least one processor; and
Memory
including,
the at least one processor,
using a neural network model to identify a region in which the semiconductor device cannot be disposed based on information about a semiconductor device to be disposed; and
configured to calculate a reward for the neural network model based on an area in which the semiconductor element cannot be disposed,
The compensation for the neural network model includes a compensation corresponding to a lower limit value of a negative reward when the area in which the semiconductor device cannot be disposed corresponds to the entire area,
computing device.

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