JP2019021123A - Layout method of semiconductor integrated circuit - Google Patents

Abstract

To shorten a layout period of a new semiconductor integrated circuit having excellent device usage efficiency in a layout, and satisfying desired characteristics.SOLUTION: A semiconductor integrated circuit which has been laid out is used as a master layout, and a layout design of a new semiconductor integrated circuit is conducted by changing only a wiring layer. The laid-out semiconductor integrated circuit being the master layout is configured to enable allocation of all of devices to be used in a circuit diagram of the new semiconductor integrated circuit, and also to enable database retrieval by narrowing down product databases having less non-use devices and excellent device use efficiency. Further, a function is provided that displays in a highlighted manner and guides a portion needing a wiring change on a layout editor, according to a device correspondence table indicating to which device of the master layout the element of the circuit diagram of the new semiconductor integrated circuit is allocated.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for designing a semiconductor integrated circuit using a master slice method for customizing a wiring layer, and to a method for laying out a new semiconductor integrated circuit newly developed based on existing layout data.

  In recent years, there has been a strong demand for shortening the development period in the field of analog semiconductor integrated circuits. There is a master slice method as a method for shortening the layout design period.

  In the master slice method, as shown in FIG. 11, a predetermined number of elements such as a pad 11, a capacitor element 12, a resistor element 13, a PNP transistor 14, and an NPN transistor 15 are prepared in advance on a semiconductor substrate 10, This is a layout method in which only wiring between necessary semiconductor elements is performed in accordance with the function of a newly developed semiconductor integrated circuit. (For example, Patent Documents 1 and 2)

Japanese Patent No. 3214332 Japanese Patent No. 3171431

  As described above, the master slice method is effective for shortening the layout period. However, a specific circuit is not assumed, and the number of elements is previously provided with a margin, and the layout is also provided with a margin in order to prioritize the ease of wiring. Therefore, depending on the circuit, the element use efficiency is poor, and there is a demerit that the degree of integration is lower than that of the custom IC and the chip size is increased. Increasing the chip size not only increases the manufacturing cost of semiconductor integrated circuits, but analog circuits that are highly dependent on layout characteristics cannot obtain the desired characteristics due to parasitic resistance and capacitance of wiring. Such a problem may occur.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a master slice type layout method that solves the above-mentioned problems and that can improve layout element use efficiency and shorten the layout design period of a semiconductor integrated circuit having desired characteristics. To do.

  In order to achieve the above object, the invention according to claim 1 is a layout design method of a semiconductor integrated circuit using a master slice method, a step of creating a product database of a laid-out semiconductor integrated circuit, From the step of creating circuit diagram information of the semiconductor integrated circuit, the step of assigning elements by comparing the product database of the semiconductor integrated circuit having been laid out and the circuit diagram information of the new semiconductor integrated circuit, and the result of the element assignment And a step of determining a product database to be a master layout, and highlighting and guiding a place to be changed on a layout editor.

  According to a second aspect of the present invention, the element assigning step includes a step of narrowing down a product database with a matching process, and a step of performing a database search for comparing the product database with circuit diagram information of the new semiconductor integrated circuit. And a step of creating an element correspondence table in which element allocation information matched in the database search is described.

  According to a third aspect of the present invention, the step of performing the database search includes the step of determining whether the functional block of the net list of the new semiconductor integrated circuit can be allocated, and the element of the net list of the new semiconductor integrated circuit allocated Determining whether it is possible, determining whether the new semiconductor integrated circuit netlist element can be allocated by changing the conditions, and determining whether the new semiconductor integrated circuit netlist element can be allocated manually. It has a process and the process of determining whether a circuit change is possible.

  According to a fourth aspect of the present invention, in the element assigning step, layout data of a semiconductor integrated circuit that has been laid out, circuit diagram information of a new semiconductor integrated circuit, and layout data of a new semiconductor integrated circuit that has undergone wiring changes It is characterized by having a step of performing machine learning of the relationship, weighting the product database of the semiconductor integrated circuit that has been laid out, and determining whether element allocation is possible at the time of designing the layout of the new semiconductor integrated circuit thereafter.

  According to the present invention, a laid-out semiconductor integrated circuit is used as a master layout, and a new semiconductor integrated circuit is laid out by changing a wiring layer, so that a layout with good element use efficiency can be obtained and manufacturing costs can be reduced. Since it is possible to obtain a circuit configuration in which it is confirmed that desired circuit characteristics can be obtained, it is suitable for designing an analog circuit having a large characteristic dependency due to layout. In addition, the layout design period can be shortened because a guide is provided for the part where the wiring is changed in the layout design.

1 is a system configuration diagram of a layout apparatus of the present invention. It is explanatory drawing of hierarchy information. It is a flowchart of the layout design of this invention. It is a figure which shows narrowing down of the product database of this invention. It is a flowchart of the database search of this invention. It is a figure which shows the Example of this invention, and is a figure of the semiconductor integrated circuit by which layout was completed. It is a figure which shows the Example of this invention, and is the circuit diagram and net list of a new semiconductor integrated circuit. It is a figure which shows the Example of this invention, and is explanatory drawing of the step of element allocation. It is a figure which shows the Example of this invention, and is the example which allocated the new semiconductor integrated circuit to the master layout. It is a figure which shows the Example of this invention, and is a figure which shows the relationship between the circuit diagram and layout of a new semiconductor integrated circuit. It is an example of a master slice layout which is a conventional example.

  The layout method of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of a layout apparatus according to the present invention. A product database (hereinafter referred to as “product DB”) of a semiconductor integrated circuit that has been laid out is created (step 1), and a circuit diagram of a new semiconductor integrated circuit An apparatus capable of performing layout design by comparing and assigning elements and reflecting the comparison result in the wiring layout of a new semiconductor integrated circuit is shown.

  In creating a product DB of a semiconductor integrated circuit that has been laid out (step 1), terminal name, instance name, hierarchical information, function block name, element model name, and various parameter information are collected from netlist information in the circuit diagram, and layout data is collected. The information of the function block, the element and the coordinates of each terminal is collected, and the information of the used flag is collected in addition to the information of the process (design rule), package and manufacturing cost, the maximum rating of each terminal. As shown in FIG. 2, the hierarchy information is information indicating a level division such that an element level is a hierarchy 1, a functional cell is a hierarchy 2, and a functional block is a hierarchy 3. A user searches in advance when assigning elements. It is possible to specify the level of the hierarchy to be performed. The used flag is information used in database search (step 4) for comparing the product DB and circuit diagram information of a new semiconductor integrated circuit, and the initial value is set to FALSE (hereinafter referred to as “F”). The element of the layout data and the coordinate data of each terminal can be extracted by commercially available software. The product DB can be constructed in a general relational database management system (RDBMS). Note that some logic cells such as DFFs laid out as functional cells are not suitable for reuse in a new semiconductor integrated circuit as a single transistor. Such a cell is not described at the transistor level, and the function cell is treated as one unit.

  FIG. 3 is a flow chart of the layout design of the present invention. First, circuit diagram information of a new semiconductor integrated circuit is created (step 2). Next, based on the circuit diagram information data of the new semiconductor integrated circuit such as process and package information, maximum ratings of each terminal, the product DB that is a candidate for the master layout is narrowed down and compared with the circuit diagram information of the new semiconductor integrated circuit. The order is determined (step 3). Thereafter, a database search is performed to determine whether all functional blocks and elements used in the circuit diagram of the new semiconductor integrated circuit exist in the product DB (step 4). When a product DB to which all the elements of the circuit diagram of the new semiconductor integrated circuit can be assigned is found, an element correspondence table in which element matching information is described is created (step 5). Subsequently, the element correspondence table is read into the layout editor, the wiring data is changed according to the guide (step 6), and various verifications such as DRC (Design Rule Check) / LVS (Layout Versus Schematic) are performed (step 7), and the layout design is performed. To complete. If element allocation cannot be performed for all product DBs selected in step 3, it is determined that layout design by changing the wiring layer is impossible.

  Hereinafter, each step will be described in detail. First, in the creation of circuit diagram information for a new semiconductor integrated circuit (step 2), terminal names, instance names, hierarchical information, function block names, element model names, various parameters, processes included in the netlist obtained from the circuit diagram editor In addition to the information such as (design rule), a list is created in which information about the maximum rating of the package and each terminal as data necessary for narrowing the product DB (step 3) is created.

  In narrowing down the product DB (step 3), as shown in FIG. 4, in addition to the netlist of a new semiconductor integrated circuit, data of circuit diagram information such as processes (design rules), packages, and maximum ratings of each terminal is used. First, the product DBs that are candidates for the master layout are narrowed down, and the priority order to be compared with the circuit diagram information of the new semiconductor integrated circuit is determined. Even when there are many product DBs that match only with process (design rule) information, a more similar product DB can be selected by adding and comparing the maximum rating information of packages and terminals. In addition, when a product DB for which wiring data can be easily changed is known in advance, it is possible to specify that a database search be preferentially performed.

  In the database search (step 4), as shown in FIG. 5, it is first determined whether all functional blocks that are higher layers of the new semiconductor integrated circuit exist in the product DB and can be assigned (step 41). When a matching functional block is found, the used flag in the product DB is set from F to TRUE (hereinafter referred to as “T”) and described in the matching list. The function block whose used flag is set to T is excluded from the subsequent search targets. When a function block matching the master layout is known in advance in the new semiconductor integrated circuit netlist, the used flag can be set to T in advance so that the function block is excluded from the search target. . Alternatively, the used flag can be set to T in advance so that a portion that is not changed in the circuit diagram and matches in the LVS is also excluded from the search target. After all the searches are completed, a list of unused elements whose used flag is F is created. Even if it is already assigned as a function block, if there are unused elements in the function block, it is added to the list of unused elements. It is possible to allocate elements flexibly. If all the functional blocks match at this stage, the process proceeds to creation of an element correspondence table (step 5). When a function block that matches the product DB is not found, the function block and the instance are described in the mismatch list.

  If there is an element in the mismatch list after the database search in step 41, the element level search is performed (step 42). It is determined whether an element having the same element model name and parameters in the circuit diagram information list of the new semiconductor integrated circuit exists in the product DB and can be assigned. When a matching element is found, the used flag in the product DB is set from F to T and described in the matching list. Elements whose used flag is set to T are excluded from subsequent search targets. If an element that matches the master layout is known in advance in the new semiconductor integrated circuit netlist, the used flag may be set to T manually in advance so as to exclude the element from the search target. After all the searches are completed, a list of unused elements whose used flag is F is created. If all the functional blocks and elements match, the process proceeds to the element correspondence table creation (step 5). If no matching element is found in the product DB, the instance is described in the mismatch list.

  If there is an element in the mismatch list after the database search in step 41 and step 42, it is determined whether the assignment can be made by changing the condition (step 43). Condition change refers to adjustment of element parameters. The gate width of the MOS transistor is expressed by W × M, which is the product of the gate width (W) and the number (M), and in the circuit diagram, the layout is expressed as one transistor with W = 10 μm (M = 1). In some cases, W and M may be different, such as using two transistors with W = 5 μm (M = 2). Thus, simply comparing W and M increases instances that do not match. Similarly, in the case where the resistance and the capacitance are expressed by one resistance value and capacitance value in the circuit diagram and can be realized by a plurality of resistances and capacitances in the layout, the comparison does not agree. Therefore, as shown in the description example of the product DB in FIG. 6D, MOS transistors having the same hierarchy and the same gate length (L) are grouped in advance by adding a group property. As for the resistance, a resistance table that can be realized by combining a plurality of unit resistance cells is prepared in advance. For example, when the resistance value of the unit resistance cell is 10 kΩ, it is possible to realize 5 kΩ in two parallel, 20 kΩ in series, 3.3 kΩ in three parallel, 30 kΩ in series, and 15 kΩ in series parallel. Regarding the capacitance value, a necessary number is obtained by calculating so as to be the capacitance of the circuit diagram with a plurality of capacitances.

  If assignment is impossible due to the condition change in step 43 and there is an element in the mismatch list, it is determined whether assignment is possible manually (step 44). For example, manual assignment refers to the use of an unused element when the layout of the functional block in step 41 matches the circuit diagram but contains an unused element. This is a case where an element of another functional block can be assigned. In this case, the user manually changes the description to the match list, the deletion from the mismatch list, and the use flag setting.

  If there is an element in the mismatch list even after manual assignment, the process returns to the circuit design to determine whether the insufficient element can be changed (step 45). If there is a possibility that the shortage will be resolved, the net list is changed, the circuit diagram information is updated, and the processing is sequentially performed again starting from the function block database search in step 41 to determine the product DB as the master layout.

  When the database search is performed for all the selected product DBs and all the elements in the circuit diagram of the new semiconductor integrated circuit match, an element correspondence table that describes element allocation information based on the matching list Is created (step 5). When there are a plurality of product DBs that match the circuit diagram information of the new semiconductor integrated circuit, the product DB that is used as the master layout is determined with priority given to those with few unused elements or those with low manufacturing costs.

  When the product DB to be the master layout is determined, the position coordinates of each element are acquired from the element correspondence table and the information of the product DB, and the circuit element selected in the circuit diagram editor is highlighted (highlighted) on the layout editor. The wiring data is changed manually according to the guide (step 6). When a plurality of unused elements correspond to one element in the circuit diagram, an element optimal for the analog characteristics of the product is manually selected. Furthermore, when changing the wiring data, it is possible to obtain the position coordinates of the unused elements from the unused element list and the product DB information and confirm them on the layout editor. Elements assigned to the element correspondence table It is also possible to make a selection by checking whether there is an element suitable for the product characteristics.

  After changing the wiring data, various verifications such as DRC / LVS are performed (step 7), and the layout design of a new semiconductor integrated circuit is completed.

  Also, machine learning is performed on the layout data of the semiconductor integrated circuit that has been laid out, the circuit diagram information of the new semiconductor integrated circuit, and the layout data of the new semiconductor integrated circuit in which the wiring has been changed, and the product DB of the semiconductor integrated circuit that has been laid out Perform weighting. When designing a layout of a new semiconductor integrated circuit thereafter, it may be possible to narrow down product DBs of semiconductor integrated circuits that have been laid out based on this weighting.

  Next, it demonstrates in detail using the Example of this invention. 6 to 10 show an embodiment of the present invention. 6A is a circuit diagram of a semiconductor integrated circuit that has been laid out, FIG. 6B is a net list of the semiconductor integrated circuit that has been laid out, and FIG. 6C is a diagram excluding the wiring layer of the semiconductor integrated circuit that has been laid out. It is a layout drawing (master layout). Here, for description, the instance name in the master layout and the circuit diagram instance name of the laid-out semiconductor integrated circuit are shown in the layout drawing. FIG. 6D shows netlist information of a semiconductor integrated circuit that has been laid out, coordinates of elements and terminals extracted from the layout data, process (design rule), package, manufacturing cost, and maximum rating information of each terminal. This is a description example of the product DB to which is added.

  FIG. 7 is a circuit diagram and a net list of a new semiconductor integrated circuit, and is a circuit in which the transistor size is changed from the circuit diagram of FIG. The flow of assigning this to the element of the product DB in FIG. 6D will be described. FIG. 8A is a description of the product DB, and shows an initial state in which all used flags are F. In the database search in step 42, an element having the same element type and parameters such as L and W is found in the circuit diagram information of the new semiconductor integrated circuit and the product DB, and the state where the used flag is T is shown in FIG. b). Next, FIG. 8C shows a state in which the condition is changed in step 43, the element parameter L is equal, W is multiplied by N, an element having the same parameter is found, and the used flag is set to T. At this time, N elements are set to T.

  FIG. 9A is a layout drawing when the new semiconductor integrated circuit of FIG. 7 is assigned to the master layout of FIG. 6C, and FIG. Here, for description, the instance name in the master layout and the circuit diagram instance name of the new assigned semiconductor integrated circuit are shown in the layout drawing. Next, the element list obtained as a result of element assignment is read into a circuit diagram editor and a layout editor, and wiring data is changed. FIG. 10 shows an example of confirming the relationship between a master layout and a circuit diagram of a new semiconductor integrated circuit that is found to be assignable. FIG. 10A is a circuit diagram of the new semiconductor integrated circuit, and is displayed on the circuit diagram editor. When MS3 is selected, MS3 is searched from the element list shown in FIG. 10B, and converted into instance names X0 / M24 and X0 / M25 of the master layout. Then, position information is acquired from the product DB of the master layout of FIG. 10C, and the corresponding element is highlighted (highlighted) on the layout editor as shown in FIG. 10D, and a wiring guide is shown.

  As described above, according to the present invention, a layout of a semiconductor integrated circuit that has been laid out is used as a master layout, and a new semiconductor integrated circuit is laid out by changing a wiring layer. In addition, desired characteristics can be obtained in an analog circuit that is highly dependent on layout characteristics. In addition, the layout design period can be shortened because a guide is provided for the part where the wiring is changed in the layout design.

MS1, MS2, MS2 ′, MS3, MS3 ′: PMOS transistor MS4, MS5: NMOS transistor VDD: power supply terminal GND: ground terminal 1: PMOS transistor 2: NMOS transistor 3: gate 4: source 5: drain 6: electrode 7: 1st wiring 8: 2nd wiring 9: 3rd wiring 10: Semiconductor substrate 11: Pad 12: Capacitance element 13: Resistance element 14: PNP transistor 15: NPN transistor

Claims (4)

A semiconductor integrated circuit layout design method using a master slice method,
Creating a product database of laid-out semiconductor integrated circuits; and
Creating circuit diagram information of a new semiconductor integrated circuit;
A step of assigning elements by comparing a product database of a laid-out semiconductor integrated circuit and circuit diagram information of the new semiconductor integrated circuit;
From the result of the element allocation, determining a product database as a master layout, and highlighting and guiding a place to change wiring on the layout editor, and
A layout design method for a semiconductor integrated circuit, comprising: The step of assigning the elements includes:
The process of narrowing down the product database with the matching process,
Performing a database search comparing the product database and circuit diagram information of the new semiconductor integrated circuit;
Creating an element correspondence table describing element allocation information matched in the database search;
The layout design method for a semiconductor integrated circuit according to claim 1, further comprising: The step of performing the database search includes:
Determining whether the functional block of the netlist of the new semiconductor integrated circuit can be assigned;
Determining whether an element of a netlist of the new semiconductor integrated circuit is assignable;
Determining whether the element of the net list of the new semiconductor integrated circuit can be assigned by changing the conditions;
Determining whether the new semiconductor integrated circuit netlist element can be assigned manually;
Determining whether the circuit can be changed; and
The layout design method for a semiconductor integrated circuit according to claim 2, further comprising: The step of assigning the elements includes:
Machine learning of the layout data of the semiconductor integrated circuit that has been laid out, the circuit diagram information of the new semiconductor integrated circuit, and the layout data of the new semiconductor integrated circuit that has undergone wiring changes, to the product database of the semiconductor integrated circuit that has been laid out 2. The layout design method for a semiconductor integrated circuit according to claim 1, further comprising a step of performing weighting and determining whether or not element allocation is possible at the time of layout design of a new semiconductor integrated circuit thereafter.

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