CN112364599A - Fixed frame circuit layout planning method - Google Patents
Fixed frame circuit layout planning method Download PDFInfo
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- CN112364599A CN112364599A CN202011354840.XA CN202011354840A CN112364599A CN 112364599 A CN112364599 A CN 112364599A CN 202011354840 A CN202011354840 A CN 202011354840A CN 112364599 A CN112364599 A CN 112364599A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/10—Processors
Abstract
The invention discloses a fixed frame circuit layout planning method, which is characterized in that in a rough layout stage, an analysis method based on electrostatic field simulation is used for dispersing modules, and the length of interconnection lines is optimized; in order to maintain good coarse layout results at the first stage, the legalization stage first generates a partition tree of results of the coarse layout, and then finally merges the partition trees to generate the final reasonable layout result. The invention can quickly determine the position of each module in the circuit system on the fixed frame, and simultaneously determine the width and the height of the soft module in the circuit system, thereby obtaining a layout result with better quality, promoting the time of chip design and manufacture and improving the performance of the chip; in addition, the method can be applied to large-scale hybrid module circuit layout planning.
Description
Technical Field
The invention belongs to the technical field of cloth cover detection, and particularly relates to a fixed frame circuit layout planning method.
Background
As science and technology advances, more and more transistors are integrated onto a single chip. To reduce the complexity of the design, modern designs often employ a hierarchical design or use IP blocks to address the problem. Floorplanning is a critical step in the physical design of a chip, since the cost and performance of a chip are directly affected by floorplanning. This would greatly shorten the chip design cycle if a good floorplan could be obtained at the beginning. Therefore, floorplanning has always played an important role in chip-on-chip design.
However, the conventional floor planning algorithm only considers the area optimization of the chip and the optimization of the length of the interconnection line, and does not consider the condition constraint of the fixed frame. Since the area of a chip is usually determined in advance, a floorplanning result without considering the problem of the fixed frame is usually unreasonable, which may result in inaccuracy and unreasonable floorplanning. In addition, the conventional layout planning method for the fixed frame cannot quickly determine the position of the frame and the size of the module.
Disclosure of Invention
In order to solve the problems, the invention provides a fixed frame circuit layout planning method, which can quickly determine the position of each module in a circuit system on a fixed frame, simultaneously determine the width and the height of a soft module in the circuit system, obtain a layout result with better quality, promote the time of chip design and manufacture and improve the performance of a chip; the method is particularly suitable for large-scale hybrid module circuit layout planning.
In order to achieve the purpose, the invention adopts the technical scheme that: a fixed frame circuit layout planning method comprises the following steps:
s10, calculating the line length gradient and density in the circuit;
s20, calculating the potential and the electric field of each module of the equivalent electrostatic system of the whole circuit by using the density;
s30, calculating the gradient of the potential energy according to the obtained electric field;
s40, establishing a rough layout objective function by using the line length gradient and the potential energy gradient;
s50, optimizing the target function by using a Nesterov Newton momentum method, updating parameters and simultaneously obtaining an optimized rough layout result;
s60, judging whether the result of the rough layout reaches convergence adjustment, if not, repeating the steps S10-S50, and if so, taking the rough layout as a final rough layout;
s70, dividing the rough layout by using the obtained rough layout to obtain a division tree;
and S80, determining the width and height of the soft module and the module position by using shape curve combination according to the obtained partition tree to obtain a reasonable layout.
Further, in step S20, the electric potential and the electric field at the position of each module of the entire circuit equivalent electrostatic system are calculated by using the density, and the calculation formula is:
where ρ is the density, Ψ (x, y) is the potential at the location of the module, ξ (x, y) is the electric field at the location of the module, R is the entire fixed layout area,
refers to a normal exovector of the fixed layout area.
Further, in the step S30, the gradient of the potential energy is calculated from the obtained electric field
The calculation formula is as follows:
wherein q is equal to the area of the module, and ξ (x, y) is the electric field at the location of the module.
Further, in the step S40, a rough layout objective function is established using the line length gradient and the gradient of the potential energy:
wherein v represents a coarse layout result; w (v) a bus length representing a coarse layout; n (v) represents the total potential of the coarse layout; λ is a weighting parameter used to balance line length and potential energy.
Further, the total potential energy n (v) of the coarse layout is:
wherein V represents a set of modules; q. q.siRepresenting a charge and electricity quantity equivalent to the area size of a module; ΨiIndicating the potential at which the module is located.
Further, in step S50, optimizing the objective function by using a Nesterov newton momentum method, updating the parameters, and obtaining the optimized coarse layout result, the method includes the steps of:
firstly, derivation is carried out on an objective function:
then, according to the derived objective function, the Nesterov Newton momentum method is used for optimizing the objective function
Where vk +1 represents the coarse layout result, f represents the objective function,
meaning that the derivation of the objective function is performed,α denotes the step size and NL-Solver refers to the Nesterov optimization method.
Further, in the step S60, the result of the coarse layout is determined, and when the density overflow τ is less than 10%, the result converges to be the final coarse layout; if not, repeating the steps S10-S50;
where Ai represents the module area, Ab represents the area in one grid, ρ b represents the actual density within the grid, and ρ t is the set density.
Further, in step S70, the method for obtaining the partition tree by using the obtained rough layout and dividing the rough layout includes the steps of:
firstly, calling an unmetis recursive algorithm to divide the whole netlist until the number of modules contained in each part is less than 9;
then, the geometric positions of the partitions are recorded to form a partition tree.
Further, in S80, determining the width and height of the soft module and the module position by using shape curve combination to obtain a reasonable layout according to the obtained partition tree, including the steps of:
s81, constructing shape functions of all independent blocks in the partition tree;
s82, determining the shape function of the top-level layout by the shape function of each individual block by using a bottom-up strategy, namely, starting from the bottommost block, performing horizontal or vertical combination until the optimal size and shape of the topmost layer are determined;
and S83, tracing back to the shape function of each block from the corner point corresponding to the minimum top layer layout area in a top-down mode, thereby determining the size and the position of the block.
Further, the shape function is:
wherein w represents the width of the module and area represents the area of the module; all heights h ≧ h (w) of the block are legal.
The beneficial effects of the technical scheme are as follows:
the present invention proposes a two-stage approach to address this problem; in the rough layout stage, an analytical method based on electrostatic field simulation is used for dispersing the modules, and meanwhile, the length of the interconnection lines is optimized; in order to maintain good coarse layout results at the first stage, the legalization stage first generates a partition tree of results of the coarse layout, and then finally merges the partition trees to generate the final reasonable layout result. The invention changes the first stage process of the layout planning into a two-dimensional space to solve the static balance state, then adjusts the width and the height of the soft module, and adjusts the position of the module locally to obtain the final layout result, and all the work forms a complete chip layout planning algorithm. The quality of the coarse layout is sufficiently improved to ultimately produce better layout results, thereby improving chip performance and reducing manufacturing time. The method has the advantages that the layout planning work of the physical design stage in the chip design is faster and more efficient, meanwhile, because the first stage of the layout planning work is a global layout, a better rough layout planning result can be brought, a layout result with better quality can be finally obtained, the chip design and manufacturing time is promoted, and the chip performance is improved.
In the invention, the layout planning example is modeled into an electrostatic field, the module example is modeled into positive charge, the density corresponds to the system potential energy, the potential energy is changed through the movement of the charge, the density of the layout system is also changed, and when the density reaches the constraint condition, the density is converged. Since the whole system is modeled as an electrostatic field system, the charge movement of the system is a global movement, which also means that our layout is a global layout, and therefore better layout results are obtained in the coarse layout stage.
Drawings
FIG. 1 is a schematic flow chart of a fixed-frame circuit layout planning method according to the present invention;
fig. 2 is a schematic diagram of finding an optimal border according to a partition tree in the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described with reference to the accompanying drawings.
In this embodiment, referring to fig. 1, the present invention provides a fixed frame circuit layout planning method, including the steps of:
s10, calculating the line length gradient and density in the circuit;
s20, calculating the potential and the electric field of each module of the equivalent electrostatic system of the whole circuit by using the density;
s30, calculating the gradient of the potential energy according to the obtained electric field;
s40, establishing a rough layout objective function by using the line length gradient and the potential energy gradient;
s50, optimizing the target function by using a Nesterov Newton momentum method, updating parameters and simultaneously obtaining an optimized rough layout result;
s60, judging whether the result of the rough layout reaches convergence adjustment, if not, repeating the steps S10-S50, and if so, taking the rough layout as a final rough layout;
s70, dividing the rough layout by using the obtained rough layout to obtain a division tree;
and S80, determining the width and height of the soft module and the module position by using shape curve combination according to the obtained partition tree to obtain a reasonable layout.
As an optimization solution of the above embodiment, in step S20, the electric potential and the electric field at the position of each module of the entire circuit equivalent electrostatic system are calculated by using the density, and the calculation formula is as follows:
where ρ is the density, Ψ (x, y) is the potential at the location of the module, ξ (x, y) is the electric field at the location of the module, R is the entire fixed layout area,
refers to a normal exovector of the fixed layout area.
As an optimization of the above embodiment, in the step S30, the gradient of the electric potential energy is calculated according to the obtained electric field
The calculation formula is as follows:
wherein q is equal to the area of the module, and ξ (x, y) is the electric field at the location of the module.
As an optimization solution of the above embodiment, in the step S40, a rough layout objective function is established by using the line length gradient and the potential energy gradient:
wherein v represents a coarse layout result; w (v) a bus length representing a coarse layout; n (v) represents the total potential of the coarse layout; λ is a weighting parameter used to balance line length and potential energy.
The total potential of the coarse layout N (v) is:
wherein V represents a set of modules; q. q.siRepresenting a charge and electricity quantity equivalent to the area size of a module; ΨiIndicating the potential at which the module is located.
As an optimization scheme of the above embodiment, in step S50, optimizing the objective function by using a Nesterov newton momentum method, updating parameters, and obtaining an optimized coarse layout result, the method includes the steps of:
firstly, derivation is carried out on an objective function:
then, according to the derived objective function, the Nesterov Newton momentum method is used for optimizing the objective function
Where vk +1 represents the coarse layout result, f represents the objective function,
denotes the derivation of the objective function, α denotes the step size, NL-Solver refers to the Nesterov optimization method.
As an optimization scheme of the above embodiment, in step S60, the result of the coarse layout is determined, and when the density overflow τ is less than 10%, the result converges to be the final coarse layout; if not, repeating the steps S10-S50;
where Ai represents the module area, Ab represents the area in one grid, ρ b represents the actual density within the grid, and ρ t is the set density.
As an optimization scheme of the above embodiment, in step S70, the method for obtaining a partition tree by using the obtained rough layout and dividing the rough layout includes the steps of:
firstly, calling an unmetis recursive algorithm to divide the whole netlist until the number of modules contained in each part is less than 9;
then, the geometric positions of the partitions are recorded to form a partition tree.
As an optimization solution of the above embodiment, in S80, determining the width and height of the soft module and the module position by using shape curve combination to obtain a reasonable layout according to the obtained partition tree, includes the steps of:
s81, constructing shape functions of all independent blocks in the partition tree;
s82, determining the shape function of the top-level layout from the shape function of each individual block by using a bottom-up strategy, i.e. performing horizontal or vertical combination starting from the bottom-most block until the optimal size and shape of the top-most layer are determined, as shown in FIG. 2;
and S83, tracing back to the shape function of each block from the corner point corresponding to the minimum top layer layout area in a top-down mode, thereby determining the size and the position of the block.
The shape function is:
wherein w represents the width of the module and area represents the area of the module; all heights h ≧ h (w) of the block are legal.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A fixed frame circuit layout planning method is characterized by comprising the following steps:
s10, calculating the line length gradient and density in the circuit;
s20, calculating the potential and the electric field of each module of the equivalent electrostatic system of the whole circuit by using the density;
s30, calculating the gradient of the potential energy according to the obtained electric field;
s40, establishing a rough layout objective function by using the line length gradient and the potential energy gradient;
s50, optimizing the target function by using a Nesterov Newton momentum method, updating parameters and simultaneously obtaining an optimized rough layout result;
s60, judging whether the result of the rough layout reaches convergence adjustment, if not, repeating the steps S10-S50, and if so, taking the rough layout as a final rough layout;
s70, dividing the rough layout by using the obtained rough layout to obtain a division tree;
and S80, determining the width and height of the soft module and the module position by using shape curve combination according to the obtained partition tree to obtain a reasonable layout.
2. The method as claimed in claim 1, wherein in step S20, the electric potential and the electric field at the position of each module of the whole equivalent electrostatic system are calculated by using the density, and the calculation formula is:
where ρ is the density, Ψ (x, y) is the potential at the location of the module, ξ (x, y) is the electric field at the location of the module, R is the entire fixed layout area,
refers to a normal exovector of the fixed layout area.
3. The fixed-bezel circuit layout method as claimed in claim 2, wherein in step S30, the gradient of the electric potential energy is calculated according to the obtained electric field
The calculation formula is as follows:
wherein q is equal to the area of the module, and ξ (x, y) is the electric field at the location of the module.
4. The fixed-frame circuit layout planning method according to claim 3, wherein in said step S40, a coarse layout objective function is established by using the line length gradient and the potential energy gradient:
wherein v represents a coarse layout result; w (v) a bus length representing a coarse layout; n (v) represents the total potential of the coarse layout; λ is a weighting parameter used to balance line length and potential energy.
5. The method of claim 4, wherein the total potential N (v) of the coarse layout is:
wherein V represents a set of modules; q. q.siRepresenting a charge and electricity quantity equivalent to the area size of a module; ΨiIndicating the potential at which the module is located.
6. The fixed-frame circuit layout planning method of claim 5, wherein in step S50, the Nesterov Newtonian momentum method is used to optimize the objective function, update the parameters, and obtain the optimized coarse layout result, comprising the steps of:
firstly, derivation is carried out on an objective function:
then, according to the derived objective function, the Nesterov Newton momentum method is used for optimizing the objective function
Where vk +1 represents the coarse layout result, f represents the objective function,
denotes the derivation of the objective function, α denotes the step size, NL-Solver refers to the Nesterov optimization method.
7. The fixed-frame circuit layout planning method according to claim 1 or 6, wherein in the step S60, the result of the coarse layout is judged, and when the density overflow τ is less than 10%, the result is converged as the final coarse layout; if not, repeating the steps S10-S50;
where Ai represents the module area, Ab represents the area in one grid, ρ b represents the actual density within the grid, and ρ t is the set density.
8. The fixed-frame circuit layout planning method of claim 7, wherein in step S70, the obtained coarse layout is used and divided to obtain a division tree, comprising the steps of:
firstly, calling an unmetis recursive algorithm to divide the whole netlist until the number of modules contained in each part is less than 9;
then, the geometric positions of the partitions are recorded to form a partition tree.
9. The fixed-frame circuit floorplanning method of claim 8, wherein in the step S80, determining the soft module width and height and the module position by using shape curve combination to obtain a reasonable floorplan according to the obtained partition tree, comprises the steps of:
s81, constructing shape functions of all independent blocks in the partition tree;
s82, determining the shape function of the top-level layout by the shape function of each individual block by using a bottom-up strategy, namely, starting from the bottommost block, performing horizontal or vertical combination until the optimal size and shape of the topmost layer are determined;
and S83, tracing back to the shape function of each block from the corner point corresponding to the minimum top layer layout area in a top-down mode, thereby determining the size and the position of the block.
10. The fixed-frame circuit floorplanning method of claim 9, wherein the shape function is:
wherein w represents the width of the module and area represents the area of the module; all heights h ≧ h (w) of the block are legal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023130434A1 (en) * | 2022-01-10 | 2023-07-13 | 华为技术有限公司 | Layout design method and apparatus, device, medium and program product |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1347303A2 (en) * | 2000-08-03 | 2003-09-24 | QUALCOMM Incorporated | Automated EMC-driven layout and floor planning of electronic devices and systems |
| CN103984794A (en) * | 2014-04-02 | 2014-08-13 | 宁波大学 | Fixed-outline integrated circuit floorplanning method for soft module |
| US20150012901A1 (en) * | 2013-07-05 | 2015-01-08 | National Cheng Kung University | Fixed-outline floorplanning approach for mixed-size modules |
| CN107526860A (en) * | 2017-03-31 | 2017-12-29 | 福州大学 | VLSI standard cell placement methods based on electric field energy modeling technique |
-
2020
- 2020-11-27 CN CN202011354840.XA patent/CN112364599A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1347303A2 (en) * | 2000-08-03 | 2003-09-24 | QUALCOMM Incorporated | Automated EMC-driven layout and floor planning of electronic devices and systems |
| US20150012901A1 (en) * | 2013-07-05 | 2015-01-08 | National Cheng Kung University | Fixed-outline floorplanning approach for mixed-size modules |
| CN103984794A (en) * | 2014-04-02 | 2014-08-13 | 宁波大学 | Fixed-outline integrated circuit floorplanning method for soft module |
| CN107526860A (en) * | 2017-03-31 | 2017-12-29 | 福州大学 | VLSI standard cell placement methods based on electric field energy modeling technique |
Non-Patent Citations (2)
| Title |
|---|
| 杜世民等: "一种有效的面向软模块的VLSI布图规划算法", 《计算机工程与应用》 * |
| 杜世民等: "面向软模块的稳定固定边框布图规划算法", 《电子与信息学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023130434A1 (en) * | 2022-01-10 | 2023-07-13 | 华为技术有限公司 | Layout design method and apparatus, device, medium and program product |
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Application publication date: 20210212 |