JP3655064B2 - Semiconductor device design support equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI design support apparatus, and more particularly to a semiconductor device design support apparatus that accurately simulates a high-frequency analog circuit, an analog / digital mixed circuit, and the like and efficiently supports high-performance optimum LSI design.
[0002]
[Prior art]
With the development of semiconductor manufacturing technology, high speed and high integration of LSI have been remarkably advanced, and various high performance LSIs can be manufactured. In such LSIs, not only high-level analog circuits and analog (digital / analog) mixed circuits are required, but also high-performance and low-cost demands are strong. In response to such demands on LSIs, circuit designers must design their circuits in a short time at a low cost. Therefore, it has been demanded that a circuit design support apparatus also has a support function suitable for it.
[0003]
For example, as LSIs become faster and more integrated, high-frequency analog circuits and analog-mixed circuits have had little effect so far. Crosstalk between wires and digital circuit parts that are transmitted to the analog circuit part via a semiconductor substrate. The design must also take into account the effects of parasitic effects such as generated noise that depend on the element layout pattern on the LSI.
[0004]
For this purpose, it is necessary to accurately simulate these effects. In order to accurately simulate these effects, it was necessary to execute an analysis called electromagnetic field analysis or device simulation, but these were not practical because they required a lot of calculation time.
[0005]
Therefore, conventionally, there has been proposed a method as described in Reference 1 in which circuit simulation is performed by modeling a substrate as a resistance network or replacing a wiring with a model having a resistance component and a capacitance component (Reference 1: Balshz R. Stanisic). , Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley and David J. Allstot, "Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Distribution Synthesis", IEEE Journal of Solid-State Circuits, Vol. 9, No. 3, pp. 226-238, March, 1994). It is generally accepted that the simulation results by this method agree well with the experimental results.
[0006]
However, in an actual integrated circuit in which a large number of elements are arranged and formed two-dimensionally on an LSI substrate, each of these elements is written in the form of circuit simulation input data in consideration of the spatial positional relationship. It was very difficult to do. Furthermore, since the conventional circuit simulation is performed independently of the layout design, the simulation results show, for example, the positional relationship between the digital circuit section that is a noise source and the analog circuit section that is easily affected by the noise. There was a problem such as being unable to respond.
[0007]
Therefore, since the simulation result cannot be fed back to the designer as effective information, it cannot be an efficient LSI design support apparatus.
[0008]
[Problems to be solved by the invention]
As described above, in LSI design, as LSIs become faster and more integrated, crosstalk between wirings, noise generated in the digital circuit part system transmitted to the analog circuit part via the semiconductor substrate, etc. It is necessary to consider the influence of the parasitic effect depending on the element arrangement layout pattern. To that end, it is necessary to simulate the parasitic effects that are problematic in high-frequency analog circuits and analog-digital mixed circuits. To that end, the elements placed on the LSI substrate and the parasitic elements of the wiring are extracted and input data for circuit simulation. It is necessary to convert to the format. In the past, this relied on manual labor, but it was an extremely difficult task to perform this manually. In addition, the simulation is performed independently of the LSI element layout design.
[0009]
Therefore, in the conventional LSI design support apparatus, performing the simulation is a work with great effort, and even if the simulation is performed, the obtained result cannot be fed back to the designer as effective information.
[0010]
Therefore, the object of the present invention is to solve the problems of the above-mentioned conventional LSI design support device, and to perform various analyzes easily including parasitic effects depending on the layout pattern while performing layout design, An object of the present invention is to provide an LSI design support apparatus that can feed back the results to the designer as effective information.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device design support apparatus according to the present invention inputs information such as the shape and arrangement of circuit elements such as elements and wirings constituting a semiconductor integrated circuit, physical constants, manufacturing conditions, and calculation conditions. An input means for displaying, a display means for displaying the input information and analysis results, and an equivalent model for extracting circuit elements such as linear elements, nonlinear elements, wiring, contact holes, and via holes from the information, and creating an equivalent model Model creation means, data format conversion means for converting the equivalent model obtained by the equivalent model creation means into a data format that can be numerically analyzed, data converted by the data format conversion means, and calculation conditions And a calculation means for numerically analyzing the extracted equivalent model; and an output means for outputting a calculation result of the calculation means to the display means; Comprising.
[0012]
Moreover, in the semiconductor device design support apparatus having such a configuration,
A means for creating data at the same hierarchical level as the element arrangement and wiring information in a mask layer that is not used for manufacturing a semiconductor integrated circuit, and storing the information in a form that can be handled by the element extraction and equivalent model creating means. Means to
Furthermore, a means for adding a circuit that does not exist on the LSI chip to an arbitrary position on the means for displaying information on the shape and arrangement of the elements and the wiring is provided.
Further, the present invention is characterized in that it has a function of designating various simulation setting methods and simulation result display methods from means for displaying information on the shape, arrangement, and wiring of the elements.
[0013]
According to the semiconductor device design support apparatus of the present invention having such a configuration, information such as the shape and arrangement of elements that are circuit elements constituting a semiconductor integrated circuit, wiring, physical constants, manufacturing conditions, and calculation conditions are input. When input is made by the means, the inputted information is displayed on the display means. At this time, the shape, arrangement state, etc. of the elements and wirings are displayed on the layout screen (image display state screen in which the layout state can be seen). The equivalent model creation means extracts linear elements, nonlinear elements, wirings, etc. from the above information and creates an equivalent model, and the data format conversion means can numerically analyze the equivalent model obtained by the equivalent model creation means. To the correct data format. Then, the calculation means numerically analyzes the extracted equivalent model based on the data converted by the data format conversion means and the calculation conditions, and the output means outputs the calculation result of the calculation means to the display means. Output.
[0014]
In the system of the present invention, when designing an integrated circuit, from the layout data, the influence of the noise that wraps around the semiconductor substrate constituting the integrated circuit and the influence of the crosstalk between the wirings can be analyzed by the calculation means in the circuit simulation. Parasitic element components that do not appear in the design circuit can be extracted as an equivalent model and converted into a circuit simulation input data format.
[0015]
The circuit simulation can be freely generated at any position as a virtual element, such as a necessary power supply or load, which does not exist on the layout screen so that the circuit simulation can be executed directly from the layout screen.
[0016]
Furthermore, various analysis methods can be set while designing the layout, and the simulation results can be displayed on the layout screen to feed back useful information to the designer.
[0017]
In this system, parasitic elements (parasitic elements) are extracted from the layout data as equivalent models so that the effects of noise that wraps around the semiconductor substrate that constitutes the LSI and the effects of crosstalk between wires can be analyzed by circuit simulation. In addition to being able to perform circuit simulation directly from the layout screen, it does not exist on the layout screen, but the necessary data, load, etc. can be generated as virtual elements as input data for circuit simulation. Furthermore, various analysis methods can be set while designing the layout, and the simulation results can be displayed on the layout screen to feed back useful information to the designer. Therefore, it is possible to efficiently design a high function LSI.
[0018]
Further, the equivalent model creation means in the semiconductor device design support apparatus of the present invention is created with a mask layer unrelated to the manufacture of the semiconductor integrated circuit with reference to the size of the transistor formed on the semiconductor substrate interface. A function of determining the size of the mask data graphic and generating a mask data graphic of the determined size is provided.
[0019]
The substrate substrate is modeled in the form of a resistor network in which the resistance model is connected three-dimensionally per unit block, and the electrical effect is given by assigning resistance values from the composition and dimensions of the medium within the unit block size. Can be analyzed with a circuit simulator. However, in that case, the practical size of the substrate substrate model is important.
In general, in such a model, the smaller the size, the higher the accuracy of the analysis can be expected. However, the smaller the size, the greater the amount of calculation, and therefore the performance and design time of the computer. Because of this limitation, it is impractical to make the model size smaller than necessary.
[0020]
However, it is possible to generate a substrate substrate model having a desired practical size by generating equivalent model data in a virtual mask layer with reference to the transistor size. The effect becomes.
[0021]
Further, the equivalent model creation means in the semiconductor device design support apparatus of the present invention is such that the size of the mask data figure created in the mask layer unrelated to the semiconductor integrated circuit manufacture is near the interface of the semiconductor substrate or in various wells. Mask data is generated near the boundary, near the boundary of regions with different impurity polarities, near the boundary of regions with different impurity concentrations, or near electrodes, so that it is smaller than the size of the mask data figure in other parts. Means are provided.
[0022]
If the unit block size of the substrate substrate model is too large, there will be a problem in analysis accuracy, and if it is too small, there will be problems in analysis cost and analysis time, so an appropriate size is required. In determining the size, the substrate substrate model having a unit size and a unit size that can be expected to have a certain analysis accuracy can be generated by making the size as described above according to the place.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0024]
(Example 1)
The present invention enables various analyzes (circuit simulation) including parasitic effects depending on the layout pattern while performing LSI layout design, and effectively feeds back the LSI simulation results of the layout design to the designer. It is an object of the present invention to provide a semiconductor device design support apparatus that can perform such operations as means for inputting information such as the shape and arrangement of elements constituting a semiconductor integrated circuit, wiring, physical constants, manufacturing conditions, and an image. Display means for displaying, creating means for extracting linear elements, nonlinear elements, wiring, contact holes, via holes, etc. from the above information and creating equivalent models, and manufacturing conditions necessary for extracting elements and creating equivalent models And storage means for storing physical constants and numerical analysis of the extracted elements and equivalent models A conversion means for converting to a data format, an operation condition input means for inputting operation conditions, an operation means for numerically analyzing the extracted equivalent model, and an output means for outputting the operation result of the operation means In semiconductor device design support equipment,
Means for creating data at the same hierarchical level as the element arrangement and wiring information in a mask layer that is not used for semiconductor manufacturing, and means for storing these information in a form that can be handled by the element extraction and equivalent model creation means With
Furthermore, a means for adding a circuit that does not exist on the LSI to an arbitrary position on the means for displaying the information on the shape and arrangement of the elements and the wiring is provided.
Further, the present invention is characterized by a function capable of selecting and specifying various simulation setting methods and simulation result display methods.
[0025]
FIG. 1 is a block diagram showing a functional configuration of an LSI design support apparatus according to an embodiment of the present invention. In the figure, 1 is layout information input means, 2 is layout information storage means, 3 is display means, 4 is element extraction / equivalent model creation means, 5 is model creation condition input means, 6 is input data creation means, and 7 is computation. Condition input means, 8 calculation means, 9 calculation result output means, 10 additional circuit input means, 11 element extraction data input creation means, and 12 element extraction data storage means.
[0026]
Of these, the layout information input means 1 is a layout value of each circuit element forming material such as an element associated with LSI design, layout information such as shape and size, and parameter values indicating physical constants, manufacturing conditions, material characteristics, etc. And the like. The information storage unit 2 is a unit for storing these pieces of information input by the layout information input unit 1. The display means 3 is means for displaying layout information, parameter information, etc. input by the layout information input means 1. For the sake of simplicity, the layout screen will be used hereinafter.
[0027]
The element extraction / equivalent model creation means 4 is for each circuit element such as a linear element, nonlinear element, wiring, contact hole, via hole, etc. on the design LSI chip obtained based on the layout information stored in the information storage means 2. The design LSI chip can be numerically analyzed by performing circuit simulation of the design LSI chip from the layout information based on the geometric information such as each spatial position and shape, and the parameter value. This is an element extraction / equivalent model creation means for extracting circuit elements such as elements and the like and creating an equivalent model. The elements extracted and created here and the equivalent model are configured so that the display unit 3 can display the elements and equivalent models on the layout screen of the display means 3 with symbols that can be identified by the operator. It is. At this time, as a display form of the extracted circuit elements such as elements, a plurality of elements can be combined and displayed based on the connection relationship. For example, when there are a plurality of transistors in which the connection destinations of all the terminals are common, it is clear that they are described by one symbol.
[0028]
The element extraction / equivalent model creation means 4 is given special information for elements such as parasitic elements and noise that occur in response to the arrangement of circuit elements such as elements and the arrangement of power supplies. As long as there is no, it is not the structure made into extraction object. Therefore, when it is necessary to extract an element such as a parasitic element or the noise to obtain an equivalent model, information for that purpose must be given. This is because these parasitic elements and elements such as noise are generated due to the operation of other circuit elements on the same semiconductor substrate or signals transmitted through the wiring.
[0029]
The model creation condition input means 5 includes information related to the manufacturing process and accuracy of the model or modeling required when the element extraction / equivalent model creation means 4 extracts circuit elements such as elements and creates an equivalent model. This is for inputting model creation conditions such as a region and a position to be performed.
[0030]
The input data creation means 6 is a data creation means for converting circuit elements such as elements and equivalent models extracted and created by the element extraction / equivalent model creation means 4 into a data format that can be numerically analyzed by the calculation means 8. It is. The calculation condition input means 7 is calculation condition input means for specifying an analysis method, an output form of calculation results, and the like. The arithmetic means 8 is an arithmetic means for numerically analyzing the circuit, for example, an arithmetic means for executing a circuit simulation program such as “SPICE” to analyze the circuit. The calculation result output means 9 is calculation result output means for outputting the calculation result.
[0031]
The additional circuit input means 10 uses a pointing device such as a mouse, and the power supply or signal is placed at a desired position on the layout screen of the display means 3 by cooperation of the pointing device and a GUI (graphical user interface) function. A means for element addition editing that adds an external circuit such as a source and a load or an arbitrary element, and processes it so that it is reflected in data. The added circuit and element are also input. Information that can be converted into input data to the calculation means 8 by the data creation means 6.
[0032]
The element extraction data input creation means 11 is necessary for extracting and creating a parasitic element or equivalent model (equivalent element model) different from the element or equivalent model extracted based on the data created by the layout information input means 1. This is a means for automatically or manually creating simple information, and for high-performance analysis using a mask layer, which is a virtual layer that has nothing to do with design information for LSI manufacturing. This is a means for automatically or manually creating necessary parasitic elements and information necessary for extracting and creating an equivalent model.
[0033]
The element extraction data storage means 12 is a means for storing these pieces of information created by the element extraction data input creation means 11, and each piece of information is also recorded by the element extraction / equivalent model creation means 4. Extraction of circuit elements and creation of an equivalent model are executed.
[0034]
FIG. 2 shows a layout screen display example on the display means 3 when an external circuit Cout and a capacitor as an additional circuit Cad are added to the laid-out element pattern Dpt for forming an LSI chip.
[0035]
Next, the operation of the apparatus having the above configuration will be described.
This system is obtained by adding three functional elements of an additional circuit input means 10, an element extraction data input creation means 11 and an element extraction data storage means 12 to the configuration of a conventional LSI design support apparatus. Therefore, the input means 1, the information storage means 2, the display means 3, the element extraction / equivalent model creation means 4, the model creation condition input means 5, the input data creation means 6, the calculation condition input means 7, the calculation means 8, and the calculation result output Each functional element of the means 9 is originally provided in a conventional LSI design support apparatus.
[0036]
The process flow and operation will be described with reference to FIG. 4. First, the system lays out the LSI chip to be designed (step S1). This is done from the input means 1. That is, the operator (designer) operates the input means 1 to arrange layout information such as the location, shape and size of circuit elements such as elements accompanying LSI design, physical property constants, manufacturing conditions, and materials. Input a parameter value or the like indicating the characteristics. This input information is stored in the information storage unit 2. At this time, the display means 3 displays a layout image as the layout information on the layout screen so that the state during input (an image indicating the state during the input operation) and the state after input can be understood. Various setting data are displayed.
[0037]
When the input of necessary information associated with the LSI design is completed, the process proceeds to a process for creating layout data D1-a based on the input necessary information. The layout data creation process includes model creation conditions such as “information relating to manufacturing process”, “model accuracy”, “area to be modeled”, and “position” given from the model creation condition input means 5 Based on the information stored in the storage means 2, the element extraction / equivalent model creation means 4 performs extraction processing of circuit elements such as elements using an element extraction program, and creates an equivalent model ( Step S2).
[0038]
When extraction of circuit elements such as elements and creation of an equivalent model are completed, these data are transferred to the input data creation means 6. In addition, the operator (designer) sets the analysis method designation, the output form of the calculation result, and the like in advance in the calculation condition input means 7, so that the input data creation means 6 uses these element extraction / equivalent model creation means. 4 and data processing using information such as data and conditions from the calculation condition input means 7, the data is converted into a data format that can be numerically analyzed by the calculation means 8. For example, if the circuit analysis software used by the arithmetic means 8 is “SPICE”, which is a typical software for circuit simulation, each element such as “element” which is information necessary for executing this “SPICE” is used. Circuit element connection information, “device size and characteristics”, “physical constants”, “analysis method”, “output format” and the like are generated as a netlist by data conversion processing (step S3), and are given to the calculation means 8 . The computing means 8 performs a circuit analysis simulation based on the inputted net list (step S4), Stain Get the calculation result.
[0039]
Circuit by the arithmetic means 8 Stain When the calculation operation result is obtained, it is passed to the operation result output means 9, and the operation result output means 9 Stain The calculation result is displayed on the display means 3.
[0040]
When the influence of the parasitic element is to be added as an analysis target, the operator sets the system state to the virtual layer setting mode, and operates the element extraction data input creation unit 11 while viewing the layout screen of the display unit 3. In this virtual layer setting mode, a virtual layer is set in a desired size in a desired area. Then, the information is stored in the element extraction data storage unit 12, and the layout information at that time is displayed on the display unit 3 (step S21).
[0041]
On the other hand, information necessary for extraction and creation of parasitic elements and equivalent models (equivalent element models) is automatically or manually created by the element extraction data input creation means 11, and the design information for LSI manufacturing is as follows. Information necessary for extraction and creation of parasitic elements and equivalent models necessary for high-performance analysis is created using a mask layer that is a virtual layer that has nothing to do with it.
[0042]
The element extraction data storage unit 12 stores the information created by the element extraction data input creation unit 11. The element extraction / equivalent model creation means 4 extracts and creates individual parasitic elements and equivalent models based on the stored information. Next, the element extraction / equivalent model creation means 4 In accordance with the parasitic element extraction rule in the virtual layer, parasitic element extraction processing in the virtual layer is performed, and an equivalent model is created (step S2).
[0043]
When the extraction of the parasitic elements in the virtual layer and the creation of the equivalent model are completed, these data are transferred to the input data creation means 6. Then, the input data creation means 6 performs data processing using the data from the element extraction / equivalent model creation means 4 according to the information such as the analysis method designation given from the calculation condition input means 7 and the output form of the calculation results. Data of the equivalent model for the parasitic element for the set virtual layer is converted into a data format (net list) that can be numerically analyzed by the computing means 8 (step S3). In the input data creation means 6, such processing is also performed on the parasitic element data D1-b to generate a net list.
[0044]
The calculation means 8 also performs circuit analysis simulation on the net list for the parasitic element of the virtual layer (step S4), and obtains a simulation calculation result.
[0045]
When a circuit simulation calculation result is obtained by the calculation means 8, it is transferred to the calculation result output means 9, and the calculation result output means 9 displays the transferred circuit simulation calculation result on the display means 3.
[0046]
As a result, it is possible to obtain a circuit simulation result including the influence of the parasitic element in the set desired virtual layer.
[0047]
In this system, the additional circuit input means 10 can place an external circuit Cout such as a virtual signal source and an additional circuit Cad such as a parasitic capacitance at an arbitrary position on the layout screen of the display means 3. ing. When performing circuit simulation of an LSI during design, when an external circuit such as a power supply or a virtual signal source is required or when it is desired to add a parasitic capacitance, the operator uses an additional circuit input means 10 to use a mouse or the like. By operating the pointing device, an external circuit Cout such as a power source or a virtual signal source or an additional circuit Cad such as a parasitic capacitance is placed at an arbitrary position on the layout screen of the display means 3.
[0048]
Then, this information is input to the input data creating means 6 and converted into a circuit simulation input data format (net list) by the input data creating means 6. The calculation means 8 also performs circuit analysis simulation on the net list for these external circuits and parasitic capacitance (step S4), and obtains a simulation calculation result (step S5).
[0049]
When a circuit simulation calculation result is obtained by the calculation means 8, it is transferred to the calculation result output means 9, and the calculation result output means 9 displays the transferred circuit simulation calculation result on the display means 3.
[0050]
As a result, a circuit simulation result including an external circuit and parasitic capacitance can be obtained.
[0051]
Therefore, referring to these circuit simulation results, the layout information such as the location, shape, size, etc. of circuit element forming materials such as elements in the LSI chip is appropriately changed as necessary, and the conditions after the change are changed. If necessary, change the layout information such as the location, shape, size, etc. of the circuit element forming material such as elements in the LSI chip as needed by referring to the circuit simulation result. By repeating circuit simulation under conditions, it is possible to design a desired circuit to be in an optimal state, and this can be done in a short time, making it easy to develop a high-performance LSI. It can be implemented and the development cost can be reduced.
[0052]
The position and shape on the layout corresponding to the circuit elements such as the elements and the model shown on the screen of the display unit 3 and the shape can be distinguished from other layouts by reflecting the result of the calculation by the calculation unit 8. If the output means 9 is provided with a function for processing the output image so that it can be displayed, a semiconductor device design support apparatus that is more convenient to use can be obtained. When the calculation result by the calculation means 8 satisfies a preset condition, an element (circuit element such as an element), element arrangement (arrangement of the circuit element such as the element), or wiring related to the parameter is extracted, Giving the output means 9 the function of processing the output image so that the screen of the display means 3 is displayed in a discriminable state also leads to the provision of an easy-to-use semiconductor device design support apparatus.
[0053]
The above is a rough description of the operation of the LSI design support apparatus according to the first embodiment of the present invention. Next, details of the feature points of the LSI design support apparatus of the present invention related to the first embodiment will be described.
[0054]
The greatest feature of the LSI design support apparatus of the present invention is that three types of "circuit analysis function including parasitic elements", "analysis function by additional circuit input", and "analysis method setting function" are added. The details will be described next.
[0055]
<Example 1-1>
[Circuit analysis function including parasitic elements]
The first feature of the LSI design support apparatus of the present invention resides in means for extracting parasitic elements (element extraction data input creation means 11). The effects of substrates such as substrates and wells can be analyzed by taking these parts as parasitics that depend on layout data and applying them as equivalent models (equivalent element models) consisting of resistance and capacitance components to simulate the circuit. become able to. Therefore, it is the role of the element extraction data input creation means 11 to extract parasitic elements from the layout state of the laid-out LSI chip and apply them as equivalent element models. By providing the data input creation means 11, the influence of the semiconductor substrate such as the substrate and the well can be analyzed and reflected in the design of the LSI chip.
[0056]
The element extraction / equivalent model creation means 4 in FIG. 1 extracts the original circuit constituent elements (circuit elements) from the layout data and converts them into a form that can be simulated. In Paragraph 4, parasitic elements are not extracted and cannot be handled.
[0057]
Therefore, in the system of the present invention, the element extraction data input generation means 11 and the element extraction data 12 are provided so that the parasitic elements can be extracted in order to enable simulation of the effects of the parasitic elements described above. .
[0058]
A virtual layer is used for extracting parasitic elements. And a parasitic element is extracted from the figure drawn by this virtual layer. Here, the virtual layer is a mask layer that exists on the layout screen but is not used for circuit / element design in actual LSI manufacturing.
[0059]
The virtual layer includes a virtual substrate layer (a layer assuming a substrate), a virtual N-well layer (a layer assuming an N-well), a virtual P-well layer (P-well) as layers meaning the physical shape of an LSI substrate. For example). In addition, particularly when there is a portion where parasitic extraction is desired by utilizing the knowledge of the designer, a virtual wiring layer assuming a wiring layer can also be used.
[0060]
As for the LSI substrate portion, the virtual layer has at least two layers of a shallow layer (a shallow virtual layer) and a deep layer (a deep virtual layer) in the depth direction of the LSI substrate. It shall have a structure. That is, because the well portion does not have a depth to the bottom of the LSI substrate, a single layer cannot represent the three-dimensional structure of the LSI substrate. This is the reason for providing a two-layer structure.
[0061]
Thus, at least a two-layer structure is required for the LSI substrate portion. However, if there are many layers, the mesh of the resistor network becomes finer (that is, the unit block size, which is the unit volume dimension to be equivalently modeled), and the accuracy is improved, but the number of nodes increases and calculation time increases. The problem that leads to. Therefore, it is preferable that the mesh is coarse as long as accuracy permits.
[0062]
In this embodiment, as described above, in this embodiment, the LSI substrate is divided into a shallow portion and a deep portion. As a reference for this, the depth of the well is used here.
[0063]
The depth of the well is input in advance as a process parameter. The shallow portion includes an N well, a P well, a shallow portion substrate, and the like, and a deep portion substrate is provided thereunder. It is not always necessary to match the size and position of the mesh of each part. A node (equivalent circuit connection point) of a figure (equivalent circuit unit size) written in a shallow layer and a node (equivalent cuboid as a unit size of equivalent model) written in a deeper layer This is because if a virtual via layer is input between both layers in order to connect (equivalent circuit connection point), it can be generated based on the input virtual via layer.
[0064]
Furthermore, a virtual via layer is also formed on the shallow layer layer for coupling the LSI substrate with elements created above and on the surface of the LSI substrate, such as elements such as transistors and wiring. generate.
[0065]
Since the pad and the substrate electrode may have a feature in the structure in the depth direction, they are extracted separately from the elements on the substrate surface. At that time, since it can be extracted based on actual layout pattern data, it is not necessary to prepare a virtual layer. When a buried layer or an oxide film layer is present in an advanced manufacturing process, it is necessary to add a corresponding layer such as a virtual buried layer.
[0066]
In addition, when a more accurate analysis is desired, the deep substrate can be further divided into a plurality of layers. Furthermore, when element isolation is performed using silicon oxide or the like, a model corresponding to the depth of the trench is prepared, for example, in the case of only a shallow portion or the same depth as the buried layer. Here, it is assumed that the graphic written in each virtual layer has a three-dimensional structure with a thickness although it is expressed in a plane.
[0067]
The following describes the method of extracting the deep substrate part, but the other parts are treated in the same way.
First, a figure (a rectangular parallelepiped as a unit size of the equivalent model) is input with a virtual layer corresponding to a portion to be extracted. At this time, the figure is input using a mouse or the like as in the layout design. However, in the case of a deep part, the figure is continuously input by inputting the size and shape of the figure and the range in which the figure is generated. Can be programmed to occur.
[0068]
In the case of a shallow portion, the figure information of the well or the like already drawn is referred to, and the corresponding mask layer is overlaid to give a figure of any size (divided block (equivalent model unit block) as the unit size of the equivalent model. Can be programmed to generate a cuboid). In this way, when drawing the same figure more than once, if you enter the size of one figure and generate the same figure multiple times by automatic figure generation, this same figure multiple drawing operation is easy. Can be done. Moreover, in any layer, if the figure to be generated is limited to a rectangle or particularly a square, there is an advantage that it is easy to fill a plane without a gap even if there is a pad, a substrate electrode or the like.
[0069]
In addition, if a figure is generated by inputting how many areas to divide, the part that you want to analyze with high precision using the designer's knowledge can be divided more finely. It becomes possible to implement feedback that divides the part that you want to analyze well and re-analyze it.
[0070]
The size of the figure (equivalent model unit block) written in each virtual layer needs to be set optimally based on the resistivity of the portion. For example, the well portion has a higher resistivity than the substrate portion, so if the figure size is set too large, the lateral resistance value parallel to the substrate surface is the depth direction of the substrate. It becomes larger than the resistance value. Then, only the current flows into the deep layer, which is a low resistance substrate, and there is no flow flowing in the well in the lateral direction. In this case, the effect of the edge of the well cannot be examined.
[0071]
On the other hand, if the size of the figure is set too small, the number of elements and the number of nodes increase, leading to an increase in circuit simulation calculation time, resulting in inefficiency.
[0072]
Therefore, it is necessary to optimally set the size of the graphic written in each virtual layer based on the resistivity of the portion.
[0073]
As an example of setting the size of the figure (equivalent model unit block), the size of the figure (equivalent model unit block) written in the shallow virtual layer can be matched with the depth of the well. In this way, since the vertical resistance value and the horizontal resistance value in the well are approximately the same, the effect of the edge of the well can be analyzed. Similarly, the size of the substrate in the deep part can be efficiently analyzed by setting it in accordance with the depth.
[0074]
As an example of a figure (equivalent model unit block) drawn in a virtual layer, consider a rectangular parallelepiped as shown in FIG. Of course, the present invention is not limited to this, and even if it is expressed by a block of another shape, it can be similarly extracted.
[0075]
The equivalent element model as shown in FIG. 3 represented by a rectangular parallelepiped figure has six faces (that is, a total of six faces FC1 to FC6), so that these faces correspond to these faces. There are a total of six nodes, upper and lower end nodes (NU, ND), left and right end nodes (NL, NR), and front and rear end nodes (NF, NB), which serve as electrical connection points with other adjacent equivalent element models.
[0076]
Among these, the upper end node NU is a node extending toward the upper surface FC1 in the rectangular parallelepiped, the lower end node ND is a node extending toward the lower surface FC2 in the rectangular parallelepiped, and the left end node NL is a node extending toward the left side surface FC6 in the rectangular parallelepiped. The right end node NR is a node extending toward the right side FC5 in the rectangular parallelepiped, the front end node NF is a node extending toward the front side FC3 in the rectangular parallelepiped, and the rear end node NB is on the rear side FC4 in the rectangular parallelepiped. It is a node that stretches toward you.
[0077]
The equivalent element model expressed in the area of a rectangular parallelepiped figure shows that the resistance component can be considered as a representative element when the target is a substrate, so that the nodes are connected by resistance component elements. .
[0078]
That is, when the target is a substrate, an equivalent element model represented by a rectangular parallelepiped figure is an area between upper and lower end nodes (between NU and ND), between left and right end nodes (between NL and NR), and between front and rear end nodes ( In each of the NF-NB), since the resistance is a typical element, an equivalent circuit is expressed as a configuration connected by the resistance component. The magnitude of the resistance is determined by the resistivity of the substrate and the size of the cuboid figure. However, the equivalent element model needs to have a capacitive component when the signal to be handled is faster than the time constant determined by the dielectric constant of the material.
[0079]
When the equivalent element model is adjacent to the side node (nodes NF and NB at the front and rear ends or nodes NR and NL at the left and right ends), the equivalent element model has a side surface of the adjacent equivalent element model. Connected with the node.
[0080]
For an equivalent element model placed on the outermost side so that a floating node cannot be formed, an equivalent element model expressed in a configuration having no node connected to the side surface corresponding to the outermost side is prepared and applied. . Alternatively, by preparing a model in which each node is grounded through a high resistance with little influence, and applying this model, it is possible to avoid the problem of a floating node in one type of model.
[0081]
In the equivalent element model of the substrate, the bottom node (ND) is connected to the ground, that is, the ground (GND). This is because the LSI is usually bonded onto a metal surface having a low resistivity when it is housed in a package, and the metal surface is often connected to the ground (GND). When it is necessary to simulate the situation when the bottom surface side of the LSI chip is not dropped to the ground (GND), or when it is desired to analyze the influence of the bottom surface of the substrate in more detail, the node (ND) on the bottom surface of the equivalent element model is set. Furthermore, it is necessary to connect with a resistance network.
[0082]
At this time, the substrate resistance network can be extracted by using a layer generated based on the input virtual layer in the deep part, and it is not necessary to add a new virtual layer. Alternatively, a model without a node on the bottom surface (a model without ND) can be prepared from the beginning.
[0083]
The node (NU) on the upper surface of the equivalent element model of the virtual part in the deep part is connected to a rectangular figure drawn in the virtual layer in the shallow part via the virtual via layer generated from the virtual layer in the input board part. ing.
[0084]
FIG. 5 shows the positional relationship between a rectangular parallelepiped figure (equivalent model unit block) of a deep virtual part and a rectangular parallelepiped figure (equivalent model unit block) of a shallow virtual layer. Here, L1 is a deep virtual layer, L3 is a shallow virtual layer, L2 is a virtual via layer, and L4 is a virtual via layer on the substrate surface. Here, the size of the figure (equivalent model unit block) of the virtual layer L1 in the deep part and the size of the figure (equivalent model unit block) of the virtual layer L3 in the shallow part do not match, but in the case of FIG. In this example, four nodes on the bottom surface of the virtual layer L3 in the shallow part are connected to one node on the top surface of the virtual layer L1 in the deep part via the virtual via layer L2.
[0085]
The figure (equivalent model unit block) written in this virtual layer is extracted by the element extraction function (function possessed by the element extraction / equivalent model creation means 4) provided in the layout CAD (computer design support apparatus), and the input data The data is written into the input data format of the circuit simulator by the data creation function of the creation means 6.
[0086]
The element extraction function provided in the layout CAD is a function of the element extraction / equivalent model creation means 4, which is realized by executing an element extraction program. By executing this program, element extraction (extraction of circuit elements such as elements) is performed. This is performed according to a preset element extraction rule. The element extraction rule is prepared as a file, and the element extraction process can be executed by referring to the extraction rule file describing the element extraction rule.
[0087]
At this time, the relationship between the three-dimensional structure of the figure and the equivalent model is also input to the extraction rule file referred to by the element extraction program. The same applies to other virtual layers.
[0088]
The equivalent element model of the substrate is expressed by a simple resistor network. Like the junction capacitance of the PN junction surface at the interface where the layers of different conductivity types are in contact, such as the P-type substrate and the N-type well, If a simple capacitance component or a voltage-dependent nonlinear capacitance component is provided and the effect of the joint surface is taken into consideration, a more accurate simulation can be executed.
[0089]
The wiring is extracted as a conventional circuit of R, L, C, G components such as T type, L type, and π type. Furthermore, by preparing an equivalent model in advance, it is possible to distinguish and extract a straight line portion and a bent portion. Further, as shown in FIG. 6, the equivalent element model has an arbitrary number of stages by overwriting input setting with a small size so that the wiring virtual layer Lp is divided into an arbitrary size on the wiring pattern PL. A lumped parameter model M can be substituted. FIG. 6 is an example in which the wiring portion is extracted by a plurality of L-type lumped constant models, and is an example in which the wiring portion is extracted by an L-type lumped constant model including a resistance component (R component) and a capacitance component (C component).
[0090]
Here, the figure (equivalent model unit block) to be overwritten with the virtual wiring layer on the wiring part can be automatically generated by setting the size of the figure as in the case of the virtual well, or the number of divisions can be set. It can also be generated automatically. Each of these advantages is the same as in the case of the virtual well. At this time, the set size can be given as a function of the frequency of the signal to be handled.
[0091]
That is, it becomes possible to determine whether or not to extract the parasitics of the wiring portion by inputting the frequency of the signal to be handled by the circuit under design, and to determine the optimum size of the figure to be generated. In addition, by inputting a range to be considered, it is possible to insert a wiring capacitance. At this time, the value of the inter-wiring capacitance is determined by the interval and length of the portions running in parallel.
[0092]
The resistance value, the capacitance value, and the like constituting each equivalent model are determined by physical constants, manufacturing conditions, the size of a unit figure, and in some cases, circuit operating conditions.
[0093]
The above parasitic element extraction operation can be limited to a specified range for the entire circuit.
[0094]
In addition, in the case of being composed of only linear elements as in the substrate model, unnecessary nodes can be omitted by obtaining a transfer function as preprocessing. Furthermore, due to requirements such as simulation accuracy requirements and calculation time reduction requirements, pre-processing such as replacing each part with a simpler model, or combining each specified area to reduce the number of nodes It is also effective to prepare as
[0095]
<Example 1-2>
[Analysis function with additional circuit input]
The second feature of the LSI design support apparatus according to the present invention is that an additional circuit input function is provided.
Normally, when a designer is designing a layout, data extracted from the layout data is used for comparison with schematic data for verification. On the other hand, circuit simulation has been performed based on this schematic data. The difference between the two data is that the schematic data has a power source, a signal source, and a load that do not exist on the LSI chip, which are necessary for executing the circuit simulation.
[0096]
However, as described above, in order to execute a more accurate simulation, it is necessary to perform a simulation based on the layout data. Therefore, according to the present invention, a circuit simulation can be performed by providing a function that can add a power source, a signal source, and a load necessary for executing the circuit simulation to the layout data. This will be described in Example 1-2.
[0097]
The additional circuit input means 10 of FIG. 1 prepares a pointing device such as a mouse and a GUI function, and can be moved to an arbitrary position on the layout screen of the display means 3 in cooperation with the GUI function by operating the mouse or the like. An external circuit Cout such as a power source or a virtual signal source and an additional circuit Cad such as a parasitic capacitance can be provided. On the layout screen, each signal source (Cout, Cad, etc.) is displayed as a symbol using a corresponding symbol prepared in advance.
[0098]
This symbol display data (symbol data) is also inputted from the additional circuit input means 10 to the input data creating means 6 and converted into the input data format of the circuit simulation by the input data creating means 6. These additional circuits Cad can also be designated as a virtual power source such as a noise source having a certain area.
[0099]
7 and 8 show display examples.
FIG. 7 shows a state where a power source (equivalent noise source) Enoise is added as an additional circuit Cad at a certain point on the layout screen in the display means 3. In other words, if an element pattern Dpt is laid out in a certain area on a semiconductor substrate for LSI design, a power source (equivalent noise source) is used to indicate that there is a noise source near the laid out element pattern Dpt. A state in which Enoise is added as an additional circuit Cad is shown. In addition, the added signal source can be set to have a function as a control power source. For example, the output of an arbitrary node set from the outside can be used as the control signal, or the control signal of the signal source can be set. It is possible to deal with various kinds of analysis.
[0100]
Such setting can be performed by, for example, instructing the layout information input unit 1 or the like after setting the additional circuit Cad. 6 creates data that uses the output of an arbitrary node set from the outside as its control signal and gives it to the computing means 8 or creates data that gives the control signal of the signal source arbitrarily. This is given to the calculation means 8.
[0101]
FIG. 8 shows a state where an equivalent noise source is set in a square area and displayed as a symbol, and Ensa is an equivalent noise source area displayed in the square area. That is, FIG. 8 shows an example in which the power source (equivalent noise source) Enoise is set close to a certain element pattern Dpt so as to give a state in which it has a rectangular area. In the equivalent model of the format as shown in FIG. 8 in which the equivalent noise source is set in the area display format, this corresponds to that a plurality of power sources (equivalent noise sources) Enoise are connected in the area at equal intervals. become. In this case, the number of equivalent miscellaneous power supplies depends on the accuracy of the equivalent model. Such a setting can also be performed by giving an instruction for the setting by the layout information input means 1 or the like after setting the additional circuit.
[0102]
The signal source added by the additional circuit input means 10 is displayed on the display screen with a desired area on the layout screen of the display means 3. The display position and display area reflect the influence of the signal source on each circuit element on the semiconductor substrate, and the input data creating means 6 creates data and gives it to the computing means 8. As a result, it is possible to simulate the influence of the signal source in various situations.
[0103]
<Example 1-3>
[Analysis method setting function]
The third feature of the LSI design support apparatus according to the present invention is the setting function of the circuit analysis method. In the present system shown in FIG. 1, the circuit analysis is performed by the calculation means 8, and this calculation means 8 is an arithmetic processing means for performing circuit simulation, and is installed in “SPICE” which is software for circuit simulation. This is a circuit simulator for performing a typical circuit simulation. As described above, in this circuit simulator, the circuit simulation calculation result can be obtained by inputting connection information of circuit elements such as elements, device size and characteristics, physical constants, analysis method and output format.
[0104]
The circuit simulator can be executed as a single simulation as before, but the function is configured so that the layout information can be analyzed from the layout screen, such as transient analysis, AC analysis, noise analysis, sensitivity analysis, and steady state analysis. . This can be done by specifying any analysis method among transient analysis, AC analysis, noise analysis, sensitivity analysis, steady state analysis, etc. on the layout screen by the calculation condition input means 7 so that the analysis by the specified analysis method is performed. This is realized by the configuration in which the input data creating means 6 creates data so that the means 8 can execute the data.
[0105]
By providing the input data creation means 6 with such a function, the calculation condition input means 7 allows any arbitrary analysis among transient analysis, AC analysis, noise analysis, sensitivity analysis, steady analysis, etc. on the layout screen. If a method is designated, the calculation means 8 performs analysis by the analysis method and obtains a circuit simulation result.
[0106]
Of the settings for analysis, the node whose output is to be viewed can be specified by performing a setting operation with a pointing device such as a mouse on the layout screen or the schematic screen. The layout information input means 1 outputs the designation information based on the setting operation information by a pointing device such as a mouse.
[0107]
Thus, when a node can be specified on the layout screen and a circuit simulation can be performed, for example, how much elements (circuit elements such as elements) are within the range from the digital circuit portion on the LSI chip. It is possible to feed back to the layout design the positional information on whether there is any noise. It is possible to set a plurality of nodes for which the circuit simulation analysis result is desired.
[0108]
The power supply, signal source, and load characteristics necessary for executing the circuit simulation are given by the additional circuit input means 10 or written in advance in a file prepared for providing basic information to be referred to in the circuit simulation. This can also be set. The circuit simulation analysis result is displayed as numerical data and, if necessary, in a graph format so that the characteristics can be visually read.
[0109]
Furthermore, a node can also be specified from symbols generated on the layout screen in advance. For example, when performing sensitivity analysis, etc., a large number of analysis results are output. Therefore, if an element (circuit element such as an element) to be analyzed can be designated on the layout screen, design time can be shortened.
[0110]
In addition, display programs having various display modes (output modes) are prepared, whereby the system can display analysis results that are easy for the user to use or easily grasp the state.
[0111]
For example, when the standard display mode is selected, the analysis result displays the elements (circuit elements such as elements) and their parameters in a table format. When an element (circuit element such as an element) or a parameter thereof is designated, an analysis result is displayed in a graph format. It is also possible to specify an output mode in which the analysis result is displayed as a corresponding element (circuit element such as element) area on the layout screen or a symbol of the element (circuit element such as element). Displaying in this output mode has the effect that position information can be fed back to the design. Furthermore, among the parameters of the displayed elements (circuit elements such as elements), the number when displaying a plurality of elements having a large influence and the threshold value when displaying an element having an influence over a certain value are set. Can be specified.
[0112]
These are effective for shortening the circuit design time with desired performance.
For noise analysis by circuit simulation, a signal source is set as an equivalent noise source at an arbitrary position on the layout screen, and its influence is analyzed. If the equivalent noise source added on the layout screen has a function as a control power source, and the control signal can be arbitrarily specified or given from the output of the specified node, This leads to an understanding of the characteristics and provides effective information for countermeasures against noise.
[0113]
That is, as described with reference to FIG. 7, a power supply (equivalent noise source) Enoise is added as an additional circuit Cad at a desired position on the layout screen in the display means 3. In other words, if an element pattern Dpt is laid out in a certain area on a semiconductor substrate for LSI design, a power source (equivalent noise source) is used to indicate that there is a noise source near the laid out element pattern Dpt. Let's add Enoise as an additional circuit Cad. Then, the added signal source is set so as to have a function as a control power source. As a result, when an equivalent noise source is placed in an arbitrary region, the influence of the equivalent noise source on nearby circuits can be analyzed.
[0114]
Such setting can be performed by, for example, instructing the layout information input unit 1 or the like after setting the additional circuit Cad. 6 performs processing such as creating data that gives equivalent noise to the surrounding circuits and giving it to the computing means 8.
[0115]
Further, when the equivalent noise source Ensa in the square area as shown in FIG. 8 is set, a state corresponding to that a plurality of power sources (equivalent noise sources) Enoise are connected in the area at equal intervals. In this case, the input data creating means 6 expresses the equivalent noise by the distribution of a plurality of equivalent models, creates data that affects the surrounding circuit from the distributed equivalent model, and calculates this. Processing such as giving to the means 8 is performed.
[0116]
As a result, it is possible to simulate the influence of the noise signal in various situations.
[0117]
In this way, the equivalent noise source added on the layout screen has a function as a control power source, and the control signal can be arbitrarily specified or given from the output of the specified node. This leads to an understanding of the characteristics of noise and provides effective information for countermeasures against the noise.
[0118]
In general LSI design procedures, circuit design is performed first, and then layout design is performed. The circuit design is performed while repeating the analysis in the circuit simulation until it is confirmed that desired characteristics are obtained. Subsequent layout design is performed taking into account the effect of degrading circuit characteristics depending on the layout pattern.
[0119]
By extracting elements from the completed layout pattern and comparing them with the schematic data used at the time of circuit design, or by performing circuit simulation using the extracted data and checking the characteristics of the circuit, the validity of the layout data can be verified. Can be verified.
[0120]
Furthermore, by extracting elements including parasitic effects between wirings, or extracting the model so that it can be analyzed including the effects of the board using the functions described above, the effects of effects that depend on the layout pattern are also affected. Can be analyzed.
[0121]
However, verification by so-called after simulation cannot be performed unless layout design is completed at the circuit block level. Even if the parasitic effect or the like is analyzed at the circuit block level, the portion contributing to the deterioration of the circuit characteristics may not be identified. In addition, if layout data needs to be modified to correct layout design errors or improve the effects of parasitics, it will involve extensive correction work, which wastes design time and creates new layout errors. It leads to the danger to produce.
[0122]
Therefore, if the model is extracted and the circuit simulation can be executed even during the layout design, it will be possible to make fine corrections as appropriate, leading to a reduction in design time and contributing to deterioration of circuit characteristics. It can be specified and is extremely effective for optimal LSI design.
[0123]
Elements that are not yet on the layout data are complemented using elements on the schematic data. This applies to the elements on the layout data and the corresponding schematic. I This is possible by assigning the same name as the element on the data.
[0124]
Similarly for wiring, I It can be compensated by associating node names on the data. If the elements and wirings used for complementation are displayed as symbols and lines on the layout screen, the connection relationship can be verified by the eyes of the designer.
[0125]
Partial element extraction from the completed layout data is also very effective in identifying a portion that has degraded circuit characteristics depending on the layout. This is effective not only when the element is a transistor or the like but also when wiring is arranged. It is possible to select an optimal position and shape by replacing only the wiring portion to be arranged with an equivalent model and repeating the analysis by circuit simulation.
[0126]
As a method for specifying a range for element extraction on the layout screen, a method for inputting a range with a mouse or the like, a method for automatically setting a range visible on the current window screen, and the like are useful. Furthermore, when a specified part is modeled, a window for displaying the equivalent circuit or the value of the S parameter or the Y parameter is opened, and the equivalent circuit or the value of the parameter is displayed there. Then, the influence between elements, between wirings, etc. can be judged quantitatively.
[0127]
If the window once opened is left until there is an instruction to close it, the equivalent circuit before and after the change of the layout pattern or various parameters can be compared.
[0128]
For experienced designers, when the equivalent circuit including element values and the values of various circuit parameters are displayed, the effect on the circuit characteristics of the modeled part can be understood without performing circuit simulation. it can. This leads to a significant reduction in LSI design time. When a substrate substrate or the like is modeled by an equivalent circuit such as a resistor network and extracted in a format that allows circuit simulation, an important issue is how to select the mesh of the resistor network.
[0129]
As described above, when the mesh is too coarse, the accuracy is poor and the reliability of the simulation result is lowered. If the mesh is too fine, the number of extracted elements is too large, leading to an increase in the calculation time of the circuit simulation, or inconvenience that the calculation may become impossible due to the limitation of the memory of the computer.
[0130]
Therefore, it is desirable to finely divide the mesh at places where the influence on the circuit characteristics is large and improve the accuracy of the analysis, and to increase the precision of the analysis at places where the influence is small to suppress the increase in the number of elements. The size of the figure written in the virtual layer for model extraction is initially set large.
[0131]
For example, one figure corresponding to the size is assigned to the well portion. After that, while repeating the simulation, the area where the influence on the signal at the terminal related to the output signal of the circuit or the specification of the circuit is greatly reduced. Focusing on a certain item in the frequency characteristics and transient response of the circuit, it is used as an index to determine the influence on the circuit characteristics. When the designer sees the difference value and determines that it is necessary, the mesh is reduced.
[0132]
That is, the size of each figure written in the virtual layer is reduced. It is also effective for shortening the design time to program the operation to automate this operation by setting the judgment reference value of the difference in advance.
[0133]
Instead of changing the size of the mesh with a constant resistor network model, multiple levels of models are prepared like the conventional transistor model, and each time a specification is received, a more precise The method of replacing with a model is also effective for the same purpose.
[0134]
The conventional parasitic element extraction method has been to extract using a model prepared in advance in accordance with the difference in the embedded shape of a substrate such as a substrate or a well. To that end, a model had to be prepared for every structure made on the substrate.
[0135]
However, substrate parts, N-type and P-type wells, buried layers, oxide film parts, polysilicon layers, aluminum wiring parts, etc. are prepared in advance as submodels in accordance with the cross-sectional structure of the LSI. It is also conceivable to generate a model of a certain size using the sub-model of the difference in the structure in the depth direction for each size range of the written figure.
[0136]
Even with this method, it is possible to set the method of cutting the mesh treated as a model uniformly, or as described above, it is possible to gradually refine the necessary portion from a large one while repeating the analysis.
[0137]
As described above, the present system described in the first embodiment includes the input means for inputting the shape and arrangement of the elements constituting the semiconductor integrated circuit, the wiring, the physical constants, the manufacturing conditions, the calculation conditions, and the like, and the input information. Display means for displaying the analysis results, equivalent model creation means for extracting circuit elements such as linear elements, nonlinear elements, wiring, contact holes, and via holes from the information, and creating equivalent models, and equivalent model creation means A data format conversion means for converting the equivalent model obtained by the above into a data format that can be numerically analyzed, and the extracted equivalent model is converted into a numerical value based on the data converted by the data format conversion means and the calculation condition. And an output means for outputting the calculation result of the calculation means to the display means.
[0138]
Moreover, in the semiconductor device design support apparatus having such a configuration,
Means for creating data at the same hierarchical level as the element arrangement and wiring information in a mask layer that is not used for semiconductor manufacturing, and means for storing these information in a form that can be handled by the element extraction and equivalent model creation means With
Furthermore, a means for adding a circuit that does not exist on the LSI chip to an arbitrary position on the means for displaying information on the shape and arrangement of the elements and the wiring is provided.
Also, a function for designating various simulation setting methods and simulation result display methods from the means for displaying information on the shape, arrangement, and wiring of the elements is provided.
[0139]
Then, the semiconductor device design support apparatus of the present invention having such a configuration displays the shape and arrangement of elements constituting the semiconductor integrated circuit, wiring, physical property constants, manufacturing conditions, calculation conditions, and the like by inputting means. The input information is displayed on the means. At this time, the shape and arrangement state of the elements and wirings are displayed on the layout screen (image display state screen that shows the layout state), and the equivalent model creation means uses the information to obtain linear elements and nonlinear elements. Then, wiring and the like are extracted to create an equivalent model, and the data format conversion means converts the equivalent model obtained by the equivalent model creation means into a data format that can be numerically analyzed. Then, the calculation means numerically analyzes the extracted equivalent model based on the data converted by the data format conversion means and the calculation conditions, and the output means outputs the calculation result of the calculation means to the display means. For example, output and display.
[0140]
In such a system of the present invention, when designing an integrated circuit, the influence of noise that wraps around the semiconductor substrate constituting the integrated circuit and the influence of crosstalk between wirings can be analyzed and processed by a calculation means in circuit simulation. A parasitic element component that does not appear in the design circuit can be extracted from the layout data as an equivalent model, and can be converted into a circuit simulation input data format.
[0141]
The circuit simulation can be freely generated at any position as a virtual element, such as a necessary power supply or load, which does not exist on the layout screen so that the circuit simulation can be executed directly from the layout screen.
[0142]
Furthermore, various analysis methods can be set while designing the layout, and the simulation results can be displayed on the layout screen to feed back useful information to the designer.
[0143]
Therefore, it is possible to efficiently design a high function LSI.
[0144]
(Example 2)
By the way, according to the above-mentioned “Document 1”, the substrate substrate is modeled in the form of a resistance network in which the resistance model shown in FIG. 3 is connected three-dimensionally per unit block, and the composition of the medium within the size of the unit block. It is shown that the electrical influence can be analyzed by a circuit simulator by giving a resistance value from the dimensions and the like.
[0145]
In that case, however, knowledge about the practical size of the substrate substrate model is required.
[0146]
In general, it is known that in such a model, the higher the size, the higher the accuracy of the analysis can be expected. However, the finer the size, the greater the amount of calculation. It is impractical to reduce the size of the model more than necessary due to the performance and design time constraints.
[0147]
Therefore, next, an embodiment of a semiconductor device design support apparatus that enables efficient analysis by clarifying the practical size of the substrate substrate model (unit block size of the equivalent model of the substrate substrate portion) will be described. .
[0148]
<Example 2-1>
The feature of the LSI design support apparatus of the present invention shown here as an embodiment is that a substrate substrate model of a practical size (a substrate substrate model in which a practical equivalent model unit block size is obtained from the relationship between accuracy and calculation efficiency) ).
[0149]
In general, a substrate substrate model as shown in FIG. 3 has a rectangular parallelepiped shape of a predetermined size as a unit block, which is used as a modeling target region, and the unit block as the modeling target region is formed by a resistor network. This is an equivalent circuit model. It is known that a highly accurate analysis can be performed by reducing the size of the unit block and making the substrate portion a finer resistor network.
[0150]
Here, in the substrate substrate model of FIG. 3 in which the unit block shape is a rectangular parallelepiped shape, each node (NU, NF, ND, NB, NR, NL) is each side surface (cuboid surface FC1, FC2, cuboid) having the node. It can be seen that the points representing the region of FC3, FC4, FC5, FC6) are represented. That is, each side surface in the rectangular parallelepiped unit block is considered to be an equipotential surface.
[0151]
Therefore, the size of the substrate substrate model (unit block size) represents the size of a region that can be expressed as an equipotential surface in the analysis.
[0152]
Here, the substrate substrate model of FIG. 3 represents the unit block shape as a rectangular parallelepiped shape, and the following explanation is also made as a rectangular parallelepiped shape, but the essence of the present invention is to fill the plane with respect to the shape of the substrate substrate model. Any polygonal prism, such as a triangular prism or a hexagonal prism, can be used, and it does not necessarily have to be a rectangular parallelepiped.
[0153]
Next, an example of a typical model of a transistor is shown in FIG. In the analysis of a normal circuit, such a well-known transistor lumped constant model is used as a transistor model. In the model of FIG. 9, like the gate G, the drain D, and the source S, the bulk or back gate B that actually has a certain region is handled by one node.
[0154]
Although some elements include the effect of transistor size, such as parasitic capacitances (Cg5, Cgd, Cgb, Cdb, Csb), the back gate B is treated as one node having no region.
[0155]
That is, the interaction between the transistor and the substrate substrate is performed via a node “B” which is a representative point of the transistor. Accordingly, the region of the substrate portion viewed from the transistor formation region portion (the side opposite to the channel region and the gate G, source S, drain D connected by the parasitic capacitance as viewed from the gate side) and the size of the substrate substrate model. In the substrate substrate model, the equipotential surface determined by (the size of the unit block) (in this case, the equipotential surface is the same as the surface of the transistor forming region for one element and the opposite surface of the substrate region facing it). It turns out that it is a reasonable size.
[0156]
Even if the node on the substrate side is finely divided in accordance with the internal structure of the transistor for one element (even if the unit block size is reduced to match the internal structure of the transistor for one element), the transistor and the substrate Since there is only one node connecting the two, the spatial resolution finer than the size of the transistor is redundant, leading to an increase in the number of elements and the number of nodes, leading to a deterioration in the computational efficiency of the analysis.
[0157]
Therefore, one of the ways to determine the practical size of the substrate substrate model (the practical unit block size of the substrate substrate model) is to refer to the size of the elements such as transistors made on the substrate. This is a method to match the size of the element formation region. The size of the upper surface of the substrate model at a position facing the element region formation surface of a transistor or the like may be determined as follows.
[0158]
[I] First, the top surface shape of the smallest square or rectangle that completely includes the area of the layout data figure for forming the gate, source, and drain of the transistor.
[0159]
[Ii] Second, the top surface shape of the region corresponding to the region sandwiched between the layout data for forming the source and drain, corresponding to the portion for forming the channel of the transistor, is used.
[0160]
[Iii] Third, a layout that forms all the source, drain, and gate portions of a plurality of transistor groups that share at least one source or drain portion and are connected to be supplied with the same gate voltage. The top surface shape of the smallest square or rectangle that completely includes the data graphic area.
[0161]
[Iv] Fourth, an upper surface shape corresponding to a region satisfying a condition for recognizing a transistor by an element extraction rule of layout CAD is adopted.
[0162]
The size specified in any of the above methods is used as the transistor size, and the size of the substrate substrate model is determined accordingly.
[0163]
In the first embodiment, a concept of interposing a virtual mask layer not involved in LSI manufacturing is introduced, and an element such as a transistor and each model of a substrate of a layer below the virtual mask layer are interposed through the virtual mask layer. By finding the equivalent coupling relationship, the substrate substrate model can be extracted as a parasitic element. Therefore, the substrate having the desired practical size can be generated by referring to the size of the transistor and generating data in a virtual mask layer that is not involved in LSI manufacturing. A substrate model can be generated.
[0164]
FIG. 10 shows the relationship between the transistor Tr, the unit area (virtual layer unit area) UA set in the virtual layer (virtual mask layer) Li, and the substrate substrate model Smodel.
[0165]
This shows an example according to the method of determining the size of the first transistor (method [i]). Here, as described above, the virtual layer Li is a virtual layer for combining an element and an equivalent model of the board on the LSI board for extracting the parasitic elements, and exists on the layout screen. However, it is a mask layer that is not used at all for circuit / element design in actual LSI manufacturing.
[0166]
As described above, in the embodiment 2-1, the equivalent model data in the virtual mask layer is generated with reference to the transistor size, so that the sub-size having the target practical size is generated. An effect is obtained that a straight substrate model can be generated.
[0167]
Next, if the unit block size of the substrate board model is too large, problems remain in the analysis accuracy, and if it is too small, problems such as analysis cost and time required for analysis will occur, so an appropriate size is required. In determining the size, a method for generating a substrate substrate model having a unit block size that can be expected to have a certain analysis accuracy will be described in detail.
[0168]
<Example 2-2>
The fifth feature of the LSI design support apparatus of the present invention is that the element extraction data input creation means 11 can generate a substrate substrate model having a shape that can be expected to have a certain analysis accuracy. In There is to do.
[0169]
According to the reference 1 shown above, different analysis results are obtained by changing the direction of finely chopping the substrate model, that is, the direction of finely chopping the substrate resistor network, in the depth direction on the substrate and the plane direction on the substrate, respectively. It has been shown that
[0170]
However, circuit designers do not always have knowledge about how to make effective substrate resistor networks. If the substrate resistor network is not cut correctly, the analysis result may include a large analysis error.
[0171]
Therefore, it is necessary to avoid the generation of a substrate substrate model that causes a large analysis error.
[0172]
Ideally, if the substrate substrate model shown in FIG. 3 is always in a cubic unit block shape, analysis can be performed without worrying about fluctuations in accuracy due to the shape of the model. In reality, however, the resistivity of the substrate varies depending on the depth direction of the substrate due to the presence of wells and buried layers.
[0173]
Therefore, it is necessary to prepare a separate substrate substrate model in accordance with the resistivity of each structure in the depth direction of the substrate substrate.
For example, the well portion generates a model of a well portion composed of a resistance element having an element value determined by the resistivity and dielectric constant of the well and a capacitance element. However, if the substrate model is a cubic unit block that is sized according to the well depth, the well depth is thinner than the substrate thickness. In addition, many substrate substrate models are generated only in the well portion, which leads to a significant increase in the number of elements and the number of nodes in the entire substrate.
[0174]
Therefore, in the embodiment 2-2 of the present invention, when the unit block size of the substrate substrate model is set to vertical a, horizontal b, and height c so that this can be properly maintained, it is determined from the model cube. Slip
c < 10xa, c < 10xb
To allow.
[0175]
In this way, an increase in the number of elements and the number of nodes can be avoided while suppressing a decrease in accuracy. It is necessary to prepare a substrate substrate model that changes the element value according to the structure in the depth direction of the substrate, but the size of each model is based on the physical size of the structure in the depth direction. Decide.
[0176]
This is based on the input information from the model creation condition input means 5 in the system of FIG. 1 and the layout information stored in the layout information storage means 2. Specifically, the thickness of the substrate substrate and its thickness The specified value for the number of layers to be expressed, the planar size and depth of the well portion, the thickness of the buried layer, and the depth of the buried layer, the thickness of the insulator layer, and the insulator layer The depth, the width, the length, and the depth of the trench, and the size of the substrate electrode.
[0177]
Using these dimensional information, the unit block size length a, width b, and height c of the substrate model at each position of each layer are determined.
c < 10xa, c < 10xb
Modeling to effectively fill the three-dimensional space while suppressing the increase in the number of elements and the number of nodes by causing the element extraction data input creation unit 11 to execute data creation processing while appropriately adjusting within a certain range. Can do.
[0178]
A specific example of generating a substrate substrate model having a unit block having a shape and dimension that can be expected to have a certain analysis accuracy while suppressing an increase in the number of nodes or the number of elements will be described below.
[0179]
<Example 2-3>
The sixth feature of the LSI design support apparatus of the present invention is to generate a substrate substrate model having a shape and dimension so that a certain analysis accuracy can be expected while suppressing an increase in the number of nodes or the number of elements. An example of this will be described below as Example 2-3.
[0180]
In general, it is known that the finer the substrate resistor network is cut, that is, the smaller the unit block size is, the more accurate the analysis can be. This is not practical.
[0181]
Therefore, in the present invention, a fine substrate resistance network is formed in the vicinity of the substrate substrate interface, in the vicinity of various well boundaries, in the vicinity of the electrodes, etc. (so as to form a fine unit block), and in other regions it is rough. The virtual layer graphic (shape pattern) is generated so that the unit block has a large size.
[0182]
Specifically, for example, as shown in FIG. 11, a layer L0 including a boundary surface f that can be assumed to be discontinuously in contact with a well portion and a substrate portion, and a plurality of layers La from the layer L0. The substrate model (equivalent model of the substrate substrate) should be smaller than the substrate model of the outer layers Lb and Lc. For example, the size (unit block size) of the board model in which the size to be modeled is set to be smaller than the size of the board model in which the size to be modeled is set to “vertical”, “horizontal”, “height” Are each ½. In other words, the size of the small board model is halved for “vertical”, “horizontal”, and “height” of the large board model.
Here, for the sake of simplicity, in FIG. 11, the resistor network is represented by a model of a cubic unit block. Hereinafter, the drawings for explanation follow this.
[0183]
In order to investigate the effect of the present invention, an experiment was performed to obtain the resistance value between the two electrodes E1 and E2 on the substrate substrate interface f as shown in FIG. As shown in FIG. 12, only the vicinity of the substrate interface f was made into a fine resistance network (a fine unit block), and the range was changed and examined. For the distance between multiple electrodes, we compared the analysis results of the device simulator under the same conditions as the analysis results of the circuit simulator using the substrate resistance network.
[0184]
FIG. 13 shows the relationship between the number of nodes of the substrate resistance network and the average error between the device simulation results. From this figure, it can be seen that the error is 1.5% or less when the number of nodes is 700 to 800 or more, and practical calculation accuracy is obtained even when only the vicinity of the substrate interface is cut into a fine resistor network. Can be confirmed.
[0185]
Although FIG. 11 illustrates that the size of the substrate model is changed with respect to the depth direction of the substrate, it can also be applied to the planar direction. In addition, as shown in FIG. In The same effect can be obtained by assigning a model that forms a finely chopped resistance network only to the near region.
[0186]
In the above example, the size of the substrate model in the vicinity of the boundary (the size of the unit block) is set to “½” of the size of the substrate model on the outside. As described above, when the ratio of the sizes of the substrate models having different sizes is determined to be “one integer” or “two integers”, the equipotential surface of the large model is obtained as shown in FIG. The connection of models with different sizes can be handled easily.
[0187]
Next, a specific example for the process of automatically erasing mask data created in the virtual layer after extracting the parasitic elements will be described.
[0188]
<Example 2-4>
The seventh feature of the LSI design support apparatus of the present invention resides in a process of automatically erasing mask data created in a virtual layer after extracting parasitic elements.
In the first embodiment, by introducing a virtual mask layer that is not involved in LSI manufacturing, it is possible to associate the portion of the element formation region and its vicinity with the substrate substrate portion, thereby making the substrate substrate parasitic. It was extracted as an element, and analysis with a circuit simulator including this was made possible.
On the other hand, the newly introduced virtual mask layer data (virtual layer data) is not necessary except for circuit analysis, and it must be removed after the LSI layout design is completed.
[0189]
Therefore, in the system of the present invention, the mask data created in this virtual layer is erased between the parasitic extraction process and the mask data saving process. The process of erasing the virtual mask layer data is performed when the element extraction / equivalent model creation means 4 in FIG. When the model creating means 4 is executed, it is possible to eliminate mistakes such as unused or erroneous mask data erasure that occur in the case of manual mask data processing, and the LSI design efficiency can be improved.
[0190]
In the present invention, by introducing a virtual mask layer, it is possible to associate the portion of the element formation region and its vicinity with the substrate substrate portion, thereby extracting the substrate substrate as a parasitic element, Analysis using the included circuit simulator is now possible.
Then, how quickly the virtual mask layer data necessary for the parasitic element extraction can be obtained in accordance with the surface structure of the semiconductor device greatly affects the efficiency of circuit analysis. Therefore, a method for efficiently obtaining virtual mask layer data will be described next.
[0191]
<Example 2-5>
The eighth feature of the LSI design support apparatus of the present invention resides in processing for automatically generating virtual layer data necessary for extraction of parasitic elements in accordance with the surface structure of the semiconductor device. In the present invention, a virtual mask layer that is not used for LSI manufacture introduces data at the same level as other layout data, so that a substrate portion can be extracted as a parasitic element and analyzed by a circuit simulator. Met.
[0192]
The LSI substrate interface includes portions such as wells having different electrical characteristics, impurity polarities and concentrations, and the size and shape are not constant even on the same substrate. As described in the above description, virtual layer data (virtual mask layer data) corresponding to each of the wells and the like must be generated in accordance with the shape. It takes a lot of time to do this manually.
[0193]
Therefore, in this embodiment, the processing is automated by creating a processing program and causing the element extraction data input creation means 11 to execute the creation of the virtual layer data so as to carry out the following procedure.
[0194]
[Virtual layer data automatic generation processing]
FIG. 16 shows the flow of processing of the virtual layer data automatic generation program.
[0195]
This program consists of initial setting step S8-1, substrate part parasitic extraction data creation step S8-2, wiring part parasitic extraction data creation step S8-3, and parasitic extraction data meaning coupling between wirings. The creation step S8-4 includes a total of four steps.
[0196]
<First Step> In the initial setting step S8-1, which is the first step, various initial setting processes are performed prior to the start of the process. Here, “designation of the area to be analyzed”, “generation of unit cell”, and the like are performed. The unit grid means vertical and horizontal lines (grids) generated at regular intervals over the entire region to be analyzed on the layout screen, that is, a grid. This lattice interval is set in advance.
The region to be analyzed is determined by a mouse operation on the layout screen, input of coordinate values, or a method of conversion from the coordinate values of the right end, left end, upper end, and lower end of the data on the layout screen.
[0197]
When determining from the data on the layout screen, not only the coordinate values at each end are used as they are, but also a margin can be provided outside the coordinates. For example, as shown in FIG. 17 (a), assuming that the elements are arranged on the screen as indicated by reference numeral 8-5, first, as shown in FIG. 17 (a). As described above, the analysis region 8-6 is set somewhat wider than the region where the layout data exists (the region surrounded by the dotted lines 8-8 and 8-10).
[0198]
Then, the unit cell is generated so that the substrate substrate exists up to the range of the analysis region 8-6. Reference numeral 8-11 in FIG. 17B represents the generated unit cell.
[0199]
By doing so, the influence of the edge of the substrate substrate can be mitigated, and a circuit simulation can be performed in a state close to the actual LSI chip conditions.
[0200]
In FIG. 17, 8-5 is layout data, 8-6 is a region to be analyzed, 8-7 is a right end of layout data 8-5, 8-8 is a left end of layout data 8-5, 8-9 Represents the upper end of the layout data 8-5, and 8-10 represents the lower end of the layout data 8-5.
[0201]
As shown in FIG. 17A, the analysis region 8-6 is set somewhat wider than the region where the layout data exists (the region surrounded by the dotted lines 8-8 and 8-10). That is, an area having a size with a predetermined margin added to an area where layout data exists is set as a target area, and the target area is drawn with a unit grid. In this specific example, the size of the margin is determined by the size of the unit cell.
[0202]
For example, the margin size is determined such that the size of the analysis region including the vertical and horizontal margins is an integral multiple of the unit cell size. Then, as shown in FIG. 17B, unit graphic data 8-12 is generated so that tiles are spread over the entire area to be analyzed in accordance with the unit grid 8-11. Furthermore, in this initial setting process, whether to extract “parasitic part of substrate”, “parasitic part of wiring”, or “parasitic of coupling between wirings” is set. Do.
[0203]
This completes the initial setting step S8-1, and then proceeds to the second step of creating parasitic part extraction data S8-1, which is the second step.
[0204]
<Second Step> The second step is a step S8-2 for creating data for extracting the parasitic part of the board portion. Here, in order to perform an analysis including the influence of the parasitic part of the board, the parasitic part of the board portion is extracted. Performs processing to generate necessary data. Mainly, processing for generating virtual layer data is performed in accordance with the structure of a shallow portion of a substrate such as a well.
[0205]
First, the layout data corresponding to the well is searched.
Next, among the figures of the respective layout data, the coordinate value of each vertex is obtained in the case of a polygon, and the diagonal coordinate value is obtained in the case of a rectangle.
Next, as shown in FIG. 18A, the coordinate values are rounded to the coordinate values of the nearest lattice points among the lattice points generated in the initial setting step S8-1. In FIG. 18, 8-13 is mask data for forming a Pwell (P well), 8-14 is mask data for forming an Nwell (N well), and 8-15 is determined by a coordinate value rounding operation. An example of a lattice point is shown.
[0206]
Next, new polygon or rectangle data having the rounded coordinate values is generated. Then, among the unit graphic data generated in the initial setting step S8-1 as shown in FIG. 18 (b), the virtual layer data corresponding to the well is included in the graphic having the rounded coordinate value. And
[0207]
In the figure, 8-15 represents Pwell virtual layer data, and 8-16 represents Nwell virtual layer data. At this time, of the portion that was originally inside the well but became outside the new figure due to the rounding operation of the coordinate value, the portion where the electrode portion provided for determining the potential of the well exists Is also assumed to be virtual layer data corresponding to the well.
[0208]
This operation is performed according to the type of well and the structure of the substrate such as a trench as necessary.
[0209]
As shown in FIG. 18B, the deep portion of the substrate is created using the virtual layer data generated here and the unit graphic generated in the initial setting step S8-1.
[0210]
At this time, these figures can be used as they are, or a larger figure can be created by combining a plurality of these figures. For example, when the deep part is further divided into a plurality of layers, the part in contact with the shallow well, etc. generates small virtual layer data, and the large virtual layer data is generated as it goes deeper, the number of nodes in the circuit network of the board part An increase in the number of elements can be suppressed. Further, even when a buried layer, an insulator layer, or the like is present, the same process is performed by increasing the number of layers.
[0211]
In FIG. 18, 8-17 represents an example of the substrate substrate data of the portion in contact with the shallow well and the like of the virtual layer data of the deep portion, and 8-18 represents an example of the substrate substrate data having a changed size.
[0212]
When the parasitic extraction data creation step S8-2 for the substrate portion is completed, the process proceeds to the third parasitic extraction data creation step S8-3 for the wiring portion.
[0213]
<Third step> In step S8-3, which is the third step for creating data for parasitic extraction of the wiring part, in order to perform analysis including the effects of wiring parasitic, data necessary for parasitic extraction of the wiring part is obtained. The generated landfill is performed.
[0214]
With respect to the extraction of the parasitic of the wiring, there are a case where only the designated wiring is targeted and a case where all the wirings within the range are targeted, but the parasitic operation can be handled by the same operation.
[0215]
Wiring is extracted by dividing it into “straight line part”, “bent part” and “end part”. Further, only the straight line portion of the wiring can be set as a parasitic extraction target by a pre-specified setting.
[0216]
As shown in FIG. 19B, the “end portion” of the wiring means a portion where the contact hole or via hole overlaps the wiring, and is not necessarily at the end of the wiring. In FIG. 19, 8-19 is mask data for forming a wiring, 8-20 is mask data for forming a contact hole or via hole, 8-21 is a linear portion of the wiring, and 8-22 is a bending of the wiring. 8-23 indicates an end portion of the wiring.
[0217]
First, each piece of wiring data on the layout screen is merged, and the wiring data composed of a plurality of rectangles is converted into polygon data in units of chunks. Next, a portion corresponding to the “end portion” (portion 8-23) is cut out from each polygon data.
[0218]
The end portion 8-23 is searched for as a portion where the wiring data overlaps with the contact hole or via hole.
[0219]
Next, a bent portion 8-22 is cut out from the remaining portion. The bent portion 8-22 is found by placing a small square on each vertex and classifying the edges of the square and the edge of the wiring data.
[0220]
The remaining portion is defined as a straight line portion 8-21 of the wiring. The straight line portion 8-21 of the wiring can be further divided into a plurality of straight wirings according to a preset designation. At this time, in the above setting, the longest value of the straight wiring is designated. Based on this longest value, a rounding operation similar to that performed in the second step (step S8-2 for creating substrate portion parasitic extraction data) is performed so that the division point comes to the unit lattice point.
[0221]
The data generated by the above operation is set as the virtual layer wiring data 8-24.
[0222]
FIG. 19B shows an example in which the virtual layer data for wiring is automatically generated in the specified straight line portion of the wiring.
[0223]
This completes the parasitic extraction data creation step S8-3 for the wiring portion, and then moves to the parasitic extraction data creation step S8-4, which means coupling between wirings, which is the fourth step.
[0224]
<Fourth Step> In step S8-4, which is a fourth step for creating data for extracting parasitics, which means coupling between wirings, in order to perform an analysis including the effect of coupling between wirings, Performs processing to generate data necessary for extraction.
[0225]
Regarding the analysis of the effects of parasitics between wirings, when targeting only specified wiring and all wiring within the range, further processing is performed for wiring parts that have a straight line part longer than the specified length. It may be.
[0226]
As for the extraction of coupling parasitics between wirings, “wirings arranged in parallel within a specified interval”, “overlapping portion between wirings in different layers”, “coupling of all wiring elements within a specified interval The target of parasitic extraction is set in advance.
[0227]
Here, the wiring element means the “straight line portion”, “bent portion”, and “end portion” described in the third step (wiring portion parasitic extraction data creation step S8-3). The third step and the process are the same up to the point where each wiring element is divided.
[0228]
Next, as shown in FIG. 20, each side of the figure of each wiring element data is extended to the designated size in the x-axis direction and the y-axis direction of the layout screen. The extension size is a preset range of “adjacent wiring considering influence”.
[0229]
If the range in which the influence of the coupling is considered is 8-25a and 8-25b, in FIG. 20, for the sake of simplicity, the side of the straight line portion of the designated wiring 8-20 is designated in the y-axis direction. An example in which the range to be considered is extended to 8-25a and 8-25b is shown.
[0230]
It is checked whether or not there is data for another wiring in the area A1 formed by the operation of extending the side. As a result, if there is data for other wiring, the area A1 that overlaps with the portion of the other wiring is cut out.
[0231]
In the example of FIG. 20, a portion 8-27a of a wiring 8-27 that is another wiring overlaps the area A1. Therefore, attention is paid to a region between the overlapping portion 8-27a and the wiring 8-25 facing the overlapping portion 8-27a, and this region is finally extracted.
[0232]
For this purpose, the overlapping portion 8-27a is cut out from the region A1, and the region between the overlapping portion 8-27a excluding the contact hole and via hole portion from the remaining region and the wiring 8-25 facing the overlapping portion 8-27a. To extract. That is, those not contacting the original wiring element are deleted and the rest is extracted. This extracted area is 8-26b.
[0233]
The region 8-26a remaining by this operation is used as virtual layer data for parasitic extraction of the interconnection coupling.
[0234]
Through the above processing, virtual layer data (virtual mask layer data) corresponding to each of the wells and the like can be automatically generated corresponding to the shape.
[0235]
Of these processes, if the parasitics related to the wiring in the third or fourth step are extracted without extracting the parasitics in the substrate in the second step, the terminal on the substrate side of the wiring-to-substrate capacitance is All are connected to ground.
[0236]
According to the present invention described above, a high-function LSI can be designed efficiently.
[0237]
As described above, the invention according to the first embodiment is a model of a format in which a parasitic can be analyzed by a circuit simulator in a semiconductor device design support apparatus that enables various analyzes including parasitic effects depending on a layout pattern while performing layout design. The purpose is to generate the data required for extraction so that efficient and highly accurate analysis can be performed. In the mask layer that is not used for semiconductor manufacturing introduced for the purpose of parasitic element extraction Data refer to the size of the transistor formed on the substrate, or to the characteristic size of the structure necessary to realize an integrated circuit, or near the substrate interface, near the boundary of the well, This is a mechanism that determines the size of the area near the boundary of the region where the polarity and concentration of impurities are different, and the area near the electrode so that it is smaller than other parts. Is obtained by such comprises, furthermore, is obtained as a function of erasing the data for said parasitic extraction before the mask data storing process executed after the processing of element extraction.
[0238]
Then, according to such a semiconductor device design support apparatus, parasitic elements are extracted from the layout data as equivalent models so that the effects of noise that wraps around the substrate and the effects of crosstalk between wirings can be analyzed by circuit simulation. In addition, the equivalent model can be converted into an equivalent model with an appropriate size that can maintain the analysis accuracy, and the analysis simulation of the LSI under design can be performed. Therefore, a highly functional LSI can be designed efficiently. It will be like that.
[0239]
In addition, this invention is not limited to the Example mentioned above, In the range which does not change a summary, it can deform | transform suitably and can be implemented.
[0240]
【The invention's effect】
As described above, according to the present invention, parasitic elements can be extracted as equivalent models from layout data so that they can be analyzed by circuit simulation, and additional circuits necessary for executing circuit simulation can be generated on the layout screen. Since various analysis methods can be set while designing the layout, it is possible to feed back useful information to the designer, and for this reason, a high-performance LSI can be designed efficiently.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the present invention, and is a functional configuration diagram of a semiconductor device design support apparatus showing an embodiment of the present invention.
FIG. 2 is a diagram for explaining the present invention, showing an example in which an external circuit is added to an LSI under layout design and circuit simulation is performed by the semiconductor device design support apparatus of the present invention.
FIG. 3 is a diagram for explaining the present invention and showing an example of a substrate model as an example of a figure drawn in a virtual layer handled in the semiconductor device design support apparatus of the present invention;
FIG. 4 is a flowchart for explaining the present invention, and is a flowchart showing an example of a processing flow in the semiconductor device design support apparatus of the present invention.
FIG. 5 is a diagram for explaining the present invention, showing an example of a substrate model in which a shallow part and a deep part handled in the semiconductor device design support apparatus of the present invention have a layer structure.
FIG. 6 is a diagram showing an example of pattern replacement with an equivalent element model in the semiconductor device design support apparatus of the present invention, and a diagram showing an example in which a wiring portion is extracted with a plurality of L-type lumped constant models.
FIG. 7 is a diagram for explaining the present invention and shows an example in which a circuit simulation is performed by adding an equivalent noise source to an LSI under layout design by the semiconductor device design support apparatus of the present invention.
FIG. 8 is a diagram for explaining the present invention, and an example in which a circuit simulation is performed by adding an equivalent noise source having a region to an LSI under layout design by the semiconductor device design support apparatus of the present invention; FIG.
FIG. 9 is a diagram for explaining the present invention and showing an example of a typical model of a transistor used for analysis in the system of the present invention.
FIG. 10 is a diagram for explaining the present invention, and is a diagram showing a substrate model in accordance with the size of a transistor as an example of a model used in the system of the present invention.
FIG. 11 is a diagram for explaining the present invention, and shows an example in which the vicinity of a boundary surface of a substrate is a small substrate model as an example of a model used in the system of the present invention.
FIG. 12 is a diagram for explaining the present invention and showing a configuration example of a model used in an experiment for examining the effect of the system of the present invention.
13 is a diagram for explaining the present invention, and showing experimental results in the model of FIG. 12 performed for explaining the effect of the system of the present invention.
FIG. 14 is a diagram for explaining the present invention, showing an example in which a portion close to a plane from an electrode is used as a small substrate model as an example of the system of the present invention;
FIG. 15 is a diagram for explaining the present invention, and is a diagram for explaining models of different sizes used in the system of the present invention and connections between the models;
FIG. 16 is a diagram for explaining the present invention, and showing a flow of a program for automatic generation of virtual layer data as an example used in the system of the present invention;
FIG. 17 is a diagram for explaining the present invention, and is a diagram showing a region to be analyzed, a unit grid, and a unit graphic as an example used in the system of the present invention;
FIG. 18 is a diagram for explaining the present invention, and showing an example of automatically generated virtual layer data as an example used in the system of the present invention.
FIG. 19 is a diagram for explaining the present invention, and shows an example in which wiring virtual layer data is automatically generated in a straight line portion of wiring as an example used in the system of the present invention;
FIG. 20 is a diagram for explaining the present invention, and showing an example in which inter-wiring coupling virtual layer data is automatically generated in a straight line portion of wiring as an example used in the system of the present invention;
[Explanation of symbols]
1 ... Layout information input means
2 ... Louisout information storage means
3. Display means
4 ... Element extraction / equivalent model creation means
5 ... Model creation condition input means
6 ... Input data creation means of the calculation means
7. Calculation condition input means
8 ... Calculation means
9. Output means
10 ... Additional circuit input means
11 ... Element extraction data input creation means
12 ... Device extraction data storage means

Claims (17)

Input means for inputting layout information as information constituting the semiconductor integrated circuit, parameter values including physical constants and manufacturing conditions, and calculation conditions as information;
Semiconductor substrate interface, in the vicinity of the boundary or electrodes of the well has an area which is divided into unit blocks of small size compared to other regions, is divided into unit blocks is independent of the virtual layer to the semiconductor integrated circuit manufacturing When the mask layer is set in a desired region on the circuit element of the semiconductor integrated circuit input by the input means or the wiring pattern as the circuit element, the parasitic element in the mask layer set using the unit block And a data input creation means for element extraction that creates information necessary for obtaining the equivalent model,
Display means for displaying the input information, the set mask layer and analysis results;
Each circuit element and wiring are extracted from the layout information and parameter values input by the input means to create an equivalent model. When the mask layer is set, information from the element extraction data input creation means is used. An equivalent model creating means for creating an equivalent model of the mask layer part;
Data format conversion means for converting the equivalent model obtained by the equivalent model creation means into a data format that can be numerically analyzed;
Calculation means for numerically analyzing the extracted equivalent model based on the data converted by the data format conversion means and the calculation conditions input from the input means;
Output means for outputting the calculation result of the calculation means to the display means;
A semiconductor device design support apparatus, comprising:   The semiconductor substrate for forming the semiconductor integrated circuit is divided into a portion close to the interface and a portion deep from the interface, and the boundary is based on the depth of the well on the semiconductor substrate, and the mask layer is placed on each of them. The semiconductor device design support apparatus according to claim 1.   3. The semiconductor device design support apparatus according to claim 2, wherein the mask layer has at least a two-layer structure.   2. The semiconductor device design support apparatus according to claim 1, wherein the layer structure of the mask layer is increased by one layer each time the buried layer is increased.   A circuit that does not exist on the semiconductor substrate to be designed but is indispensable for operation, at any position on the display screen of the display means for displaying information on the shape and arrangement of each circuit element including elements and wiring. 2. The semiconductor device design support apparatus according to claim 1, further comprising an adding means for adding, and adding a function for creating an equivalent model for information from the adding means to the equivalent model creating means.   6. The semiconductor according to claim 5, wherein the circuit added by said adding means is not present on the semiconductor substrate to be designed, but is an indispensable power source for operation, an activation signal source, and a driving element for a load circuit. Device design support device.   The input means is arbitrarily given a control signal of the signal source added by the adding means, or as an output value of a designated terminal of the semiconductor integrated circuit displayed on the screen of the display means to be displayed An instruction function for giving is added, and a function for creating and giving data that can be obtained by the calculation means to the calculation means for the situation corresponding to the instruction is added to the input data creation means. Item 2. A semiconductor device design support apparatus according to Item 1.   8. The signal source added by the adding means is displayed with a certain area on a display screen of a display means for displaying information on the shape and arrangement of circuit elements of the elements and wiring. The semiconductor device design support apparatus described.   The display means displays the information input by the input means and the analysis result of the calculation means as layout information, and the position and shape on the layout corresponding to the circuit element and the model indicated in the calculation result, 2. The semiconductor device design support apparatus according to claim 1, further comprising output means for processing and outputting the display data so as to be displayed in a state distinguishable from the layout.   When the calculation result by the calculation means satisfies a preset condition, an output means for extracting the element, element arrangement, or wiring related to the parameter and processing and outputting the display data so as to be displayed in a discriminable state The semiconductor device design support apparatus according to claim 1, further comprising:   A first storage unit configured to store information input by the input unit; and a second storage unit configured to store information such as manufacturing conditions and physical property constants necessary for the extraction. The creating unit includes the second storage unit. By processing the storage information of the first storage unit using the storage information of the storage unit, the circuit element of the linear element, the nonlinear element, and the wiring is extracted, and an equivalent model is created. The semiconductor device design support apparatus according to claim 1.   Judgment means for judging whether the information of the extracted equivalent model is input data necessary for analysis by the arithmetic means for numerical analysis, and the information of the extracted equivalent model is incomplete as the input data 2. The semiconductor device according to claim 1, further comprising means for complementing the information described at a circuit element level inputted in advance and storing it as input data of the arithmetic means for numerical analysis. Design support device.   Means for comparing layout information with information previously described at the circuit element level, and the input data converting means included in the information described at the circuit element level but not included in the layout information Means for supplementing with the information described at the circuit element level, displaying on the means for displaying the layout information using the symbol, and storing as input data of the means for extracting the equivalent model The semiconductor device design support apparatus according to claim 1, further comprising:   2. The semiconductor device design support apparatus according to claim 1, wherein the extracted equivalent model has a plurality of different levels of accuracy.   15. The semiconductor device design according to claim 14, wherein the plurality of equivalent models having different accuracy levels are changed by using frequency characteristics or transient responses of the circuit analyzed by the arithmetic means. Support device.   The equivalent model creating means creates a structure of the semiconductor substrate as an equivalent model using a sub model prepared in accordance with a structure on or under the semiconductor substrate interface. Item 2. A semiconductor device design support apparatus according to Item 1.   2. The semiconductor device design support apparatus according to claim 1, further comprising means for storing an output signal of the arithmetic means for numerical analysis at a designated terminal, wherein the output signal is used as an input signal for circuit analysis. .

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