KR100253309B1 - Mounting method of vertical package - Google Patents

Mounting method of vertical package Download PDF

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Publication number
KR100253309B1
KR100253309B1 KR1019970039667A KR19970039667A KR100253309B1 KR 100253309 B1 KR100253309 B1 KR 100253309B1 KR 1019970039667 A KR1019970039667 A KR 1019970039667A KR 19970039667 A KR19970039667 A KR 19970039667A KR 100253309 B1 KR100253309 B1 KR 100253309B1
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KR
South Korea
Prior art keywords
package
packages
pcb
leads
mounting
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Application number
KR1019970039667A
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Korean (ko)
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KR19990016937A (en
Inventor
김상하
Original Assignee
김영환
현대반도체주식회사
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Priority to KR1019970039667A priority Critical patent/KR100253309B1/en
Publication of KR19990016937A publication Critical patent/KR19990016937A/en
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Publication of KR100253309B1 publication Critical patent/KR100253309B1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A method for mounting a vertical-type package on a circuit board is provided to prevent the package from falling down before or during a solder reflow process. CONSTITUTION: The vertical-type package(P') has outer leads(11c) and outermost supportable leads(11d), all of which are protruded from a mold body and bent in a certain direction. The package(P') further has a perforated hole formed at a portion of the mold body. In the method, the several packages(P') are placed upright on the circuit board(40) and aligned with each other, after solder paste is applied on lands of the circuit board(40) for receiving the outer leads(11c) and supportable leads(11d). Next, a fastening rod(41) is inserted into the perforated holes of the packages(P') to prevent the falling down of the packages(P'). After that, a planned solder reflow process is performed to harden the solder paste and thereby to fix the packages(P').

Description

직립형 패키지의 실장방법{MOUNTING METHOD OF VERTICAL PACKAGE}How to mount upright package {MOUNTING METHOD OF VERTICAL PACKAGE}

본 발명은 직립형 패키지의 실장방법에 관한 것으로, 특히 실장시 패키지의 쓰러짐으로 인하여 불량이 발생되는 것을 방지하도록 하는데 적합한 직립형 패키지의 실장방법에 관한 것이다.The present invention relates to a method for mounting an upright package, and more particularly, to a method for mounting an upright package suitable for preventing a defect from occurring due to the package falling down during mounting.

일반적으로 피시비의 상면에 실장면적을 적게 차지하는 직립형 패키지의 일종으로 SVP(SURFACE VERTICAL PACKAGE)가 소개되고 있는 바, 도 1을 참고하여 간단히 설명하면 다음과 같다.In general, SVP (SURFACE VERTICAL PACKAGE) is introduced as a type of upright package that occupies a small mounting area on the upper surface of the PCB, and is briefly described with reference to FIG. 1.

도 1은 종래 직립형 패키지의 구조를 보인 사시도이고, 도 2는 도 1의 A-A'를 절취하여 보인 단면도로서, 도시된 바와 같이, 종래 직립형 패키지는 리드프레임(1)의 패들(1a) 상면에 반도체 칩(2)이 부착되어 있고, 그 칩(2)의 상면에 형성되어 있는 칩패드(2a)들과 칩(2)의 주변에 형성되어 있는 다수개의 인너리드(1b)들은 각각 금속와이어(3)로 연결되어 있으며, 상기 칩(2), 패들(1a), 인너리드(1b)의 일정부분을 감싸도록 에폭시로 몸체부(4)가 형성되어 있고, 상기 인너리드(1b)에 각각 연결됨과 아울러 몸체부(4)의 일측으로 돌출되도록 아웃리드(1c)가 절곡형성되어 있으며, 상기 아웃리드(1c)들 중 양측 외곽에는 전기적으로 연결되지 않고 아웃리드(1c)들 보다 크게 동일형태로 절곡되어 있는 지지리드(1d)가 형성되어 있다.1 is a perspective view illustrating a structure of a conventional upright package, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1. As illustrated, the conventional upright package is a top surface of a paddle 1a of the lead frame 1. The semiconductor chip 2 is attached to the chip pad, and the chip pads 2a formed on the upper surface of the chip 2 and the plurality of inner leads 1b formed around the chip 2 are each metal wire. It is connected to (3), the body portion (4) is formed of epoxy so as to surround a portion of the chip (2), paddle (1a), the inner lead (1b), respectively on the inner lead (1b) The outer lead 1c is bent so as to protrude to one side of the body portion 4, and the outer lead 1c is not electrically connected to both outer sides of the outer lead 1c, and is larger than the outer lead 1c. The support lead 1d bent by is formed.

상기와 같이 구성되어 있는 종래 직립형 패키지(P)는 도 3에 도시된 바와 같이, 피시비(5)의 상면에 형성되어 있는 다수개의 랜드(미도시)에 솔더 페이스트를 바른 상태에서 패키지(P)의 아웃리드(1c)들이 얹혀지도록 얼라인 함과 동시에 지지리드(1d)를 이용하여 수직으로 세우는 방법으로 수개의 패키지(P)를 나열하여 위치시킨 다음, 일정온도로 가열된 노의 내부를 통과시켜서 솔더페이스트를 매개로 랜드에 각각 아웃리드(1c)들을 부착함으로서 실장을 완료하게 된다.As shown in FIG. 3, the conventional upright package P configured as described above has a solder paste applied to a plurality of lands (not shown) formed on the upper surface of the PCB 5 in a state where the package P is applied. Arrange several packages (P) by arranging them so that the outleads (1c) are placed on them and standing them vertically using the support leads (1d), and then let them pass through the inside of the furnace heated to a certain temperature. The mounting is completed by attaching the outleads 1c to the lands through the solder paste.

그러나, 상기와 같은 종래 직립형 패키지(P)는 얼라인한 상태에서 리플로우공정으로 이동중이나 또는 노 안에서 리플로우공정을 실시하는 중에 쓰러진 상태로 리플로우가 진행되어 피시비(5)의 전체 불량을 발생시키는 문제점이 있었다.However, the conventional upright package P as described above is reflowed in a collapsed state while moving to a reflow process in an aligned state or during a reflow process in a furnace, thereby causing a total defect of the PCB 5. There was a problem.

상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 패키지가 쓰러져서 리플로우시 불량이 발생되는 것을 방지하도록 하는데 적합한 직립형 패키지의 실장방법을 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention devised in view of the above problems is to provide a method of mounting an upright package suitable for preventing a package from falling and causing a defect in reflow.

도 1은 종래 직립형 패키지의 구조를 보인 사시도.1 is a perspective view showing the structure of a conventional upright package.

도 2는 도 1의 A-A'를 절취하여 보인 단면도.2 is a cross-sectional view taken along the line AA ′ of FIG. 1;

도 3는 종래 직립형 패키지가 실장된 상태를 보인 사시도.Figure 3 is a perspective view showing a state in which the conventional upright package is mounted.

도 4은 본 발명 직립형 패키지의 구조를 보인 사시도.Figure 4 is a perspective view showing the structure of the present invention upright package.

도 5는 도 4의 B-B'를 절취하여 보인 단면도.5 is a cross-sectional view taken along line BB ′ of FIG. 4.

도 6는 본 발명 직립형 패키지의 제조방법을 설명하기 위한 단면도.Figure 6 is a cross-sectional view for explaining a method of manufacturing the present invention upright package.

도 7는 본 발명 직립형 패키지의 실장방법을 설명하기 위한 사시도.Figure 7 is a perspective view for explaining a method for mounting the upright package of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

11c: 아웃리드 15 : 몸체부11c: Outlead 15: Body

20 : 지지공 40 : 피시비20: support ball 40: PCB

41 : 지지봉 P' : 피시비41: support rod P ': PCB

상기와 같은 본 발명의 목적을 달성하기 위하여 피시비의 상면에 수개의 패키지를 얼라인하여 나열설치하는 정렬공정을 수행하는 단계와, 상기 나열된 패키지에 형성된 지지공에 삽입되도록 지지봉을 설치하는 패키지 지지공정을 수행하는 단계와, 상기와 같이 지지봉이 설치된 패키지들이 얹혀있는 피시비를 노에 통과시켜서 패키지를 피시비의 상면에 고정하는 리플로우공정을 수행하는 단계의 순서로 진행하는 것을 특징으로 하는 직립형 패키지의 실장방법이 제공된다.In order to achieve the object of the present invention as described above, performing the alignment process of arranging and arranging several packages on the upper surface of the PCB, and the package support process for installing the support rods to be inserted into the support holes formed in the listed packages And performing a reflow step of fixing the package to the top of the PCB by passing the PCB on which the supporting rods are installed, as described above. This is provided.

이하, 상기와 같은 본 발명 직립형 패키지의 실장방법을 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the embodiment of the accompanying drawings, the mounting method of the present invention upright package as described above in more detail as follows.

도 4은 본 발명 직립형 패키지의 구조를 보인 사시도이고, 도 5는 도 4의 B-B'를 절취하여 보인 단면도로서, 도시된 바와 같이, 본 발명 직립형 패키지는 리드프레임(11)의 패들(11a) 상면에 접착제(12)로 반도체 칩(13)이 고정부착되어 있고, 그 칩(13)의 상면에 형성된 다수개의 칩패드(13a)들과 리드프레임(11)의 인너리드(11b)들은 각각 금속와이어(14)로 연결되어 있으며, 상기 칩(13), 금속와이어(14), 인너리드(11b)의 일정부분을 감싸도록 에폭시로 몸체부(15)가 형성되어 있다.4 is a perspective view showing the structure of the upright package of the present invention, and FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. 4. As illustrated, the upright package of the present invention is a paddle 11a of a lead frame 11. The semiconductor chip 13 is fixedly attached to the upper surface with the adhesive 12, and the plurality of chip pads 13a and the inner leads 11b of the lead frame 11 formed on the upper surface of the chip 13 are respectively attached. Is connected to the metal wire 14, the body portion 15 is formed of epoxy to surround a portion of the chip 13, the metal wire 14, the inner lead (11b).

그리고, 상기 인너리드(11b)들에 각각 연결됨과 아울러 몸체부(15)의 외측으로 돌출되어 상방향으로 아웃리드(11c)가 절곡형성되어 있고, 그 아웃리드(11c)들의 양측에는 전기적으로 연결되지 않은 지지리드(11d)가 상기 인너리드(11b)들과 동일방향으로 절곡형성되어 있다.In addition, the inner leads 11b are connected to the inner leads 11b and protrude outwardly of the body portion 15 so that the outleads 11c are bent upwards, and both ends of the outer leads 11c are electrically connected to each other. 11d of unsupported bends are bent in the same direction as the inner leads 11b.

또한, 상기 몸체부(15)의 일측 상단부에는 일정크기의 지지공(20)이 관통형성되어 있어서, 리플로우시 지지봉(미도시)으로 지지할 수 있도록 되어 있다.In addition, the support hole 20 of a predetermined size is formed through the upper end of one side of the body portion 15, so that it can be supported by a support rod (not shown) during reflow.

상기와 같은 패키지(P')를 제조하기 위한 제조방법은 종래와 유사하다. 다만, 도 6에 도시된 바와 같이, 상,하부몰딩금형(30)(31)의 내면에 캐비티(32)의 내측방향으로 상,하부돌기(33)(34)를 설치하여 그 상,하부돌기(33)(34)를 제외한 부분이 몰딩되도록 함으로서, 몰딩후 상,하부돌기(33)(34)에 의하여 지지공(20)이 형성된다.The manufacturing method for manufacturing such a package (P ') is similar to the prior art. 6, the upper and lower protrusions 33 and 34 are installed on the inner surfaces of the upper and lower molding molds 30 and 31 in the inward direction of the cavity 32, and the upper and lower protrusions thereof. The parts except for (33) and (34) are molded so that the support holes 20 are formed by the upper and lower protrusions 33 and 34 after molding.

상기와 같이 제조된 패키지(P')를 피시비의 상면에 실장하기 위한 실장방법을 도 7을 참조하여 설명하면 다음과 같다.A mounting method for mounting the package P ′ prepared as described above on the upper surface of the PCB will be described with reference to FIG. 7.

먼저, 피시비(40)의 상면에 형성된 랜드(미도시)의 상면에 솔더페이스트가 도포된상태에서 패키지(P')의 아웃리드(11c)들이 랜드(미도시)의 상면에 접촉됨과 아울러 지지리드(11d)에 의해 직립으로 세워지도록 얼라인하는 방법으로 실장하고자 하는 수개의 패키지(P')를 나열설치한다.First, the outleads 11c of the package P 'come into contact with the upper surface of the land (not shown) while the solder paste is applied to the upper surface of the land (not shown) formed on the upper surface of the PCB 40. List and install several packages (P ') to be mounted by aligning them to stand upright by (11d).

그런 다음, 도 7에 도시된 바와 같이, 나열설치된 패키지(P')들의 지지공(20)에 삽입되도록 지지봉(41)을 설치한다.Then, as shown in Figure 7, the support rod 41 is installed so as to be inserted into the support hole 20 of the package (P ') arranged.

그런 다음, 지지봉(41)이 끼워진 패키지(P')들이 설치된 피시비(40)를 리플로우 노(미도시)로 이동하여 일정온도로 가열된 노의 내부를 통과시켜서 솔더페이스트가 융착되어 피시비(40)의 랜드(미도시)와 패키지(P')의 아웃리드(11c)들을 부착시킴으로서 실장을 완료하게 된다.Then, the PCB 40 having the supporting rods 41 installed therein is moved to a reflow furnace (not shown) to pass through the inside of the furnace heated to a predetermined temperature so that the solder paste is fused to the PCB 40. Mounting is completed by attaching the lands (not shown) of FIG. 7) and the outleads 11c of the package P ′.

이상에서 상세히 설명한 바와 같이, 본 발명 직립형 패키지의 실장방법은 몰딩시 패키지의 몸체부에 지지공을 형성하고, 패키지의 실장시 나열설치된 패키지의 지지공에 지지봉을 삽입한 상태에서 이동 및 리플로우를 실시하여, 공정이동시 지지봉에 의하여 패키지들이 지지되도록 함으로써, 종래와 같이 패키지가 쓰러진 상태로 리플로우하여 불량을 발생시키는 것을 방지하는 효과가 있다.As described in detail above, the mounting method of the upright package of the present invention forms a support hole in the body portion of the package during molding, and moves and reflows while the support rod is inserted into the support hole of the package installed when the package is mounted. By carrying out, the packages are supported by the support rod during the process movement, thereby preventing the defects from reflowing in the collapsed state as in the prior art.

또한, 몰딩작업과 동시에 지지공을 형성함으로써 별도의 지지공형성작업을 생략할 수 있는 효과가 있다.In addition, by forming a support hole at the same time as the molding operation there is an effect that can be omitted a separate support hole forming operation.

Claims (1)

몰딩작업시 몸체부에 지지공이 형성된 수개의 패키지를 피시비의 상면에 얼라인하여 나열설치하는 정렬공정을 수행하는 단계와, 상기 나열된 패키지에 형성된 지지공에 삽입되도록 지지봉을 설치하는 패키지 지지공정을 수행하는 단계와, 상기와 같이 지지봉이 설치된 패키지들이 얹혀있는 피시비를 노에 통과시켜서 패키지를 피시비의 상면에 고정하는 리플로우공정을 수행하는 단계의 순서로 진행하는 것을 특징으로 하는 직립형 패키지의 실장방법.Performing a process of aligning and arranging several packages in which the support holes are formed in the body part on the upper surface of the PCB during molding, and performing a package support process of installing the support rods so as to be inserted into the support holes formed in the listed packages. And passing the PCB on which the supporting rods are installed as described above to the furnace to perform a reflow step of fixing the package to the upper surface of the PCB.
KR1019970039667A 1997-08-20 1997-08-20 Mounting method of vertical package KR100253309B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279586A (en) * 1995-04-07 1996-10-22 Fujitsu Ltd Semiconductor device and unit of the device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279586A (en) * 1995-04-07 1996-10-22 Fujitsu Ltd Semiconductor device and unit of the device

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