KR100206977B1 - Vertical type ball grid array - Google Patents
Vertical type ball grid array Download PDFInfo
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- KR100206977B1 KR100206977B1 KR1019960067254A KR19960067254A KR100206977B1 KR 100206977 B1 KR100206977 B1 KR 100206977B1 KR 1019960067254 A KR1019960067254 A KR 1019960067254A KR 19960067254 A KR19960067254 A KR 19960067254A KR 100206977 B1 KR100206977 B1 KR 100206977B1
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- ball grid
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 직립형 볼 그리드 어레이 패키지에 관한 것으로, 종래 볼 그리드 어레이 패키지는 실장시 수평방향으로 실장하게 되어 실장효율을 향상시키는데 한계가 있는 문제점이 있었다. 본 발명 직립형 볼 그리드 어레이 패키지는 서브스트레이트(11)에 내설되는 패턴 리드(14)를 서브스트레이트(11)의 상면과 일측면에 노출되도록 내설하고, 그 일측면에 노출되는 패턴 리드(14)에 연결되도록 다수개의 솔더볼(17)을 부착하여 구성함으로서, 패키지(P)의 실장시 피시비(20)의 상면에 수직으로 세워서 실장하게 되어 면적을 적게 차지하게 되고, 따라서 실장효율이 향상되는 효과가 있다.The present invention relates to an upright ball grid array package, and the conventional ball grid array package has a problem in that it is mounted in a horizontal direction when it is mounted, thereby improving mounting efficiency. The upright ball grid array package according to the present invention has a pattern lead 14 embedded in the substrate 11 exposed to the upper surface and one side of the substrate 11, and exposed to the pattern lead 14 exposed to one side thereof. By attaching a plurality of solder balls 17 to be connected to each other, when mounting the package (P) is mounted vertically on the upper surface of the PCB 20 to occupy a small area, and thus the mounting efficiency is improved. .
Description
본 발명은 직립형 볼 그리드 어레이 패키지(VERTICAL TYPE BALL GRID ARRAY PACKAGE)에 관한 것으로, 특히 실장효율을 향상시키도록 하는데 적합한 직립형 볼 그리드 어레이 패키지에 관한 것이다.The present invention relates to a vertical ball grid array package (VERTICAL TYPE BALL GRID ARRAY PACKAGE), and more particularly to a vertical ball grid array package suitable for improving the mounting efficiency.
제1도는 종래 볼 그리드 어레이 패키지의 구조를 보인 종단면도로서, 도시된 바와 같이, 종래 볼 그리드 어레이 패키지는 서브스트레이트(SUBSTRATE)(1)의 상면 중앙에 접착제(2)로 반도체 칩(CHIP)(3)이 고정부착되어 있고, 상기 서브스트레이트(1)의 내측에는 다수개의 패턴 리드(PATTERN LEAD)(4)가 상,하방향으로 내설되어 서브스트레이트(1)의 상,하면에 노출되도록 설치되어 있으며, 상기 칩(3)의 상면에 형성된 다수개의 칩패드(CHIP PAD)(3a)와 상기 서브스트레이트(1)의 상면에 노출된 패턴 리드(4)의 상단부가 각각 금속와이어(5)로 연결되어 있고, 상기 칩(3), 금속와이어(5)를 감싸도록 서브스트레이트(1)의 상면에 에폭시(EPOXY)로 몰딩부(6)가 형성되어 있으며, 상기 패턴리드(4)의 하단부에 연결되도록 서브스트레이트(1)의 하면에 다수개의 솔더볼(SOLDER BALL)(7)이 부착되어 있다.FIG. 1 is a longitudinal cross-sectional view showing a structure of a conventional ball grid array package. As shown in the drawing, a conventional ball grid array package is formed of a semiconductor chip (CHIP) with an adhesive 2 in the center of an upper surface of a substrate 1. 3) is fixedly attached, and inside the substrate 1, a plurality of PATTERN LEADs 4 are installed in the up and down directions to expose the upper and lower surfaces of the substrate 1, respectively. And a plurality of chip pads 3a formed on the upper surface of the chip 3 and upper ends of the pattern leads 4 exposed on the upper surface of the substrate 1 are connected to the metal wires 5, respectively. The molding part 6 is formed on the upper surface of the substrate 1 by epoxy to surround the chip 3 and the metal wire 5, and is connected to the lower end of the pattern lead 4. A plurality of solder balls 7 are attached to the lower surface of the substrate 1 so that It is.
상기와 같이 구성되어 있는 종래 볼 그리드 어레이 패키지는 서브스트레이트(1)의 상면에 접착제(2)를 이용하여 반도체 칩(3)을 고정부착하는 다이본딩공정을 실시하고, 상기 칩(3)의 상면에 형성되어 있는 다수개의 칩패드(3a)와 상기 서브스트레이트(1)에 내설되어 있는 패턴 리드(4)의 상단부를 각각 금속와이어(5)로 연결하는 와이어본딩공정을 실시하며, 상기 칩(3), 금속와이어(5)를 감싸도록 서브스트레이트(1)의 상면에 에폭시로 몰딩하는 몰딩공정을 실시하고, 상기 서브스트레이트(1)의 하면에 다수개의 솔더볼(7)을 부착하는 볼본딩공정을 실시하여 패키지(P)를 완성한다,The conventional ball grid array package configured as described above is subjected to a die bonding step of fixing and attaching the semiconductor chip 3 using the adhesive 2 to the upper surface of the substrate 1, and the upper surface of the chip 3 A wire bonding process is performed to connect a plurality of chip pads 3a formed on the upper end portions of the pattern leads 4 embedded in the substrate 1 with metal wires 5, respectively. ), A molding process of molding with epoxy on the upper surface of the substrate 1 to surround the metal wire 5, and a ball bonding process for attaching a plurality of solder balls 7 to the lower surface of the substrate 1. To complete the package P,
이와 같이 완성된 패키지(P)는 제2도에 도시된 바와 같이 피시비(8)의 상면에 솔더볼(7)을 얼라인한 다음, 리플로우공정을 실시하여 피시비(8)의 상면에 솔더볼(7)이 부분융착되도록 하므로서 패키지(P)의 실장을 완료한다.As shown in FIG. 2, the completed package P is aligned with the solder balls 7 on the upper surface of the PCB 8, and then subjected to a reflow process to the solder balls 7 on the upper surface of the PCB 8. The mounting of the package P is completed by allowing this to be partially fused.
그러나, 상기와 같이 구성되어 있는 종래 볼 그리드 어레이 패키지는 실장시 실장 면적을 많이 차지하여 최근의 추세인 전자제품의 소형화에 역행하는 문제점이 있었다.However, the conventional ball grid array package configured as described above occupies a large amount of mounting area when mounted, and thus has a problem of countering the recent trend toward miniaturization of electronic products.
상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 실장면적을 적게 차지하도록 하여 실장효율을 향상시키도록 하는데 적합한 직립형 볼 그리드 어레이 패키지를 제공함에 있다.The object of the present invention devised in view of the above problems is to provide an upright ball grid array package suitable for improving the mounting efficiency by taking up a small mounting area.
제1도는 종래 볼 그리드 어레이 패키지의 구조를 보인 종단면도.Figure 1 is a longitudinal sectional view showing the structure of a conventional ball grid array package.
제2도는 종래 볼 그리드 어레이 패키지가 실장된 상태를 보인 정면도.2 is a front view showing a state in which a conventional ball grid array package is mounted.
제3도는 본 발명 직립형 볼 그리드 어레이 패키지의 구조를 보인 종단면도.Figure 3 is a longitudinal sectional view showing the structure of the present invention upright ball grid array package.
제4도는 본 발명 직립형 볼 그리드 어레이 패키지가 실장된 상태를 보인 정면도.Figure 4 is a front view showing a state in which the present invention upright ball grid array package is mounted.
제5도는 제3도의 변형예를 보인 종단면도.5 is a longitudinal sectional view showing a modification of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 서브스트레이트 12 : 접착제11: substrate 12: adhesive
13 : 칩 13a : 칩패드13 chip 13a chip pad
14 : 패턴 리드 15 : 금속와이어14 pattern lead 15 metal wire
16 : 몰딩부 17 : 솔더볼16 molding part 17 solder ball
상기와 같은 본 발명의 목적을 달성하기 위하여 다층회로기판인 서브스트레이트와, 그 서브스트레이트의 상면에 접착제로 고정부착되는 반도체 칩과, 상기 서브스트레이트의 상면과 일측면의 외부로 노출되도록 내설되는 다수개의 패턴 리드와, 상기 칩의 상면에 형성되는 다수개의 칩패드와 서브스트레이트의 상면에 노출된 패턴 리드를 각각 전기적으로 연결하는 금속와이어와, 상기 칩, 금속와이어를 감싸도록 서브스트레이트의 상면에 에폭시로 몰딩된 몰딩부와, 상기 서브스트레이트의 일측면에 부착되며 상기 패턴 리드의 하단부에 연결부착되는 다수개의 솔더볼을 구비하여서 구성된 것을 특징으로 하는 직립형 볼 그리드 어레이 패키지가 제공된다.In order to achieve the object of the present invention as described above, a substrate, which is a multilayer circuit board, a semiconductor chip fixedly attached to an upper surface of the substrate, and a plurality of substrates which are exposed to the outside of the upper surface and one side of the substrate. A plurality of pattern leads, a plurality of chip pads formed on the upper surface of the chip, and a metal wire electrically connecting the pattern leads exposed on the upper surface of the substrate, and an epoxy on the upper surface of the substrate to surround the chip and the metal wire. And a plurality of solder balls attached to one side of the substrate and connected to and attached to the lower end of the pattern lead.
이하, 상기와 같이 구성되는 본 발명 직립형 볼 그리드 어레이 패키지를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the upright ball grid array package of the present invention configured as described above will be described in detail with reference to embodiments of the accompanying drawings.
제3도는 본 발명 직립형 볼 그리드 어레이 패키지의 구조를 보인 종단면도로서, 도시된 바와 같이, 본 발명 직립형 볼 그리드 어레이 패키지는 다층레이어로 형성된 서브스트레이트(11)의 상면에 접착제(12)로 반도체 칩(13)이 고정부착되고, 상기 서브스트레이트(11)의 상면과 일측면의 외부로 노출되도록 다수개의 패턴 리드(14)가 내설되며, 상기 칩(13)의 상면에 형성되는 다수개의 칩패드(13a)와 서브스트레이트(11)의 상면에 노출된 패턴 리드(14)가 각각 금속와이어(15)로 전기적인 연결이되고, 상기 칩(13), 금속와이어(15)를 감싸도록 서브스트레이트(11)의 상면에 에폭시로 몰딩하여 몰딩부(16)가 형성되며, 상기 패턴 리드(14)의 하단부에 연결되도록 서브스트레이트(11)의 일측면에 다수개의 솔더볼(17)이 부착고정된다.3 is a longitudinal cross-sectional view showing the structure of the upright ball grid array package according to the present invention. A plurality of chip pads (13) are fixed and attached, and a plurality of pattern leads 14 are formed so as to be exposed to the outside of the upper surface and one side of the substrate 11 and formed on the upper surface of the chip 13 ( 13a) and the pattern lead 14 exposed on the upper surface of the substrate 11 are electrically connected to the metal wires 15, respectively, and the substrate 11 to surround the chip 13 and the metal wires 15. Molding part 16 is formed by molding with epoxy on the upper surface of the), and a plurality of solder balls 17 are fixed to one side of the substrate 11 to be connected to the lower end of the pattern lead 14.
이와 같이 구성되는 본 발명 직립형 볼 그리드 어레이 패키지의 제조방법은 다음과 같다.The manufacturing method of the upright ball grid array package of the present invention configured as described above is as follows.
서브스트레이트(11)의 상면 중앙에 접착제(12)를 이용하여 반도체 칩(13)을 고정부착하는 다이본딩공정을 수행하는 단계와, 상기 칩(13)의 상면에 형성되어 있는 다수개의 칩패드(13a)와 서브스트레이트(11)의 상면에 노출된 패턴 리드(14)를 각각 금속와이어(15)로 연결하는 와이어본딩공정을 수행하는 단계와, 상기 칩(13), 금속 와이어(15)를 감싸도록 서브스트레이트(11)의 상면에 에폭시로 몰딩부(16)를 형성하는 몰딩공정을 수행하는 단계와, 상기 서브스트레이트(11)의 일측면에 노출된 패턴 리드(14)의 하단부에 솔더볼(17)을 부착고정하는 볼본딩공정을 수행하는 단계의 순서로 제조된다.Performing a die bonding process of fixing and attaching the semiconductor chip 13 to the center of the upper surface of the substrate 11 by using an adhesive 12, and a plurality of chip pads formed on the upper surface of the chip 13. Performing a wire bonding process of connecting the pattern leads 14 exposed on the upper surface of the substrate 11 and the substrate 11 with the metal wires 15, and wrapping the chip 13 and the metal wires 15, respectively. Performing a molding process of forming the molding part 16 with epoxy on the upper surface of the substrate 11, and solder balls 17 at the lower end of the pattern lead 14 exposed on one side of the substrate 11. ) Is manufactured in the order of performing the ball bonding process of fixing.
상기와 같이 제조되는 본 발명의 패키지(P)는 제4도에 도시된 바와 같이, 피시비(20)의 상면에 패키지(P)를 수직으로 세워서 서브스트레이트(11)의 일측면에 부착되어 있는 다수개의 솔더볼(17)을 얼라인한 다음, 리플로우하여 솔더볼(17)을 부분융착시킴으로서 실장하게 된다.As shown in FIG. 4, the package P of the present invention manufactured as described above has a plurality of packages attached to one side of the substrate 11 by standing the package P vertically on the upper surface of the PCB 20. The two solder balls 17 are aligned and then reflowed to mount the solder balls 17 partially.
제5도는 제3도의 변형예를 보인 종단면도로서, 도시된 바와 같이, 서브스트레이트(21)의 양측면에 접착제(22)를 이용하여 반도체 칩(23)을 부착하고, 상기 서브스트레이트(21)의 상면과 일측면으로 패턴 리드(24)가 노출되도록 형성하며, 상기 칩(23)의 상면에 형성되어 있는 다수개의 칩패드(23a)와 서브스트레이트(21)의 상면에 노출된 패턴 리드(24)를 금속와이어(25)로 각각 연결하고, 상기 칩(23), 금속와이어(25)를 감싸도록 서브스트레이트(21)의 양측면에 에폭시로 몰딩부(26)을 형성하며, 상기 패턴 리드(24)의 하단부에 연결되도록 서브스트레이트(21)의 일측면에 솔더볼(27)을 부착하여 적층형의 직립형 볼 그리드 어레이 패키지가 구성된다.FIG. 5 is a longitudinal cross-sectional view showing a modification of FIG. 3. As illustrated, the semiconductor chip 23 is attached to both sides of the substrate 21 by using an adhesive 22, and the substrate 21 of FIG. The pattern lead 24 is formed to be exposed to an upper surface and one side thereof, and the plurality of chip pads 23a and the pattern lead 24 exposed on the upper surface of the substrate 21 are formed on the upper surface of the chip 23. To each of the metal wires (25), forming molding parts (26) with epoxy on both sides of the substrate (21) to surround the chip (23) and the metal wires (25), and the pattern leads (24). The solder ball 27 is attached to one side of the substrate 21 to be connected to the lower end of the stacked upright ball grid array package.
이상에서 상세히 설명한 바와 같이 본 발명 직립형 볼 그리드 어레이 패키지는 서브스트레이트에 내설되는 패턴 리드를 서브스트레이트의 상면과 일측면에 노출되도록 내설하고, 그 일측면에 노출되는 패턴 리드에 연결되도록 다수개의 솔더볼을 부착하여 구성함으로서, 패키지의 실장시 피시비의 상면에 수직으로 세워서 실장하게 되어 면적을 적게 차지하게 되고, 따라서 실장효율이 향상되는 효과가 있다.As described in detail above, the upright ball grid array package of the present invention has a plurality of solder balls so as to be connected to the pattern leads exposed on one side of the substrate lead and the pattern leads in the substrate exposed on one side of the substrate. By attaching and configuring, the package is mounted vertically on the upper surface of the PCB so that the package occupies a small area, thereby improving the mounting efficiency.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960067254A KR100206977B1 (en) | 1996-12-18 | 1996-12-18 | Vertical type ball grid array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960067254A KR100206977B1 (en) | 1996-12-18 | 1996-12-18 | Vertical type ball grid array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980048633A KR19980048633A (en) | 1998-09-15 |
| KR100206977B1 true KR100206977B1 (en) | 1999-07-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960067254A KR100206977B1 (en) | 1996-12-18 | 1996-12-18 | Vertical type ball grid array |
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| Country | Link |
|---|---|
| KR (1) | KR100206977B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101111427B1 (en) | 2010-02-23 | 2012-02-15 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package for horizontal and vertical adhesion, and method for manufacturing the same |
-
1996
- 1996-12-18 KR KR1019960067254A patent/KR100206977B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101111427B1 (en) | 2010-02-23 | 2012-02-15 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package for horizontal and vertical adhesion, and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980048633A (en) | 1998-09-15 |
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