KR100239706B1 - Bottom lead package - Google Patents
Bottom lead package Download PDFInfo
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- KR100239706B1 KR100239706B1 KR1019960052279A KR19960052279A KR100239706B1 KR 100239706 B1 KR100239706 B1 KR 100239706B1 KR 1019960052279 A KR1019960052279 A KR 1019960052279A KR 19960052279 A KR19960052279 A KR 19960052279A KR 100239706 B1 KR100239706 B1 KR 100239706B1
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- Prior art keywords
- lead
- package
- circuit board
- printed circuit
- leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 버틈 리드 패키지에 관한 것으로, 종래에는 패키지를 실장시 리드를 인쇄회로기판의 패턴리드에 직접 연결하는 구조로서 패키지의 하면과 인쇄회로기판의 상면이 밀착되어 있어서 공기의 순환이 원활치 못하고, 따라서 리드가 스트레스를 받게되어 패턴리드에서 리드가 떨어지는 문제점이 있었다. 본 발명 버틈 리드 패키지는 다수개의 리드 하면에 수 개의 삽입홈을 각각 형성하고, 그 삽입홈에 접속부재를 각각 삽입 고정하여 인쇄회로기판의 상면에 실장시 접속부재에 의하여 패키지와 인쇄회로기판 사이에 일정공간부가 형성되도록 함으로서, 그 공간부로 공기의 순환이 원활하게 이루어지게 되어 리드가 과열에 따른 스트레스로 패턴리드에서 떨어지는 것을 방지하는 효과가 있고, 상기 접속부재를 돌출형성시킴으로서 인쇄회로 기판의 상면에 실장시 얼라인이 용이한 효과가 있다.The present invention relates to a gap lead package, and in the related art, a structure in which a lead is directly connected to a pattern lead of a printed circuit board when the package is mounted, and the bottom surface of the package and the upper surface of the printed circuit board are closely attached to each other so that air circulation is not smooth. Therefore, the lead is stressed, there was a problem that the lead falls from the pattern lead. According to the present invention, the lid lead package forms a plurality of insertion grooves on the lower surfaces of the plurality of leads, and inserts and fixes the connection members to the insertion grooves, respectively, between the package and the printed circuit board by the connection members when mounted on the upper surface of the printed circuit board. By forming a predetermined space portion, the circulation of air to the space portion is made smoothly, there is an effect of preventing the lead from falling off the pattern lead due to the stress due to overheating, and by forming the protruding member to the upper surface of the printed circuit board It is easy to align when mounting.
Description
본 발명은 버틈 리드 패키지(BLP : BOTTOM LEAD PACKAGE)에 관한 것으로, 특히 패키지의 실장시 패키지의 하면과 인쇄회로기판(PCB) 사이에 공기의 순환을 원활하게 할 수 있는 일정공간부가 형성되도록 하여 패키지의 과열을 방지하도록 하는데 적합한 버틈 리드 패키지에 관한 것이다.The present invention relates to a bump lead package (BLP), and in particular, when a package is mounted, a predetermined space portion is formed to smoothly circulate air between the bottom surface of the package and the printed circuit board (PCB). A lid lead package suitable for preventing overheating.
일반적으로 실장면적을 적게 차지하고, 몰딩부의 외측으로 리드를 돌출형성하지 않음으로서 외부의 충격으로 부터 리드의 휨을 방지하기 위한 패키지로 버틈 리드 패키지가 사용되며, 이와 같은 버틈 리드 패키지를 제조하는 방법을 도1을 참조하여 설명하면 다음과 같다.In general, a lid lead package is used as a package to occupy a small mounting area and prevent protrusion of the lead from external impact by not protruding the lead to the outside of the molding part, and a method of manufacturing such a lid lead package is illustrated. Referring to 1, it is as follows.
도1은 종래 버틈 리드 패키지의 구조를 보인 종단면도로서, 도시된 바와 같이, 종래 버틈 리드 패키지는 반도체 칩(CHIP)(1)의 하면 양측에 다수개의 리드(LEAD)(2)가 접착제(3)로 고정부착되어 있고, 그 칩(CHIP)(1)의 칩패드(CHIP PAD)(1a)와 다수개의 리드(2)는 각각 금속와이어(4)로 전기적인 연결이 이루어져 있으며, 상기 다수개의 리드(2) 하면을 외부로 노출시킴과 아울러 상기 칩(1), 금속와이어(4), 리드(2)의 일정부분을 감싸도록 에폭시(EPOXY)로 몰딩(MOLDING)한 몰딩부(5)가 형성되어 있다.1 is a longitudinal cross-sectional view showing a structure of a conventional gap lead package. As shown in FIG. 1, in the conventional gap lead package, a plurality of leads 2 are formed on both sides of a lower surface of a semiconductor chip 1. And a plurality of leads 2 of the chip pad 1a of the chip 1 are electrically connected to the metal wires 4, respectively. Exposed to the outside of the lid (2) and the molding portion (5) molded with epoxy (EPOXY) to surround a portion of the chip (1), the metal wire (4), the lid (2) Formed.
이와 같이 구성되는 종래 버틈 리드 패키지를 제조하는 방법은 다수개의 리드(2) 상면에 반도체 칩(1)을 부착고정하는 다이본딩을 실시하고, 상기 리드(2)와 칩(1)에 형성된 칩패드(1a)를 금속와이어(4)로 연결하는 와이어본딩을 실시하며, 리드(2)의 하면을 외부로 노출시킴과 아울러 상기 칩(1), 금속와이어(4), 리드(2)의 일정부분을 감싸도록 에폭시로 몰딩하여 몰딩부(5)를 형성하는 몰딩공정을 실시하여 완성한다. 그런다음, 상기와 같이 제작된 패키지를 도2와 같이 인쇄회로기판(6)의 상면에 설치하게 되는데, 이때 인쇄회로기판(6)의 상면에 형성된 다수개의 패턴리드(PATTERN LEAD)(6a) 상면과 패키지의 리드(2) 하면이 각각 부착하게 된다.In the conventional method of manufacturing a gap lid package configured as described above, die bonding for attaching and fixing the semiconductor chip 1 to the upper surface of the plurality of leads 2 is performed, and chip pads formed on the leads 2 and the chip 1 are provided. Wire bonding connecting (1a) to the metal wires (4), exposing the lower surface of the lead (2) to the outside, and a predetermined portion of the chip (1), the metal wire (4), the lead (2) It is completed by performing a molding process to form a molding portion 5 by molding with epoxy so as to surround. Then, the package manufactured as described above is installed on the upper surface of the printed circuit board 6 as shown in FIG. 2, wherein a plurality of pattern leads 6A formed on the upper surface of the printed circuit board 6 are provided. And the lower surface of the lid 2 are attached to each other.
그러나, 상기와 같은 종래 버틈 리드 패키지는 상기 패키지의 리드(2)를 패턴리드(6a)에 직접 연결하는 구조로서 패키지의 하면과 인쇄회로기판(6)의 상면이 밀착되어 있어서 공기의 순환이 원활치 못하고, 따라서 패키지 가동시 리드(2)로 전달되는 열을 충분히 식히지 못하고 리드(2)에 스트레스를 받게되어 패턴리드(6a)에서 리드(2)가 떨어지는 문제점이 있었다. 또한 리드(2)들이 패키지의 하면에 노출되도록 동일면에 형성되어 있어서 인쇄회로기판(6)의 패턴리드(6a)에 얼라인이 용히치 못한 문제점이 있었다.However, the conventional gap lead package as described above has a structure in which the lead 2 of the package is directly connected to the pattern lead 6a, and the bottom surface of the package and the top surface of the printed circuit board 6 are in close contact with each other, so that air circulation is smooth. Therefore, there is a problem that the lead 2 is dropped from the pattern lead 6a because the lead 2 is not sufficiently cooled while the heat transferred to the lead 2 is not cooled sufficiently during package operation. In addition, since the leads 2 are formed on the same surface so as to be exposed to the bottom surface of the package, there is a problem in that the alignment of the pattern leads 6a of the printed circuit board 6 does not melt.
본 발명의 주목적은 상기와 같은 여러 문제점을 갖지 않는 버틈 리드 패키지를 제공함에 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a lid lead package that does not have various problems as described above.
본 발명의 다른 목적은 패키지의 하면과 인쇄회로기판의 상면 사이에 일정공간이 확보되도록 하여 공기의 순환이 원활하게 이루어짐으로서 리드가 스트레스를 받지 않도록 하는데 적합한 버틈 리드 패키지를 제공함에 있다.Another object of the present invention is to provide a gap lead package suitable for preventing a lead from being stressed by smoothly circulating air by ensuring a predetermined space between the bottom surface of the package and the top surface of the printed circuit board.
본 발명의 또다른 목적은 패키지를 인쇄회로기판에 실장시 얼라인이 용이하도록 하는데 적합한 버틈 리드 패키지를 제공함에 있다.It is still another object of the present invention to provide a gap lead package suitable for aligning a package when mounting the package on a printed circuit board.
본 발명의 또다른 목적은 패키지에 설치되는 외부단자의 접착력을 향상시켜서 신뢰성을 향상시키도록 하는데 적합한 버틈 리드 패키지를 제공함에 있다.It is still another object of the present invention to provide a lid lead package suitable for improving reliability by improving adhesion of external terminals installed in a package.
본 발명의 또다른 목적은 패키지에 설치되는 외부단자의 접착력을 향상시켜서 신뢰성을 향상시키도록 하는데 접합한 버틈리드 패키지를 제공함에 있다.It is another object of the present invention to provide a buried lid package bonded to improve the adhesive force of the external terminal installed in the package to improve the reliability.
도1은 종래 기술에 의한 버틈 리드 패키지의 구성을 보인 종단면도.1 is a longitudinal cross-sectional view showing the configuration of a gap lead package according to the prior art;
도2은 종래 버틈 리드 패키지가 인쇄회로기판에 실장된 상태를 보인 종단면도Figure 2 is a longitudinal sectional view showing a state where the conventional lead lid package is mounted on a printed circuit board
도3은 본 발명 버틈 리드 패키지의 제1실시예를 보인 종단면도.Figure 3 is a longitudinal sectional view showing a first embodiment of the present invention lid lead package.
도4a, 4b,4c는 본 발명 버틈 리드 패키지의 제조방법을 설명하기 위하여 리드부분을 부분적으로 보인 종단면도.Figures 4a, 4b, 4c is a longitudinal cross-sectional view partially showing the lead portion to explain the manufacturing method of the present invention lid lead package.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 칩 13 : 리드11: chip 13: lead
13a : 삽입홈 14 : 금속와이어13a: insertion groove 14: metal wire
15 : 몰딩부 16 : 솔더볼15: molding 16: solder ball
20 : 메탈 팁20: metal tip
상기와 같은 본 발명의 목적을 달성하기 위하여 다수개의 리드 상면에 칩이 부착되어 있고, 그 칩과 리드는 각각 금속와이어로 연결되어 있으며, 상기 다수개의 리드하면을 외부로 노출시킴과 아울러 상기 칩, 금속와이어, 리드의 일정부분을 감싸도록 에폭시로 몰딩부가 형성되어 있는 버틈 리드 패키지에 있어서, 상기 다수개의 리드 하면에 각각 수개의 삽입홈을 형성하고, 그 삽입홈의 내면에 부착되도록 접속부재를 삽입설치한 것을 특징으로 하는 버틈 리드 패키지가 제공된다.In order to achieve the object of the present invention as described above, a chip is attached to the upper surface of the plurality of leads, and the chip and the lead are connected to the metal wire, respectively. In a gap lead package in which a molding portion is formed of epoxy to surround a portion of a metal wire and a lead, a plurality of insertion grooves are formed on the bottom surfaces of the plurality of leads, and a connection member is inserted to be attached to an inner surface of the insertion groove. A lid lead package is provided, which is installed.
이하, 상기와 같이 구성되는 본 발명 버틈 리드 패키지를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the embodiment of the accompanying drawings, the present invention lid lead package configured as described above in more detail as follows.
도3은 본 발명 버틈 리드 패키지의 제1실시예를 보인 종단면도이고, 도4는 본 발명 버틈 리드 패키지의 제조방법을 설명하기 위하여 리드부분을 부분적으로 보인 종단면도이다.Figure 3 is a longitudinal cross-sectional view showing a first embodiment of the present invention the lid lead package, Figure 4 is a longitudinal cross-sectional view partially showing the lead portion to explain the manufacturing method of the present invention the lid lead package.
도시된 바와 같이, 본 발명 버틈 리드 패키지는 반도체 칩(11)과, 그 칩(11)의 하면 양측에 접착제(12)로 부착되는 다수개의 리드(13)와, 상기 반도체 칩(11)의 칩패드(11a)와 다수개의 리드(13)를 각각 전기적으로 연결하는 금속와이어(14)와, 상기 다수개의 리드(13) 하면을 외부로 노출시킴과 아울러 상기 칩(11), 금속와이어(14), 리드(13)의 일정부분을 감싸도록 에폭시로 몰딩한 몰딩부(15)로 구성된다.As shown, the present lid lead package includes a semiconductor chip 11, a plurality of leads 13 attached to both sides of the chip 11 with an adhesive 12, and a chip of the semiconductor chip 11; The metal wire 14 electrically connecting the pad 11a and the plurality of leads 13 to each other, and the lower surface of the plurality of leads 13 are exposed to the outside, and the chip 11 and the metal wire 14 are exposed to the outside. And, it is composed of a molding portion 15 molded with epoxy so as to surround a portion of the lead (13).
그리고, 상기 다수개의 리드(13) 하면에는 각각 수개의 삽입홈(13a)이 형성되고, 그 삽입홈(13a)에 각각 솔더볼(SOLDER BALL)(16)을 삽입고정하여 구성된다.A plurality of insertion grooves 13a are formed on the lower surfaces of the leads 13, respectively, and the solder balls 16 are inserted into and fixed to the insertion grooves 13a.
상기와 같이 구성되는 본 발명 버틈 리드 패키지는 먼저, 리드(13)의 제조시 프레싱(PRESSING) 등의 방법으로 리드(13)의 하면에 수개의 삽입홈(13a)을 형성한다.In the present invention, the lid lead package configured as described above, first, a plurality of insertion grooves 13a are formed in the lower surface of the lid 13 by a method such as pressing during the manufacture of the lid 13.
이와 같이 제작된 다수개의 리드(13)의 하면에 도4a와 같이 테이프(17)를 부착한다. 이와 같이 테이프(17)가 부착된 다수개의 리드(13) 상면에 접착제(12)를 이용하여 칩(11)을 고정부착하고, 그 칩(11)의 칩패드(11a)와 리드(13)를 금속와이어(14)로 각각 연결하며, 상기 테이프(17)가 외부로 노출되도록 상기 칩(11), 금속와이어(14), 리드(13)의 일정부분을 에폭시로 몰딩하여 몰딩부(15)를 형성하는 몰딩공정을 실시한다. 그런다음, 도4b와 같이 다수개의 리드(13) 하면에 부착되어 있는 테이프(17)을 떼어내고, 그 다수개의 리드(13) 하면에 각각 형성되어 있는 삽입홈(13a)에 도 4c와 같이 솔더볼(16)을 삽입고정하는 솔더부볼착공정을 실시하여 패키지를 완성한다.The tape 17 is attached to the lower surface of the plurality of leads 13 thus manufactured as shown in FIG. 4A. In this way, the chip 11 is fixedly attached to the upper surface of the plurality of leads 13 to which the tape 17 is attached using the adhesive 12, and the chip pads 11a and the leads 13 of the chip 11 are attached. Each of the metal wires 14 is connected to each other, and a portion of the chip 11, the metal wires 14, and the lead 13 is molded with epoxy so that the tape 17 is exposed to the outside. A molding process is performed. Then, the tape 17 attached to the lower surface of the plurality of leads 13 is removed as shown in FIG. 4B, and the solder balls are inserted into the insertion grooves 13a formed on the lower surfaces of the plurality of leads 13 as shown in FIG. 4C. A solder part attachment process for inserting (16) is performed to complete the package.
상기와 같이 제작된 패키지는 인쇄회로기판에 실장시 솔더볼에 의하여 패키지의 하면과 인쇄회로기판의 상면 사이에 공간부가 형성되고, 그 공간부에 공기의 유통이 원활하여 패키지 작동시 고열이 발생하여도 리드가 떨어지는 것을 방지하게 되는 효과가 있다. 그리고, 솔더볼이 외부로 돌출되어 있어서, 인쇄회로기판의 상면에 형성된 패턴리드에 얼라인하는 것이 용이한 효과가 있다.The package manufactured as described above has a space formed between the lower surface of the package and the upper surface of the printed circuit board by solder balls when mounted on the printed circuit board, and even though high temperature is generated during operation of the package due to the smooth flow of air in the space. There is an effect of preventing the lead from falling. In addition, since the solder ball protrudes to the outside, it is easy to align the pattern lead formed on the upper surface of the printed circuit board.
도5는 도3의 변형예를 보인 종단면도로서, 도시된 바와 같이, 리드(13)의 하면에 형성된 수개의 삽입홈(13a)에 각각 메탈 팁(METAL TIP)(20)을 삽입고정할 수도 있다.FIG. 5 is a longitudinal cross-sectional view showing a modified example of FIG. 3, and as shown in FIG. 5, metal tips 20 may be inserted into and fixed to several insertion grooves 13a formed on the bottom surface of the lid 13. have.
이상에서 상세히 설명한 바와 같이 본 발명 버틈 리드 패키지는 다수개의 리드 하면에 수개의 삽입홈을 각각 형성하고, 그 삽입홈에 접속부재를 각각 삽입고정하여 인쇄회로기판의 상면에 실장시 접속부재에 의하여 패키지와 인쇄회로기판 사이에 일정공간부가 형성되도록 함으로서, 그 공간부로 공기의 순환이 원활하게 이루어지게 되어 리드가 과열에 따른 스트레스로 패턴리드에서 떨어지는 것을 방지하는 효과가 있고, 상기 접속부재를 돌출형성시킴으로서 인쇄회로기판의 상면에 실장시 얼라인이 용이한 효과가 있다.As described in detail above, in the present invention, the lid lead package may include a plurality of insertion grooves formed on the lower surfaces of the plurality of leads, and the connection members may be inserted into and fixed to the insertion grooves, respectively, to be packaged by the connection members when mounted on the upper surface of the printed circuit board. By forming a predetermined space portion between the and the printed circuit board, the circulation of air to the space portion is made smoothly, there is an effect of preventing the lead from falling from the pattern lead due to the stress due to overheating, and by forming the connection member protruding It is easy to align when mounting on the upper surface of the printed circuit board.
또한, 접속부재가 리드에 형성된 삽입홈에 삽입된 상태로 삽입홈의 내면 전체에 접착됨에 따라 접착강도가 강하여 신뢰성이 향상되고, 전기적인 신호전달이 정확히 이루어질 수 있으며, 접속부재의 부착시 접속부재를 지지하기 위한 별도의 부품이 필요없게 되는 효과가 있다.In addition, as the connection member is attached to the entire inner surface of the insertion groove in the state of being inserted into the insertion groove formed in the lead, the adhesion strength is strong, reliability is improved, and electrical signal transmission can be made accurately, and when the connection member is attached to the connection member There is an effect that does not need a separate part to support the.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960052279A KR100239706B1 (en) | 1996-11-06 | 1996-11-06 | Bottom lead package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960052279A KR100239706B1 (en) | 1996-11-06 | 1996-11-06 | Bottom lead package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980034276A KR19980034276A (en) | 1998-08-05 |
| KR100239706B1 true KR100239706B1 (en) | 2000-01-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960052279A KR100239706B1 (en) | 1996-11-06 | 1996-11-06 | Bottom lead package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100239706B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402835B1 (en) * | 1999-11-18 | 2003-10-22 | 동부전자 주식회사 | Structure of chip scale package and method for fabricating it |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08139225A (en) * | 1994-11-11 | 1996-05-31 | Hitachi Chem Co Ltd | Semiconductor package and its manufacture |
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1996
- 1996-11-06 KR KR1019960052279A patent/KR100239706B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08139225A (en) * | 1994-11-11 | 1996-05-31 | Hitachi Chem Co Ltd | Semiconductor package and its manufacture |
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| KR19980034276A (en) | 1998-08-05 |
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