KR100253284B1 - Cell structure of semiconductor memory - Google Patents

Abstract

PURPOSE: A cell structure is provided to improve the reading data speed by increasing the amount of charge to be stored at a cell and reducing the number of reproducing operation. CONSTITUTION: The cell structure is composed of the first and second NMOS transistors(NM1,NM2) and the first and second capacitors(C1,C2). The first NMOS transistor and capacitor are in series connected between bit lines and receive a signal of the first word line via the gate of the first NMOS transistor. The second NMOS transistor and capacitor are in series connected between bit lines and receive a signal of the second word line via the gate of the second NMOS transistor.

Description

Cell structure of semiconductor memory.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell structure of a semiconductor memory, and more particularly, to a cell structure of a semiconductor memory in which the amount of charge stored in a cell is increased so as to reduce the time for which the amount of charge is leaked.

Hereinafter, a cell structure of a conventional semiconductor memory will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a structure of one cell of a conventional semiconductor memory. As shown in FIG. 1, a signal of a first word line WL1 is applied to a gate, and is formed between a bit line BL and a DC voltage Vcp. The NMOS transistor NM1 and the first capacitor C1 and the signal of the second word line WL2 are connected to the gate in series and connected in series between the bitbar line BLBAR and the DC voltage Vcp. The NMOS transistor NM2 and the second capacitor C2 are connected to each other, and a sense amplifier 10 is connected between the bit line BL and the bit bar line BLBAR. The cells configured as described above are arranged to form the cell structure of the semiconductor memory.

Hereinafter, the operation of the conventional cell structure will be described with reference to FIGS. 1 and 2 by dividing into writing and reading operations.

FIG. 2 is a waveform diagram of a voltage applied to a word, a bit, and a bit bar line in a cell structure of a conventional semiconductor memory. As shown in the drawing, first, a signal Vcc is applied to a bit line BL in a write operation. The signal 0 is applied to the bit bar line BLBAR to be amplified by the sense amplifier 10, and the high potential signal of the first word line WL1 is applied to the gate through the turned-on MOS transistor NM1. The signal amplified by the sense amplifier 10 is charged in the first capacitor C1.

로 인가한다.Subsequently, the low potential signal of the first word line WL1 is applied to the gate to turn off the NMOS transistor NM1, and then the signals of the bit line BL and the bit bar line BLBAR are respectively applied.

Is applied.

Accordingly, the voltage of the first node N1 is the maximum output Vcc of the sense amplifier 10 when the write data is at high potential, and the minimum output of the sense amplifier 10 when the write data is at low potential. A waveform of a signal applied to the first word line WL1, the bit line BL, and the bit bar line BLBAR is (0), as shown in FIG. 2.

In the read operation, when a high potential is applied to the gate of the NMOS transistor NM1 through the first word line WL1 to turn on the NMOS transistor NM1, the write operation may be performed on the bit line BL. The voltage Vcc is applied when the write data is high potential to the first node N1, and the voltage 0 is applied when the write data is low potential.

Thereafter, a low potential is applied to the gates of the NMOS transistors NM1 and NM2 through the first and second word lines WL1 and WL2 to turn the NMOS transistors NM2 and NM2. After turning off, the sense amplifier 10 is operated to amplify and output a voltage applied to the bit line BL and the bit bar line BLBAR.

However, in the cell structure of a conventional semiconductor memory constructed and operated as described above, when high potential data is stored in a write operation, the data is damaged due to leakage. In order to prevent this, there is a problem in that a replay operation must be frequently performed. there was.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a cell structure that can increase the amount of data stored in the cell.

Another object of the present invention is to provide a cell structure in which data can be easily read by increasing the amount of data output in a read operation.

Another object of the present invention is to provide a cell structure which can reduce the number of reproducing operations by increasing the amount of data stored in a cell.

1 is a diagram showing the structure of one cell of a conventional semiconductor memory.

FIG. 2 is a waveform diagram of voltages applied to words, bits, and bit bar lines in FIG.

3 is a diagram showing the structure of one cell of the semiconductor memory according to the present invention;

4A and 4B are waveform diagrams of a voltage applied to a word, a bit, a bit bar line, and a charge charged to a cell in a write operation in Fig. 3;

5A and 5B are waveform diagrams of word lines and bit lines applied to cells in a read operation and charges charged to cells in Fig. 3;

* Explanation of symbols for the main parts of the drawings

10: sense amplifiers C1, C2: first and second capacitors

WL1, WL2: first and second word lines BL: bit lines

BLBAR: Bit Barline

As described above, in a cell structure of a semiconductor memory, a first NMOS transistor and a first capacitor connected to a bit line and a bit bar line in series with a signal of a first word line are applied to a gate; It is achieved by applying a signal of a word line to a gate and comprising a second NMOS transistor and a second capacitor connected in series between the bit bar line and the bit line, and attaching the cell structure of the semiconductor memory according to the present invention. When described in detail with reference to the drawings as follows.

3 is a diagram illustrating a structure of one cell of a semiconductor memory according to an embodiment of the present invention. As shown therein, a signal of a first word line WL1 is applied to a gate, and a bit line BL and a bit bar line are shown. Signals of the NMOS transistor NM1 and the first capacitor C1 and the second word line WL2 connected in series between the BLBARs are applied to the gates, and the bit bar lines BLBAR and bit lines BL are applied. The NMOS transistor NM2 and the second capacitor C2 are connected in series, and a sense amplifier 10 is connected to the bit line BL and the bit bar line BLBAR.

The cells thus constructed are arranged to form the cell structure of the memory. Hereinafter, the operation of the cell structure configured as described above will be described with reference to FIGS. 3, 4, and 5 and limited to write and read operations when a signal is applied from the first word line WL1.

로 인가한다.4A and 4B are waveform diagrams of words, bits, bit bar lines and cell charges when high potential data or low potential data is applied during a write operation in the cell structure of the semiconductor memory according to the present invention. 5b is a waveform diagram of a word line, a bit line, and a cell charge according to the high potential data or the low potential data in a read operation. As shown in the drawing, first, a signal Vcc is applied to the bit line BL in a write operation. When the signal 0 is applied to the bit bar line BLBAR, the signal is amplified by the sense amplifier 10, and the high MOS signal of the first word line WL1 is applied to the gate to turn on the turned on NMOS transistor NM1. The signal amplified by the sense amplifier 10 is charged in the first capacitor (C1) through. Subsequently, the low potential signal of the first word line WL1 is applied to a gate to turn off the NMOS transistor NM1, and then the signals of the bit line BL and the bit bar line BLBAR are respectively applied.

Is applied.

가 되고, 상기 쓰기데이터가 저전위일 경우는

가 된다.Therefore, when the write data is high potential, the voltage of the first node N1 is Vcc +

If the write data is low potential

Becomes

In the read operation, the high potential is applied to the gate of the NMOS transistor NM1 through the first word line WL1 to turn on the NMOS transistor NM1, and then operate the sense amplifier 10 to operate the bit. Voltages applied to the line BL and the bit bar line BLBAR are amplified and output.

Hereinafter, each waveform in the read operation will be described in more detail.

에 소정의 전압(

)이 더해진

이 인가되고, 비트바라인(BLBAR)은

가 유지되며, 이때 제1노드(N1)에 충전된 전압(SN1)은 Vcc +

에서

가 되고, 상기 쓰기데이터가 저전위일 경우는 비트라인(BL)에

가 인가되고, 비트바라인(BLBAR)은

가 유지되며, 이때 제1노드(N1)에 충전된 신호(SN1)는

에서

가 된다.When the high potential is applied to the gate of the NMOS transistor NM1 through the first word line WL1 to turn on the NMOS transistor NM1, when the write data has the high potential in the write operation, the bit line BL is turned on. silver

At a given voltage (

) Added

Is applied, the bit bar line (BLBAR)

Is maintained, wherein the voltage SN1 charged in the first node N1 is Vcc +

in

If the write data is at low potential, the bit line BL

Is applied, the bit bar line (BLBAR) is

Is maintained, and the signal SN1 charged in the first node N1 is

in

Becomes

를 유지하고, 쓰기데이터가 저전위일 경우는 비트라인(BL)의 전압이 0이 되고, 비트바라인(BLBAR)의 전압이 Vcc가 되며, 상기 제1노드(N1)에 충전된 신호(SN1)는

를 유지한다.Subsequently, a low potential is applied to the gate of the NMOS transistor NM1 through the first word line WL1 to turn off the NMOS transistor NM1, and then to drive the sense amplifier 10. When SAEN is set to Vcc to drive the sense amplifier 10, when the write data is at high potential, the voltage of the bit line BL becomes Vcc, and the voltage of the bit bar line BLBAR becomes 0. The signal SN1 charged in the first node N1 is

If the write data is at low potential, the voltage of the bit line BL becomes 0, the voltage of the bit bar line BLBAR becomes Vcc, and the signal SN1 charged in the first node N1. )

Keep it.

As described above, the cell structure of the semiconductor memory according to the present invention increases the charge amount charged in the cell, thereby making the read operation easier and reducing the number of reproducing operations, thereby increasing the speed of the write and read operations. It can be effective.

Claims (1)

A signal of the first word line is applied to the gate, a first NMOS transistor and a first capacitor connected in series between the bit line and the bit bar line, and a signal of the second word line is applied to the gate, A cell structure of a semiconductor memory, comprising a second NMOS transistor and a second capacitor connected in series between bit lines.

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