KR100249186B1 - Method for manufacturing semiconductor cell - Google Patents
Method for manufacturing semiconductor cell Download PDFInfo
- Publication number
- KR100249186B1 KR100249186B1 KR1019920010035A KR920010035A KR100249186B1 KR 100249186 B1 KR100249186 B1 KR 100249186B1 KR 1019920010035 A KR1019920010035 A KR 1019920010035A KR 920010035 A KR920010035 A KR 920010035A KR 100249186 B1 KR100249186 B1 KR 100249186B1
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- South Korea
- Prior art keywords
- film
- interlayer
- photoresist film
- photosensitive film
- semiconductor cell
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 하층감광막을 직선으로 제거할 수 있는 반도체 셀 제조 방법에 관한 것으로, 종래에는 하층감광막의 단차가 크므로 활 모양으로 제거되었으나 본 발명에서는 제2층간막(5)을 하층감광막(2)의 제거 공정중에 형성하여 수직 형태로 하층감광막(2)을 정의할 수 있게 하므로서 상기 결점을 개선시킬 수 있다.The present invention relates to a method for manufacturing a semiconductor cell capable of removing the lower photoresist film in a straight line. In the related art, the step of the lower photoresist film is largely removed in a bow shape. However, in the present invention, the second interlayer film 5 is replaced by the lower photoresist film 2. This defect can be improved by forming during the removal process so that the lower photosensitive film 2 can be defined in a vertical form.
Description
제1도는 종래의 반도체 셀 제조 방법을 설명하기 위한 공정 단면도.1 is a cross-sectional view for explaining a conventional semiconductor cell manufacturing method.
제2도는 본 발명의 반도체 셀 제조 방법을 설명하기 위한 공정 단면도.2 is a cross-sectional view for explaining the method for manufacturing a semiconductor cell of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 하층감광막1: Substrate 2: Lower photosensitive film
3 : 제1층간막 4 : 상층감광막3: first interlayer film 4: upper photosensitive film
5 : 제2층간막5: second layer interlayer
본 발명은 MLR(Multilayer resist)공정을 이용한 반도체 셀에 관한 것으로, 특히 하층감광막(Bottom photoresist)을 직선으로 제거할 수 있는 반도체 셀 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor cell using a multilayer resist (MLR) process, and more particularly to a method for manufacturing a semiconductor cell capable of removing a bottom photoresist in a straight line.
일반적인 반도체 메모리 셀 제조에서 이용하는 MLR 공정이란 하층감광막을 2.0㎛정도의 두께만큼 코팅한후 베이크(bake)하고 층간막을 코팅하고, 상층감광막(Top photoresist)를 패터닝(patterning)하는 것을 의미한다.The MLR process used in general semiconductor memory cell manufacturing means coating a lower photoresist film with a thickness of about 2.0 μm, baking, coating an interlayer film, and patterning a top photoresist.
종래의 반도체 셀 제조는 제1a도와 같이 기판(1)위에 하층감광막(2), 제1층간막(3)을 차례로 형성하고, 제1층간막(3)위에 상층감광막(4)을 패터닝한후 제1b와 같이 상층감광막(4)을 마스크로하여 제1층간막(3)을 선택적으로 제거한다.In the conventional semiconductor cell manufacturing, as shown in FIG. 1A, the lower photosensitive film 2 and the first interlayer film 3 are sequentially formed on the substrate 1, and the upper photosensitive film 4 is patterned on the first interlayer film 3. The first interlayer film 3 is selectively removed using the upper photosensitive film 4 as a mask as in the first b.
다음, 제1c도와 같이 제1층간막(3)을 마스크로 하여 상기 상층감광막(4) 전체와 하층감광막(2)를 선택적으로 제거한 후 제1d도와 같이 제1층간막(3)을 전부 제거하여 하층감광막(2)를 정의한다.Next, as shown in FIG. 1C, the entire upper photosensitive film 4 and the lower photosensitive film 2 are selectively removed using the first interlayer film 3 as a mask, and then the first interlayer film 3 is completely removed as shown in FIG. 1D. The lower photosensitive film 2 is defined.
그러나 이와같은 종래의 기술에 있어서, 하층감광막(2)의 단차가 크므로 하층감광막(2)는 일직선으로 제거되지 않고 활모양으로 제거되고 제1d와 같이 하층감광막(2) 제거시 측벽에 쌓였던 폴리머(polymer)가 제1층간막(3)제거시 함께 제거되어 하층감광막(2)의 손실을 유발시키는 단점이 있었다.However, in such a conventional technique, since the step of the lower photosensitive film 2 is large, the lower photosensitive film 2 is not removed in a straight line but is removed in a bow shape, and the polymer accumulated on the sidewalls when the lower photosensitive film 2 is removed as in 1d. When the first interlayer film 3 is removed, the polymer is removed, causing a loss of the lower photosensitive film 2.
본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 안출한 것으로, 식각할 하층감광막의 단차가 클 경우, 하층감광막의 측벽에 제2층간막을 형성하여 하층감광막을 일직선으로 제거할 수 있는 반도체 셀 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and when the step of the lower photosensitive film to be etched is large, a method of manufacturing a semiconductor cell capable of removing the lower photosensitive film in a straight line by forming a second interlayer on the sidewall of the lower photosensitive film The purpose is to provide.
상기 목적을 달성하기 위한 본 발명의 반도체 셀 제조 방법은 기판상에 하층감광막과 상기 하층감광막에 제1층간막을 형성하는 공정과, 상기 제1층간막상에 상층감광막을 형성하고 패터닝하여 상층감광막 패턴을 형성하는 공정과, 상기 상층감광막 패턴을 마스크로하여 상기 제1층간막을 선택적으로 제거하고 상기 하층감광막을 일정 깊이 식각함과 동시에 상층감광막 패턴을 제거하여 개구를 형성하는 공정과, 전면에 제2층간막을 형성하고 이방성 식각하여 식각된 상기 하층감광막의 측면에 제2층간막을 측벽 형태로 남기는 공정과, 상기 제2층간막을 마스크로하여 상기 개구에 대응되는 상기 하층감광막을 제거하는 공정을 포함하는 것을 특징으로 한다.The semiconductor cell manufacturing method of the present invention for achieving the above object is a step of forming a lower layer photosensitive film and a first interlayer film on the lower layer photosensitive film on a substrate, and forming an upper layer photosensitive film on the first interlayer film and patterned to form an upper photosensitive film pattern Forming the openings by selectively removing the first interlayer film using the upper photoresist pattern as a mask, etching the lower photoresist layer at a predetermined depth, and removing the upper photoresist pattern; Forming a film and anisotropically etching and leaving a second interlayer film in the form of sidewalls on the side surface of the lower layer photosensitive film; and removing the lower photoresist film corresponding to the opening by using the second interlayer film as a mask. It is done.
이하에서 본 발명의 실시예를 첨부된 도면을 참고하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 반도체 셀 제조를 나타낸 것으로 제2a,b도는 종래와 같으며 제2c도와 같이 제1층간막(3)을 마스크로 하여 상기 상층감광막(4) 전부와, 상층감광막(4) 두께만큼(상층감광막(4)가 전부 제거되는 시점)의 하층감광막(2) 또는 상층감광막(4) 전부와, 하층감광막(2) 전체 두께중 반 만큼을 제거하고, 제2d도와 같이 하층감광막(2)의 측벽 손실 방지를 위해 전표면에 제2층간막(5)을 형성한다.FIG. 2 shows the manufacture of the semiconductor cell of the present invention. FIGS. 2A and 2B are the same as in the prior art, and as shown in FIG. 2C, the upper photoresist film 4 and the upper photoresist film 4 are formed using the first interlayer film 3 as a mask. The lower layer photosensitive film 2 or the entire upper layer photosensitive film 4 and half of the total thickness of the lower layer photosensitive film 2 at the same thickness (at the time when the upper photosensitive film 4 is completely removed) are removed, and the lower layer photosensitive film ( The second interlayer film 5 is formed on the entire surface to prevent sidewall loss of 2).
다음 제2e도와 같이 이방성 식각 공정으로 제1층간막(3) 상부의 제2층간막(5)을 제거하여 상기 패터닝되어진 제1층간막(3) 및 하층감광막(2)의 측면에만 제2층간막(5)이 측벽 형태로 남도록 한다.Next, as shown in FIG. 2E, the second interlayer 5 on the first interlayer 3 is removed by an anisotropic etching process, so that only the side surfaces of the patterned first interlayer 3 and the lower photoresist 2 are interposed therebetween. The film 5 is left in the form of a side wall.
이어, 제2f도와 같이, 두 층간막(3,5)을 마스크로 하여 하층감광막(2)을 제거한후 제2g도와 같이 상기 두 층간막(3,5)을 전부 제거하여 하층감광막(2) 패턴을 정의하여 후속 공정을 진행한다.Subsequently, as shown in FIG. 2F, the lower photoresist film 2 is removed using the two interlayer films 3 and 5 as a mask, and then the lower photoresist film 2 pattern is removed by completely removing the two interlayer films 3 and 5 as shown in FIG. 2G. Proceed to the subsequent process by defining.
이상에서 설명한 바와 같이 본 발명은 하층감광막(2)의 제거공정중에 제2층간막(5)을 형성하므로써 하층감광막(2)의 측벽에 산화막성의 폴리머를 유기시키므로 수직 형태로 하층감광막(2)을 정의할 수 있는 효과가 있다.As described above, the present invention forms the second interlayer film 5 during the removal process of the lower layer photosensitive film 2, thereby inducing an organic polymer of an oxide film on the sidewall of the lower layer photosensitive film 2, so that the lower layer photosensitive film 2 is vertically formed. There is an effect that can be defined.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920010035A KR100249186B1 (en) | 1992-06-10 | 1992-06-10 | Method for manufacturing semiconductor cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920010035A KR100249186B1 (en) | 1992-06-10 | 1992-06-10 | Method for manufacturing semiconductor cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940001321A KR940001321A (en) | 1994-01-11 |
| KR100249186B1 true KR100249186B1 (en) | 2000-03-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920010035A KR100249186B1 (en) | 1992-06-10 | 1992-06-10 | Method for manufacturing semiconductor cell |
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| Country | Link |
|---|---|
| KR (1) | KR100249186B1 (en) |
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1992
- 1992-06-10 KR KR1019920010035A patent/KR100249186B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR940001321A (en) | 1994-01-11 |
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