KR100248342B1 - Method for forming of metal wire of semiconductor device - Google Patents

Method for forming of metal wire of semiconductor device Download PDF

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Publication number
KR100248342B1
KR100248342B1 KR1019960068902A KR19960068902A KR100248342B1 KR 100248342 B1 KR100248342 B1 KR 100248342B1 KR 1019960068902 A KR1019960068902 A KR 1019960068902A KR 19960068902 A KR19960068902 A KR 19960068902A KR 100248342 B1 KR100248342 B1 KR 100248342B1
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South Korea
Prior art keywords
etching
film
forming
metal wiring
gas
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KR1019960068902A
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Korean (ko)
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KR19980050124A (en
Inventor
이승욱
설여송
최창주
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김영환
현대전자산업주식회사
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Priority to KR1019960068902A priority Critical patent/KR100248342B1/en
Priority to TW086117626A priority patent/TW350999B/en
Priority to GB9725029A priority patent/GB2320613B/en
Priority to JP34658297A priority patent/JP3238363B2/en
Priority to CN97121734A priority patent/CN1099700C/en
Priority to DE19756227A priority patent/DE19756227A1/en
Publication of KR19980050124A publication Critical patent/KR19980050124A/en
Application granted granted Critical
Publication of KR100248342B1 publication Critical patent/KR100248342B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

본 발명은 반도체소자의 금속배선 형성 방법에 관한것으로, 텅스텐 배선을 형성할때 감광막에 대하여 고 식각선택비를 갖도록 하기 위해 식각 파라메타중에 소스 전력의 증가, 바이어스 전력의 감소 및 식각 가스의 비율을 변화시켜 식각선택비를 향상시키는 기술이다. 또한, 상기와 같은방법으로 감광막에 대한 식각선택비를 높일 경우 금속 배선의 내측벽으로 라운드된 요부가 발생되는 문제점을 해결하기 위하여 식각 공정을 저온에서 진행한다. 그로인하여 수직한 측벽 프로파일을 갖는 금속 배선을 형성할 수 가 있다.The present invention relates to a method for forming a metal wiring of a semiconductor device, in order to have a high etching selectivity with respect to the photosensitive film when forming the tungsten wiring, the increase of the source power, the decrease of the bias power and the ratio of the etching gas during the etching parameters Technology to improve the etching selectivity. In addition, when the etching selectivity for the photoresist film is increased in the same manner as above, the etching process is performed at a low temperature to solve a problem in which recesses rounded to the inner wall of the metal wiring are generated. This allows the formation of metal wires with vertical sidewall profiles.

Description

반도체소자의 금속 배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 텅스텐 배선을 형성할때 감광막에 대하여 고 식각선택비를 갖도록 하는 식각 방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to an etching method for having a high etching selectivity with respect to a photosensitive film when forming tungsten wiring.

반도체소자가 고접적화됨에 따라 금속 배선의 선폭은 미세화되고, 이에 따라 미세 패턴 형성이 가능한 원자의 선용 감광막의 사용이 필수적이다. 그러나, 원자외선용 감광막의 낮은 식각선택비와 식각 공정 여유도(Etch Process Margin)의 부족이 미세패턴의 형성에 큰 어려움으로 대두된다.As semiconductor devices become highly integrated, line widths of metal wirings become fine, and thus, it is necessary to use a line photosensitive film of atoms capable of forming a fine pattern. However, the low etch selectivity and the lack of etching process margin of the ultraviolet ray photosensitive film are a great difficulty in forming the fine pattern.

즉, 단차가 있는 지역에 증착된 금속 배선층 상부에서 감광막을 도포하고, 노광 및 현상 공정으로 감광막 패턴을 형성한다음, 노출된 금속 배선층을 식각할때 상기 금속 배선에 대한 감광막의 낮은 식각선택비로 인하여 단차가 높은 지역에 얇은 두께로 도포된 감광막이 식각되어 하부의 금속 배선층이 노출되고, 결국 금속 배선층이 식각되어 불량이 발생하는등 식각 여유도가 저하되는 문제가 발생된다. 또한, 감광막이 모두 식각된후 금속 배선층이 들어나서 식각 될때 폴리머에 의해 부분적인 식각 속도 차이가 유발되고, 이로 인해 금속의 표면이 매우 거칠어지는 문제가 발생된다.That is, by applying a photoresist film on the metal wiring layer deposited in the stepped area, and forming a photoresist pattern by the exposure and development process, due to the low etching selectivity of the photoresist with respect to the metal wiring when etching the exposed metal wiring layer The photoresist coated with a thin thickness is etched in an area where the step height is high to expose the lower metal wiring layer, and eventually, the metal wiring layer is etched, resulting in a problem of deterioration of the etching margin. In addition, when all of the photoresist film is etched, when the metal wiring layer enters and is etched, a partial etching rate difference is caused by the polymer, which causes a problem that the surface of the metal is very rough.

종래기술을 도 1 및 도 2를 참조하여 설명하면 다음과 같다.The prior art will be described with reference to FIGS. 1 and 2 as follows.

도 l은 단차를 갖는 하부층(1) 상부에 베리어층(2), 텅스텐층(3), 반사방지막(4)을 적층하고, 그상부에 감광막(5)을 도포한 단면도이다. 하부층(1)의 단차가 높은 곳은 감광막(5)의 두꼐가 얇은 것을 알수 있다.FIG. 1 is a cross-sectional view in which the barrier layer 2, the tungsten layer 3, and the antireflection film 4 are laminated on the lower layer 1 having a step, and the photosensitive film 5 is applied thereon. It can be seen that the thickness of the photosensitive film 5 is thin where the step height of the lower layer 1 is high.

도 2는 금속 배선 마스크를 이용한 노광 및 현상 공정으로 감광막패턴(5A)을 형성한다음, 노출된 지역의 반사방지막(4), 텅스텐층(3) 및 베리어층(2)을 순차적으로 식각하여 금속 배선을 형성한 단면도로서, 상기텅스텐층(3)의 측벽에 요홈이 형성되어 측벽 프로파일이 불량함을 도시한다.FIG. 2 illustrates the formation of the photoresist pattern 5A by an exposure and development process using a metal wiring mask, followed by sequentially etching the antireflection film 4, the tungsten layer 3 and the barrier layer 2 in the exposed area. As a cross-sectional view of the wiring, grooves are formed in the side wall of the tungsten layer 3, indicating that the side wall profile is poor.

상기한 문제들을 해결하기 위하여 텅스텐층 상부에 텅스텐과 식각선택비가 높은 하드 마스크층 예를들어 티타늄 나이트라이드막 또는 실리콘 산화막을 두껍게 증착하여 식각 베리어로 이용하는 공정을 진행하여 왔는데 이는 후속 공정으로 진행되는 상부 금속 배선과의 콘택저항을 증대시키는 또다른 문제가 발생된다.In order to solve the above problems, a hard mask layer having a high etching selectivity, such as a titanium nitride film or a silicon oxide film, is deposited thickly on the tungsten layer and used as an etching barrier. Another problem arises that increases the contact resistance with the metal wiring.

본 발명은 종래의 텅스텐 배선을 식각할때 감광막과의 낮은 식각선택비로 인해 발생되는 문제점을 해결하기 위하여 텅스텐 식각 조건을 변화시켜 텅스텐 배선과 감광막 사이에 높은 식각선택비를 갖도록 하는 반도체소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.In order to solve the problems caused by the low etching selectivity with the photoresist when etching the conventional tungsten wiring, the metal wiring of the semiconductor device having a high etching selectivity between the tungsten wiring and the photoresist by changing the tungsten etching conditions The purpose is to provide a formation method.

도 1 및 도 2는 종래 기술에 의해 금속배선을 형성하는 단계를 도시한 단면도이다.1 and 2 are cross-sectional views showing a step of forming a metal wiring by the prior art.

도 3은 본 발명의 실시예에 금속 배선을 형성한 것을 도시한 단면도이다.3 is a cross-sectional view showing the formation of a metal wiring in an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 하부막 2 : 베리어막1: lower film 2: barrier film

3 : 텅스텐층 4 : 반사방지막3: tungsten layer 4: anti-reflection film

5 : 감광막 5A : 감광막 패턴5: photosensitive film 5A: photosensitive film pattern

상기한 목적을 달성하기 위한 본 발명은 반도체소자의 금속 배선 형성 방법에 있어서, 반도체기판 상부에 베리어막, 텅스텐층, 반사방지막을 형성하는 단계와, 상기 반사방지막 상부에 감광막 패턴을 형성하는 단계와, 저온 및 고밀도 플라즈마에서 상기 반사방지막, 텅스텐층, 베리어막을 순차적으로 식각하여 수직한 측벽 프로파일을 갖는 금속배선을 형성하는 단계로 이루어진다.In accordance with another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: forming a barrier film, a tungsten layer, and an antireflection film on an upper surface of a semiconductor substrate, and forming a photoresist pattern on the antireflection film; And sequentially etching the antireflection film, tungsten layer and barrier film in a low temperature and high density plasma to form a metal wiring having a vertical sidewall profile.

본 발명은 텅스텐 식각 공정시 감광막과의 낮은 식각선택비를 텅스텐 식각 파라메타중에 소스 전력의 증가, 바이어스 전력의 감소 및 식각가스의 비율을 변화시켜 식각선택비를 향상시키는 기술이다.The present invention improves the etching selectivity by changing the low etching selectivity with the photosensitive film during the tungsten etching process by increasing the source power, the bias power and the ratio of the etching gas in the tungsten etching parameters.

또한, 상기와 같은 방법으로 감광막에 대한 식각선택비를 높일 경우 금속 배선의 내측벽으로 라운드된 요부가 발생되는 문제점을 해결하기 위하여 식각 공정을 저온에서 진행한다. 그로인하여 수직한 측벽 프로파일을 갖는 금속 배선을 형성할 수 가 있다.In addition, when the etching selectivity for the photoresist film is increased in the above manner, the etching process is performed at low temperature in order to solve a problem in which recesses rounded to the inner wall of the metal wiring are generated. This allows the formation of metal wires with vertical sidewall profiles.

참고로, 식각 공정을 저온 에서 실시하는 경우 텅스텐이 식각되면서 측벽에 보호막이 형성되기 때문에 수직한 측벽 프로파일을 얻을수 있으며, 이보호막은 텅스텐 배선을 형성한다음, 크리닝 공정시 완전히 제거된다.For reference, when the etching process is performed at a low temperature, since a protective film is formed on the sidewall while tungsten is etched, a vertical sidewall profile is obtained. The protective film forms a tungsten wire and is completely removed during the cleaning process.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 실시예에 의해 금속 배선을 형성한 단면도를 도시한 것으로, 도 1과 같이 단차를 갖는 하부층(1) 상부에 베리어층(2), 텅스텐층(3), 반사방지막(4)을 적층하고, 그상부에 원자외선용 감광막(5)을 도포한 다음, 감광막 패턴(5A)을 형성한다음, 본 발명에 의한 식각 공정을 진행한 것이다.3 is a cross-sectional view showing a metal wiring according to an embodiment of the present invention. The barrier layer 2, the tungsten layer 3, and the anti-reflection film 4 are disposed on the lower layer 1 having a step as shown in FIG. ), A photoresist film 5 for ultraviolet rays is applied on the upper surface thereof, a photoresist film pattern 5A is formed, and then the etching process according to the present invention is performed.

즉, 본발명에 의한 베리어층(4), 텅스텐층(3) 및 반사방지막(2) 을 식각하는 공정은 고 밀도의 플라즈마(예를들어 1012-13)를 얻기 위하여 헬리콘 소스(Helicon Source)를 이용하고, 소스 전력은 1 내지 3 KWatt로 설정한다. 또한, 이온의 물리적인 힘을 감소시켜 감광막 패턴이 식각되는 것을 감소시키기 위해 챔버 내의 전극에 인가하는 바이어스 전력을10-50Watt로 설정 한다.That is, the process of etching the barrier layer 4, the tungsten layer 3 and the anti-reflection film 2 according to the present invention in order to obtain a high-density plasma (for example, 10 12-13 ) Helicon Source (Helicon Source) ), The source power is set to 1 to 3 KWatt. In addition, the bias power applied to the electrode in the chamber is set to 10-50 Watts to reduce the physical force of the ions to reduce the etching of the photoresist pattern.

그리고, 상기와 같은 조건으로 식각공정을 진행하면 감광막에 대한 금속층들의 식각선택비가 높아지는 반면 형성되는 텅스텐층 배선의 측벽에 라운드된 요부가 발생되는데 이러한 문제점을 해결하기 위하여 챔버내의 전극 온도를 -60℃ 내지 0℃로 유지한다.In addition, when the etching process is performed under the above conditions, the etch selectivity of the metal layers with respect to the photoresist film is increased, while rounded recesses are formed on the sidewall of the tungsten layer wiring to be formed. To 0 ° C.

참고로, 상기 감광막 패턴(5A)을 마스크로 이용하여 식각 공정을 진행할때 상기 반사방지막(4)은 염소계 가스 예를들어 Cl2, BCl3등을 이용하며, 동일 챔버에서 연속적으로 텅스텐층(3)을 불소계(예를들어 SF6, CF4, NF3, 등)에 질소를 혼합하거나 불소계에 산소와 아르곤을 혼합하여 식각공정을 진행하고, 동일 챔버에서 연속적으로 하부의 베리어막(2)은 상기염소계 가스를 이용하여 식각공정을 진행한다.For reference, when the etching process is performed using the photoresist pattern 5A as a mask, the antireflection film 4 uses a chlorine-based gas, for example, Cl 2 , BCl 3 , and the like, and the tungsten layer 3 is continuously formed in the same chamber. ) Is mixed with fluorine (for example, SF 6 , CF 4 , NF 3 , etc.) or oxygen and argon with fluorine, and the etching process is performed in the same chamber. An etching process is performed using the chlorine-based gas.

상기 텅스텐층(3)을 식각할때 불소계(예를들어 SF6, CF4, NF3, 등)에 질소를혼합하거나 산소와 아르곤을 혼합가스의 전체양은 50-500SCCM(Standard Cubic Centimeter) 정도이며, 질소(또는 산소 + 아르곤)/[불소계 + 질소(또는 산소 +아르곤)]의 비율이 0-50% 정도이다.When the tungsten layer 3 is etched, nitrogen is mixed with fluorine (for example, SF 6 , CF 4 , NF 3 , etc.) or oxygen and argon, the total amount of the mixed gas is about 50-500SCCM (Standard Cubic Centimeter). , The ratio of nitrogen (or oxygen + argon) / [fluorine + nitrogen (or oxygen + argon)] is about 0-50%.

상기한바와같이 본 발명은 단차를 갖는 하부막 상에 극 미세 선폭을 갖는 금속 배선을 형성할때 감광막과 금속층간의 식각선택비를 향상시켜서 식각 마진을 증대시키고, 종래에 식각선택비를 향상시키기 위해 사용되는 하드 마스크층의 두께를 줄이거나 생략할수가 있으므로 후속 공정을 용이하게 하고, 콘택 저항이 증대되는 것을 방지 할 수가 있다.As described above, the present invention improves the etching selectivity between the photosensitive film and the metal layer when forming the metal wiring having the extremely fine line width on the lower layer having the step height, thereby increasing the etching margin, and conventionally improving the etching selectivity. The thickness of the hard mask layer used for reducing the thickness can be reduced or omitted, thereby facilitating subsequent processes and preventing contact resistance from increasing.

Claims (9)

반도체소자의 금속 배선 형성 방법에 있어서, 반도체기판 상부에 베리어막, 텅스텐층, 반사방지막이 순차적으로 형성된 적층구조를 형성하는 단계와, 상기 반사방지막 상부에 금속배선으로 예정되는 부분을 보호하는 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 식각마스크로 사용하여 상기 적층구조를 순차적으로 식각하되, 식각챔버내의 온도를 160℃~0℃로 하고, 바이어스 전력은 10~50Watt로 하고, 소스전력은 1~3kWatt로 하여 염소계 가스 및 불소계 가스를 포함하는 혼합가스에 의한 고밀도플라즈마 식각방법으로 동일한 챔버내에서 식각하여, 상기 적층구조의 식각면에 보호막을 형성시켜 수직한 측벽 프로파일을 갖는 금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.A method of forming a metal wiring of a semiconductor device, the method comprising: forming a stacked structure in which a barrier film, a tungsten layer, and an antireflection film are sequentially formed on an upper surface of a semiconductor substrate, and a photoresist pattern protecting a portion of the semiconductor substrate, the metal wiring being formed on the antireflection film. And etching the laminate structure sequentially using the photoresist pattern as an etch mask, wherein the temperature in the etch chamber is 160 ° C. to 0 ° C., the bias power is 10 to 50 Watts, and the source power is 1. Etching in the same chamber by a high density plasma etching method using a mixed gas containing chlorine gas and fluorine gas at ˜3 kWatt, forming a protective film on the etching surface of the laminated structure to form a metal wiring having a vertical sidewall profile. A metal wiring forming method for a semiconductor device, characterized in that consisting of steps. 제1항에 있어서, 상기 베리어막은 티타늄과 티타늄 나이트라이드막의 적층 구조인것을 특징으로 하는 반도체소자의 금속 배선 형성방법.2. The method of claim 1, wherein the barrier film is a stacked structure of titanium and titanium nitride film. 제1항에 있어서, 상기 반사방지막은 티타늄 나이트라이드막인 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein the anti-reflection film is a titanium nitride film. 제1항에 있어서, 상기 고밀도 플라즈마를 얻기 위해 헬리콘 소스(Helicon Source)를 이용하는 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein a helicon source is used to obtain the high density plasma. 제1항에 있어서, 상기 염소계 가스는 Cl2또는 BCl3인것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein the chlorine-based gas is Cl 2 or BCl 3 . 제1항에 있어서, 상기 혼합가스는 불소계 가스에 질소 또는 산소와 아르곤이 혼합되어 있는 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein the mixed gas is a mixture of nitrogen, oxygen, and argon in a fluorine-based gas. 제6항에 있어서, 상기 혼합가스의 유량은 50-500SCCM(Standard Cubic Centimeter) 인 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 6, wherein the flow rate of the mixed gas is 50-500 SCCM (Standard Cubic Centimeter). 제6항 또는 제7항에 있어서, 상기 혼합가스는 질소/[불소계 가스 + 질소]의 비율이 0-50% 정도인 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.8. The method of claim 6 or 7, wherein the mixed gas has a ratio of nitrogen / [fluorine-based gas + nitrogen] of about 0-50%. 제6항 또는 제7항에 있어서, 상기 혼합가스는 (산소 + 아르곤)/[불소계 가스 + 산소 + 아르곤]의 비율이 0-50% 정도인 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 6 or 7, wherein the mixed gas has a ratio of (oxygen + argon) / [fluorine-based gas + oxygen + argon] in a range of about 0-50%.
KR1019960068902A 1996-12-20 1996-12-20 Method for forming of metal wire of semiconductor device KR100248342B1 (en)

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TW086117626A TW350999B (en) 1996-12-20 1997-11-25 Method for forming metal lines of semiconductor device
GB9725029A GB2320613B (en) 1996-12-20 1997-11-26 Method for forming metal lines of semiconductor device
JP34658297A JP3238363B2 (en) 1996-12-20 1997-12-16 Method for forming metal wiring of semiconductor device
CN97121734A CN1099700C (en) 1996-12-20 1997-12-17 Method for forming of semi-conductor device
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