KR100236024B1 - Manufacturing method of thin film transistor - Google Patents
Manufacturing method of thin film transistor Download PDFInfo
- Publication number
- KR100236024B1 KR100236024B1 KR1019920001208A KR920001208A KR100236024B1 KR 100236024 B1 KR100236024 B1 KR 100236024B1 KR 1019920001208 A KR1019920001208 A KR 1019920001208A KR 920001208 A KR920001208 A KR 920001208A KR 100236024 B1 KR100236024 B1 KR 100236024B1
- Authority
- KR
- South Korea
- Prior art keywords
- source
- layer
- drain
- thin film
- antimony
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052787 antimony Inorganic materials 0.000 claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000010408 film Substances 0.000 claims description 6
- 229910001245 Sb alloy Inorganic materials 0.000 claims description 5
- 239000002140 antimony alloy Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 45
- 229910017875 a-SiN Inorganic materials 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 229910006913 SnSb Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910017115 AlSb Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 공정을 단순화하여 공정 비용을 줄이고, 보다 좋은 설계 조건을 제공하기 위한 것으로 종래의 공정에서 임의의 도전형층을 형성하기 위해서는 이온 주입하거나 도핑된 물질을 사용함으로 공정이 복잡했다.The present invention is to simplify the process to reduce the process cost, and to provide better design conditions, the process is complicated by using ion implanted or doped material to form any conductive type layer in the conventional process.
이를 해결하기 위하여, 안티몬계의 금속층과 폴리실리콘층의 접촉면은 열처리하면 안티몬 원자가 폴리실리콘층에 확산됨을 이용하여 공정을 단순화하였고 더불어 공정 비용이 감소하게 되었다.In order to solve this problem, the contact surface of the antimony-based metal layer and the polysilicon layer is heat-treated, and antimony atoms are diffused into the polysilicon layer, thereby simplifying the process and reducing the process cost.
Description
제1도는 종래의 비정질 규소 박막 트랜지스터의 구조단면도1 is a structural cross-sectional view of a conventional amorphous silicon thin film transistor
제2도는 종래의 폴리실리콘 박막 트랜지스터의 구조단면도2 is a structural cross-sectional view of a conventional polysilicon thin film transistor
제3도는 본발명 제1실시예의 박막 트랜지스터의 구조단면도3 is a structural cross-sectional view of the thin film transistor according to the first embodiment of the present invention.
제4도는 본발명 제2실시예의 박막 트랜지스터의 구조단면도4 is a structural cross-sectional view of a thin film transistor according to a second embodiment of the present invention.
제5도는 본발명 제3실시예의 박막 트랜지스터의 구조단면도5 is a structural cross-sectional view of the thin film transistor according to the third embodiment of the present invention.
제6도는 본발명 제4실시예의 박막 트랜지스터의 구조단면도6 is a structural cross-sectional view of a thin film transistor according to a fourth embodiment of the present invention.
제7도는 본발명 제5실시예의 박막 트랜지스터의 구조단면도7 is a structural cross-sectional view of a thin film transistor according to the fifth embodiment of the present invention.
제8도는 제3도의 공정단면도8 is a cross-sectional view of the process of FIG.
제9도는 제4도의 공정단면도9 is a cross-sectional view of the process of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 유리기판 2 : 게이트1: glass substrate 2: gate
3,7 : a-SiN층 4 : a-Si층3,7: a-SiN layer 4: a-Si layer
8 : 게이트절연층 9 : 소오스/드레인8 gate insulating layer 9 source / drain
10 : 소오스/드레인전극 11 : 폴리실리콘층10 source / drain electrode 11 polysilicon layer
12 : 금속전극 13 : 게이트 전극12 metal electrode 13 gate electrode
본 발명은 반도체 소자인 트랜지스터에 관한 것으로 특히 공정을 단순화한 박막 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor, which is a semiconductor device, and more particularly to a method for manufacturing a thin film transistor with a simplified process.
종래의 박막 트랜지스터는 제1도 및 제2도와 같다.Conventional thin film transistors are shown in FIGS. 1 and 2.
즉 제1도는 종래의 비정질규소 박막 트랜지스터의 구조단면도로써, 유리기판(1) 위에 금속을 증착하여 포토/에치 공정으로 게이트(2)을 형성하고, 그 위에 플라즈마 화학증착법(PECVD)으로 a-SiN층(3)과 a-Si층(4), a-SiN층(7)을 연속 증착하고 포토/에치 공정으로 a-SiN층(7)을 상기 게이트(2) 위에만 남도록 선택 제거하여 에칭 스토퍼층을 형성한다.1 is a structural cross-sectional view of a conventional amorphous silicon thin film transistor, in which a metal is deposited on a glass substrate 1 to form a gate 2 by a photo / etch process, and a-SiN is formed thereon by plasma chemical vapor deposition (PECVD). Etch stopper by successively depositing layer (3), a-Si layer (4), and a-SiN layer (7) and selectively removing the a-SiN layer (7) to remain only on the gate (2) by a photo / etch process Form a layer.
그리고 전면에 n형 비정질 규소층(5)을 PECVD법으로 증착하고 상기 n형 비정질규소층(5) 위에 금속층(6)을 스퍼터링법으로 증착하여 포토/에치공정으로 a-Si층(4)과 n형 비정질규소층(5), 금속층(6)의 불필요한 부분을 제거하고, 에칭 스토퍼층의 상층 부위의 n형 비정질규소층(5)과 금속층(6)을 패턴닝하여 비정질규소 박막트랜지스터를 완성한다.Then, the n-type amorphous silicon layer 5 is deposited on the entire surface by PECVD, and the metal layer 6 is deposited on the n-type amorphous silicon layer 5 by sputtering. The a-Si layer 4 is formed by a photo / etch process. Unnecessary portions of the n-type amorphous silicon layer 5 and the metal layer 6 are removed, and the n-type amorphous silicon layer 5 and the metal layer 6 in the upper portion of the etching stopper layer are patterned to complete the amorphous silicon thin film transistor. do.
한편, 제2도는 종래의 폴리실리콘 박막트랜지스터의 구조 단면도로써, 유리기판(1)위에 폴리실리콘층을 저압 CVD법으로 증착하여 포토/에치공정으로 패터닝하여 트랜지스터의 활성영역을 형성한 다음, 전면에 케이트 절연층(8)을 증착한다.2 is a cross-sectional view of a structure of a conventional polysilicon thin film transistor, in which a polysilicon layer is deposited on a glass substrate 1 by low pressure CVD to be patterned by a photo / etch process to form an active region of a transistor, and then to a front surface thereof. A gate insulating layer 8 is deposited.
그리고 게이트 절연층(8) 위에 뒤 n+형 폴리실리콘층을 증착하고 선택적으로 제거하여 게이트(2)을 형성한다.The back n + type polysilicon layer is deposited on the gate insulating layer 8 and selectively removed to form the gate 2.
상기 게이트(2)를 마스크로 하여 상기 활성영역에 이온 주입하여 소오스/드레인(9)을 형성한다.The source / drain 9 is formed by ion implantation into the active region using the gate 2 as a mask.
그리고 전면에 층간 절연막을 증착하고 상기 소오스/드레인(9)영역에 접촉구멍을 형성하여 상기 소오스/드레인(9)영역에 금속전극(12)을 형성하면 종래의 폴리실리콘 박막 트랜지스터가 완성된다.A polysilicon thin film transistor is completed by depositing an interlayer insulating film on the entire surface and forming a contact hole in the source / drain 9 region to form a metal electrode 12 in the source / drain 9 region.
그러나 이와 같은 종래의 박막 트랜지스터에 있어서는 다음과 같은 문제점이 있었다.However, such a conventional thin film transistor has the following problems.
즉 도핑된 반도체 박막을 형성하기 위해서 추가의 n+층을 증착하거나 불순물 이온주입함으로써 공정이 복잡하고 생산비가 증가하게 된다.That is, by forming an additional n + layer or implanting impurity ions to form a doped semiconductor thin film, the process is complicated and the production cost is increased.
본발명은 이와 같은 문제점을 해결하기 위한 것으로써, 공정을 간편화하여 공정 비용을 줄이고 보다 좋은 설계 조건을 제공하는데 그 목적이 있다.The present invention is to solve such a problem, the purpose is to simplify the process to reduce the process cost and provide better design conditions.
이와 같은 목적을 달성하기 위한 본발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
제3도는 본발명의 제1실시예인 비정질규소 박막 트랜지스터의 구조단면도로써 제조공정은 제8도와 같다.3 is a structural cross-sectional view of an amorphous silicon thin film transistor according to a first embodiment of the present invention.
즉, 제8도 (a)와 같이 유리기판(1)위에 크롬이나 알루미늄등의 금속을 증착하고 패터닝하여 게이트(2)을 형성하고 제8도 (b)와 같이 전면에 플라즈마화학 증착법으로 게이트 절연막인 a-SiN층(3)과 활성층인 a-Si층(4)과 에치스토퍼층인 a-SiN층(7)을 차례로 연속 증착하여, 포토/에치 공정으로 a-SiN층(7)을 선택제거하여 에칭 스토퍼층을 형성하고 a-Si층(4)을 패터닝하여 채널 영역을 정의한다.That is, as shown in FIG. 8A, a gate 2 is formed by depositing and patterning a metal such as chromium or aluminum on the glass substrate 1, and forming a gate insulating film on the entire surface as shown in FIG. 8B by plasma chemical vapor deposition. Successively depositing the a-SiN layer (3), the a-Si layer (4) as the active layer, and the a-SiN layer (7) as the etch stopper layer, in order, to select the a-SiN layer (7) by the photo / etch process. It is removed to form an etch stopper layer and the a-Si layer 4 is patterned to define the channel region.
그리고 제8도 (c)와 같이 안티몬(Sb)또는 안티몬 합금(AlSb, SnSb)등을 스퍼터링법으로 증착하고 선택적으로 제거하여 소오스/드레인 전극(10)을 형성한다.As shown in FIG. 8C, antimony (Sb) or antimony alloys (AlSb, SnSb) and the like are deposited by sputtering and selectively removed to form a source / drain electrode 10.
그리고 200∼250℃에서 열처리함하여 소오스/드레인 전극(10)에 접촉한 비정질규소층(a-Si층)(4)으로 안티몬(Sb)원자가 확산되도록 하여 그 계면에 n형 비정질 실리콘층(도면에는 도시되지 않음)으로 형성하므로 본발명의 제1실시예인 박막 트랜지스터를 완성한다.Then, the antimony (Sb) atoms are diffused into the amorphous silicon layer (a-Si layer) 4 in contact with the source / drain electrode 10 by heat treatment at 200 to 250 ° C., and an n-type amorphous silicon layer (Fig. (Not shown) to complete the thin film transistor which is the first embodiment of the present invention.
제4도는 본발명의 제2실시예를 n채널 폴리실리콘 박막 트랜지스터 구조 단면도로써, 그 제조공정은 제9도와 같다.4 is a cross-sectional view of a structure of an n-channel polysilicon thin film transistor according to a second embodiment of the present invention, and the manufacturing process thereof is shown in FIG.
즉, 제9도 (a)와 같이 유리기판(1)위에 안티몬합금(SnSb)등을 증착하고 선택적으로 제거하여 소오스/드레인(9)전극을 형성하고 제 9도 (b)와 같이 전면에 폴리실리콘층(11)을 저압화학 기상법(LPCVD)으로 증착한다.That is, as shown in FIG. 9 (a), an antimony alloy (SnSb) or the like is deposited on the glass substrate 1 and selectively removed to form a source / drain (9) electrode, and as shown in FIG. The silicon layer 11 is deposited by low pressure chemical vapor deposition (LPCVD).
이때 LPCVD 공정 온도(400∼700℃)에 의해 소오스/드레인(9)전극으로 부터 안치몬(Sb)원자가 인접합 폴리실리콘층(11)으로 확산되어 소오스/드레인(9)전극에 인접한 폴리실리콘층(11)에 n형 폴리실리콘층이 형성된다.At this time, by the LPCVD process temperature (400 to 700 ° C.), an anchimon (Sb) atom is diffused from the source / drain (9) electrode to the adjacent polysilicon layer 11 and the polysilicon layer adjacent to the source / drain (9) electrode. An n-type polysilicon layer is formed at (11).
그리고 제9도 (c)와 같이 포토/에치 공정으로 폴리실리콘층(11)을 활성영역만 남기고 제거한뒤 제9도(d)와 같이 전면에 LPCVD법으로 게이트 절연층(8)을 증착하고 소오스/드레인(9)에 접촉구멍을 형성한다.As shown in FIG. 9 (c), the polysilicon layer 11 is removed by the photo / etch process, leaving only the active region. Then, as shown in FIG. 9 (d), the gate insulating layer 8 is deposited by LPCVD and then sourced. A contact hole is formed in the drain 9.
그리고 금속층을 증착하고 패터닝하여 게이트전극(13) 및 소오스/드레인(9)전극에 금속전극(12)을 형성한다. 한편 제5도는 본 발명의 제3실시예를 나타낸 구조 단면도로써, 마스크의 레이 아웃만 바꾸어서 트윈-게이트(twin-gate)구조의 박막 트랜지스터를 설명한 것이다.The metal layer is deposited and patterned to form the metal electrode 12 on the gate electrode 13 and the source / drain 9 electrodes. FIG. 5 is a cross-sectional view illustrating a structure of a third embodiment of the present invention, and illustrates a thin film transistor having a twin-gate structure by changing only the layout of a mask.
즉, 유리기판(1)위에 안티몬 합금등을 증착하고 선택적으로 제거하여 소오스/드레인(9)을 형성하고, 전면에 LPCVD법으로 폴리실리콘(11)을 증착한다.That is, an antimony alloy or the like is deposited on the glass substrate 1 and selectively removed to form a source / drain 9, and polysilicon 11 is deposited on the entire surface by LPCVD.
이때 소오스/드레인(9) 사이에 별도의 안티몬합금이 존재하도록 하며 LPCVD 공정 온도에 의해 소오스/드레인(9)으로 부터 안티몬원자(Sb)가 인접한 폴리실리콘층(11)으로 확산하여 n형 폴리실리콘층으로 바뀐다.At this time, a separate antimony alloy is present between the source / drain 9 and n-type polysilicon is diffused from the source / drain 9 to the adjacent polysilicon layer 11 by the LPCVD process temperature. Turns into layers
그리고 상기 폴리실리콘층(11)을 활성영역만 남기고 나머지 부분을 식각 제거한다.The polysilicon layer 11 is etched away while leaving only the active region.
음 게이트 절연층(8)을 증착하고 접촉 구멍 형성하여 금속전극을 형성한다.The negative gate insulating layer 8 is deposited and contact holes are formed to form metal electrodes.
제6도는 본발명의 제4실시예의 박막 트랜지스터의 구조단면도로써, 마스크의 레이아웃을 바꾸어 소오스/드레인(9)과 게이트로 작동하는 금속전극(12)이 서로 겹치지 않도록 일정한 간격(△1)만큼 격리시킴으로써 소오스/드레인간에 고전압이 걸려도 충분히 동작할수 있는 구조이다.FIG. 6 is a structural cross-sectional view of the thin film transistor according to the fourth embodiment of the present invention, in which the mask layout is changed so that the source / drain 9 and the metal electrode 12 acting as a gate are separated by a predetermined interval Δ1 so as not to overlap each other. By doing so, it is possible to operate sufficiently even if high voltage is applied between the source and the drain.
제7도는 본발명의 제5실시예인 박막 트랜지스터의 구조 단면도로써, 제4도와 제6도의 박막 트랜지스터의 구조를 하나의 마스크상에 구현하고 금속전극(12)의 패턴 제작후 보론(Born)이온을 주입하여 P형 폴리실리콘 영역을 형성시켜 CMOS 인버터를 구성한 것이다.7 is a cross-sectional view of a structure of a thin film transistor according to a fifth embodiment of the present invention. The structure of the thin film transistors of FIGS. 4 and 6 is embodied on a single mask and boron ions are formed after fabrication of the pattern of the metal electrode 12. The CMOS inverter is constructed by implanting a P-type polysilicon region.
이상에서 설명한 바와 같이 본발명의 박막 트랜지스터 제조방법에 있어서는 소오스/드레인(9)전극의 재질을 바꾸어 줌으로써 도핑공정을 줄여 공정이 간편화되고 따라서 공정 비용을 절감할수 있고 수율을 향상시키는등의 효과가 있다.As described above, in the method of manufacturing the thin film transistor of the present invention, the doping process is reduced by changing the material of the source / drain (9) electrode, thereby simplifying the process and thus reducing the process cost and improving the yield. .
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920001208A KR100236024B1 (en) | 1992-01-28 | 1992-01-28 | Manufacturing method of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920001208A KR100236024B1 (en) | 1992-01-28 | 1992-01-28 | Manufacturing method of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930017217A KR930017217A (en) | 1993-08-30 |
| KR100236024B1 true KR100236024B1 (en) | 1999-12-15 |
Family
ID=19328377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920001208A KR100236024B1 (en) | 1992-01-28 | 1992-01-28 | Manufacturing method of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100236024B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100575002B1 (en) * | 2004-12-16 | 2006-05-02 | 삼성전자주식회사 | Cmos thin film transistor comprising common gate, logic device comprising the same and method of manufacturing the same |
-
1992
- 1992-01-28 KR KR1019920001208A patent/KR100236024B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930017217A (en) | 1993-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2774952B2 (en) | Method for manufacturing semiconductor device | |
| US5989944A (en) | Method of fabricating self-aligned thin film transistor using laser irradiation | |
| US4637124A (en) | Process for fabricating semiconductor integrated circuit device | |
| KR870010635A (en) | Process for manufacturing optimal CMOS-FET using VLSI technology | |
| KR20030081992A (en) | Poly silicon TFT and method for fabricating of the same | |
| US6177334B1 (en) | Manufacturing method capable of preventing corrosion of metal oxide semiconductor | |
| KR970018255A (en) | PROCESS FOR THE PRODUCTION OF AN INTEGRATED CMOS CIRCUIT | |
| US5268323A (en) | Semiconductor array and method for its manufacture | |
| JP3401036B2 (en) | Semiconductor device structure | |
| KR100236024B1 (en) | Manufacturing method of thin film transistor | |
| KR100209750B1 (en) | Structure of cmos device and method of manufacturing the same | |
| JPS62229880A (en) | Semiconductor device and manufacture thereof | |
| KR100308852B1 (en) | Method of fabricating a thin film transistor | |
| KR100254924B1 (en) | Method of fabricating image display device | |
| KR100193652B1 (en) | Method of manufacturing thin film transistor of liquid crystal display device | |
| KR100451152B1 (en) | Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof | |
| KR100200924B1 (en) | Method for making semiconductor device for connecting active region electrically | |
| KR100301851B1 (en) | Method for fabricating tft | |
| KR100232218B1 (en) | Method of manufacturing semiconductor device | |
| JPH08204200A (en) | Thin film transistor | |
| KR960000954B1 (en) | Semiconductor device fabrication process | |
| KR940000988B1 (en) | Manufacturing method of double gate semiconductor device | |
| KR20030047185A (en) | Method of fabricating Poly Silicon Thin Film Transistor | |
| KR100268891B1 (en) | Thin film transistor and its manufacturing method | |
| KR100260484B1 (en) | Thi film transistor and making method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| N231 | Notification of change of applicant | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070702 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |