KR100219475B1 - A flash memory cell and method for manufacturing and operating thereof - Google Patents

Abstract

A flash memory cell and a method of operating the same are disclosed that can improve read current in a shared bit line cell. The present invention reduces the thickness of the gate oxide layer of the depletion type string select transistor by the thickness of the gate oxide layer of the increased string select transistor, thereby adding a process mask, which is a problem in a conventional shared bit line cell, and a string select transistor due to high integration. It is possible to solve the problem of reducing the read current through. In addition, the cell string current can be increased by operating the read voltage applied to the string select transistor in the shared bit line cell from Vcc and 0V to Vcc or more and 0V or more.

Description

Flash memory cell, manufacturing method and operating method thereof

1 is a plan view of a conventional single bit NAND flash memory cell.

2 is an equivalent circuit diagram of FIG.

3 is a table summarizing the operating voltages of the memory cells shown in FIG.

4 is an equivalent circuit diagram of a flash memory cell using a conventional self-boosting technique.

5A and 5B are timing charts summarizing each operation schedule of the memory cells shown in FIG.

6 is a plan view of a NAND flash memory cell with a conventional shared bit line.

7 is an equivalent circuit diagram of FIG.

8A to 8C are timing charts summarizing each operation schedule of the memory cells shown in FIG.

9A to 9D are process cross-sectional views illustrating the method of manufacturing the flash memory cell shown in FIG.

10 is a plan view of a NAND flash memory cell according to the present invention.

11 is an equivalent circuit diagram of FIG.

12A to 12D are cross sectional views for explaining the method for manufacturing a memory cell according to the present invention.

13A to 13C are timing charts summarizing each operation schedule of the memory cell according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a NAND flash memory cell capable of improving read current in a shared bit line cell, a method of manufacturing the same, and a method of operating the same. It is about.

A nonvolatile memory capable of electrically storing and erasing data generally forms a unit cell in a stacking structure of a floating gate and a control gate, and a plurality of cells are connected to a plurality of bit lines, word lines, and source lines. Bit lines, word lines, and source lines are formed at regular intervals to form a cell array.

In particular, an array of NAND flash EEPROMs in which a plurality of word lines exist between a bit line and a source line may be described. A string select line and a ground select line for connecting a bit line and a source line with a unit cell (hereinafter, SSL, GSL) is a structure in which a plurality of unit cells connect each source / drain in series to form a unit string, and the unit string has a structure in which a plurality of unit strings are connected in parallel to a bit line.

This conventional structure is described in a paper entitled A 4-Mbit NAND EEPROM with tight programmed vt distribution, published in 1990 on system on VLSI circuits, pp. 105-106.

1 is a layout of a NAND flash memory cell described in the paper, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is an erase circuit, a program, and a selected cell in the equivalent circuit of FIG. The table summarizes the operating voltage of each node when reading.

Referring to the drawings, a cell operation is as follows.

First, a program operation of resisting electrons to a floating gate applies a program voltage Vpgm to the word line W / L3 of the select cell A, and selects unselected word lines and string select line SSL. Vpass voltage is applied to the select bit line (B / L1) and GSL, and Vpi is applied to the unselected bit line (B / L2), respectively. It is injected into the floating gate through a thin tunneling oxide within 100 kHz. In the unselected cell B, the channel of the cell B is induced by the Vpi voltage applied to the unselected bit line (B / L2) and the Vpass voltage applied to the unselected word line. The electric field caused by the Vpgm voltage is reduced to suppress tunneling of electrons.

The erase field that removes electrons from the floating gate of the cell applies 0V voltage to all word lines of the string containing the select cell and Verase voltage to the bulk silicon, respectively. The electrons are erased in the floating gate and holes are injected. Therefore, in the read operation, the threshold voltage Vth of the cell changes to +1 V when electrons are stored in the cell, and the threshold voltage Vth of the cell changes to −3 V when holes are stored in the cell. 0V is applied to the selection word line W / L3 to read out 0 or 1 data depending on whether a current path is formed through the selection cell A or not.

In the above operation, it can be seen that a cell array is formed in the pocket p-well to separate a voltage of about 20V applied to the bulk during the erase operation from the bulk operation region of the peripheral circuit.

However, in the high-density flash memory using the above-described operation scale, in order to prevent program disturb, the Vpi voltage applied to the unselected bit line B / L2 must be applied with a voltage higher than the supply voltage Vcc. The Vcc voltage should be generated by charge pumping using a capacitor. In this case, the required capacitor has a problem in that the program time increases according to a time delay required for charging the increased bit line capacitor to Vpi due to high integration.

To improve this, a technique of selfboosting the Vpi voltage on the channel of an unselected string during programming was disclosed in ISSCC, pp128-129, A 3.3 V 32 Mb NAND Flash Memory with incremental step pulse programming sheme in 1995.

An automatic boosting method will be described with reference to FIG. 4 showing an equivalent circuit diagram of a cell array for implementing the self-boosting technique and a timing diagram of FIG. 5 showing each node voltage according to an operation scale thereof. The equivalent circuit of the cell array implementing the automatic boosting technique shown in FIG. 4 is the same as that of FIG.

The program first sets Vcc to unselected bit lines (B / L2) and SSL, Vpgm to select word lines (W / L3), and Vpgm and Vcc to unselected word lines to automatically boost constant voltage across all cell channels. The Vpass voltage is applied to the selected bit line (B / L1), bulk and SSL, respectively, so that the channel region electrically separated from the bit line and source line by the SSL and GSL voltages is equal to or greater than Vcc by the word line voltage. Automatic boost to constant voltage.

At this time, the channel voltage of the cell connected to the selected word line and the unselected bit line is not boosted by the Vcc and SSL Vcc voltages applied to the unselected bit line, so that a discharge path through the bit line is not generated. Even if Vpgm is applied to the word line, the voltage difference with the floating gate is reduced by the bluk voltage, thereby preventing tunneling of electrons through the tunnel oxide, thereby preventing unwanted cell programming.

As such, since the automatic boosting technique increases only the word line voltage to Vcc or more by charge pumping, the capacitor area and the bit line charging time can be reduced compared to the prior art which needs to increase the bit line voltage, thereby improving chip operation. On the other hand, due to the decrease in the active pitch due to the high integration of the cell, it acts as a limiting factor of the cell scale down.

That is, in the typical layout structure of the single bit line NAND flash described above, unit string cells are connected through one bit line and a bit line contact. Accordingly, the active overlap of the string and the contact overlap area of the metal for contact and bit line form one pitch of the cell as shown in a planar layout shown in FIG. There is a need for a complex transformed process using the light and the like, which causes problems such as adding a process step.

To overcome this limitation, shared bit line cell technology, in which two neighboring strings share one bit line, is described in US Pat. No. 4,962,481, EEPROM GATE WITH PLURALITY OF MEMORY STRINGS MADE OF FLOATING GATE. Published in TRANSISTORS CONNECTED IN SERIES. The technique is operated in such a way that the cell operation, unlike the prior art, injects electrons in the floating gate through the tunnel oxide at the floating gate of the cell during programming.

This shared bit line structure, as shown in the cell layout of FIG. 6, adds one SSL to the existing single bit line cell, which is for selecting one of two strings that share a bit line contact. Each Vth of two string select transistors connected to two SSLs is configured differently.

That is, as shown in the equivalent circuit diagram of FIG. 7, when the Vth of the left transistor of SSL1 is 1V, the Vth of the neighboring right SSL selection transistor is -2V. In addition, Vth of the left transistor of SSL2 was -2V and Vth of the right transistor was + 1V.

In addition, the ground select line (GSL), which is not used in the conventional shared bit line, is applied as a single bit line cell for improved cell operation.

The operation of the memory cell having such a configuration will be described with reference to FIGS. 8A to 8C which summarize each operation scale of the selected cell.

First, the erasing operation will be described with reference to FIG. 8A, which shows a timing diagram at the time of erasing the selected cell ('A' in FIG. 7).

Verase voltage of about 20V is applied to the bulk and erase voltage is applied to SSL and GSL to prevent the gate oxide from being destroyed by eliminating the voltage difference between the bulk and the gate. The word line (W / L2) of the selection string is 0V, the word line of the non-selection string is floating, and the electrons in the floating gate are discharged through the bulk due to the voltage difference between the selection word line and the bulk. As a result, the Vth of the cell is shifted to -3V.

Referring to FIG. 8D showing a timing diagram of a program operation, the program first applies Vcc to B / L, SSL, and SSL2, and applies a Vpass voltage higher than Vcc or Vcc and lower than Vpgm to W / L. The voltage applied to the B / L is precharged to the cell channel. Subsequently, when voltages of Vpgm are selected to the selected W / L, 0 V to the SSL2, and 0 V to the B / L1 are sequentially applied, the precharge voltage induced in the selected cell channel is discharged through the B / L to maintain 0 V, and W Vpgm of about 18V applied to / L causes electrons to be injected from the bulk into the floating gate through the tunnel oxide, thereby changing the cell Vth to -1V.

At this time, the erase cell connected to the selected W / L of the unselected bit line (B / L2) is stressed, but the cell channel connected to the unselected bit line is precharged to the bit line by the precharged voltage and the SSL and GSL voltages. The source line CSL is electrically separated and the channel voltage is automatically boosted to Vcc or more by Vpass and Vpgm applied to the selected W / L while the channel is floating, and then the voltage is maintained in the channel. Therefore, tunneling from the bulk is prevented by the Vpgm and Vpass voltages applied to the selection word line W / L1.

As shown in Fig. 8C, the read operation for reading the data storage state of the cell is performed by applying a voltage of 1.0 V to B / L1, a Vcc voltage to SSL1 and unselected W / L and GSL, and a selection W to CSL and SSL2. If the voltage of 0V is applied to / L respectively, if Vth of the selected cell is programmed above 0V, there is no current flow of B / L through the cell, and if Vth is erased below 0V, Applying Vcc to SSL1 with Vth of + 1V and 0V to SSL2 with Vth of + 2V of the select transistor to generate B / L current through the select cell of the select string on the left side of the string sharing the bit line contact. It is sensed through a sense amplifier.

The implementation of a shared bit line cell using the above technique shows that two neighboring strings are connected through one bit line contact, thus facilitating the process in terms of bit line pitch density, bit line contact, and metal bit line formation. have.

However, in a shared bit line cell, compared to a single bit line cell array, the read current of the selected cell flows to the source line through the added string select transistor, thereby increasing the read current of the cell due to the increased select transistor. . As a result, the cell's ON operation is read as the OFF operation or the lead cell current margin is reduced in response to changes in the surrounding environment, such as at high temperatures, thereby degrading cell stability.

For example, when a single bit line cell is read, even when Vcc of SSL is + 1V, even though Vcc of about 5V is applied to the gate, the bit line voltage is sufficiently passed, but the threshold of -2V is shared in the shared bitline cell. Since 0V is applied to the gate of the transistor having the voltage Vth, the transistor's shutoff voltage (the maximum voltage delivered through the depletion transistor when the gate is 0V) is generally known to the body effect. This reduces the margin, which is within 1.5V, which can conduct the bitline voltage.

Moreover, when the Vth of the depletion transistor increases with process variation, or when the cell's high integration reduces the active width of the cell, increasing the bitline voltage to 1V or more to compensate for the reduced current. The above-mentioned problem acts as a more serious operation limitation.

9A to 9D are cross sectional views taken along line A-A 'of FIG. 6 for explaining a conventional method for manufacturing a flash memory cell.

Referring to FIG. 9A, after forming the n-well 13 in the p-type substrate 11, the pocket p-well 15 is formed in the n-well 13. Subsequently, the active region is defined by a conventional device isolation process, and the gate oxide film 22 of the thick film for the string select transistor is formed to a thickness of about 150 to 300 Å. Subsequently, the channel region of the string selection transistor SSL2 having the threshold voltage of − is defined using the photosensitive film PRI, and ion implantation for adjusting the threshold voltage is performed.

Referring to FIG. 9B, after the channel region of the memory cell transistor is defined using a predetermined photoresist pattern PR2, the exposed gate oxide film 22 is removed.

Referring to FIG. 9C, a tunneling oxide film 32 having a thickness of tens of micrometers capable of quantum mechanical tunneling is grown in a channel region of the limited cell, and then an accumulation gate in which a floating gate / ONO dielectric film / control gate is stacked is fabricated. Subsequently, a high concentration n-type impurity is implanted using the accumulation gate pattern as a mask to form a source / drain region. Finally, as shown in FIG. 9D, the interlayer insulating film 24 and the metal film 26 are interconnected to complete the fabrication of the cell array.

As described above, the conventional method is complicated because different mask patterns PR1 and PR2 are used to differentiate the threshold voltage of the string selection transistor from the initial threshold voltage of the cell transistor. In addition, during ion implantation for adjusting the threshold voltage of the channel region of the depletion type string selection transistor SSL2 Tr., The separation distance between the neighboring string selection line SSL and the memory cell (or word line) according to high integration of the cell. When the ion implantation impurity is small, the threshold voltage of the neighboring SSL1 or the memory cell transistor may be affected by the heat treatment of a subsequent process, and in this case, the mask for ion implantation may be further compared to a single bit line cell. Used.

Accordingly, the present invention provides a flash memory cell and a method for fabricating the same, which can improve read current reduction due to the additional use of a string select transistor in a shared bit line cell, and can simplify the process without using a mask. Its purpose is to.

The present invention for achieving the above object is a plurality of data storage memory cells consisting of a pair of transistors connected in series, the depletion and incremental transistors are connected in series to select at least one particular cell of these cells A ground select line, to which two string select lines and a ground select transistor are connected, is formed in a series circuit between a bit line and a source line to form one unit string, and the neighboring unit strings are one bit line. The gate insulating layer of the depletion type string selection transistor sharing a contact and connected through the same string selection line is formed to be thinner than the thickness of the gate insulating layer of the incremental string selection transistor.

Preferably, the gate insulating film of the depletion type string select transistor is made of a tunnel oxide (tunnel oxide) having a thickness capable of quantum mechanical tunneling.

In addition, the thickness of the gate oxide film of the memory cell transistor is preferably the same.

A feature of the present invention for achieving the above another object is to provide at least one memory cell array comprising the following steps.

(a) forming a gate oxide film in an active region of a semiconductor substrate on which pocket wells are formed

(b) using a single mask to simultaneously define the active region of the memory cell and the channel region of the depletion type string select transistor adjacent thereto, and then perform depletion ion implantation.

(c) forming a tunnel oxide film capable of quantum mechanical tunneling after removing the exposed gate oxide film

(d) forming an accumulation gate on the entire surface of the resultant, and then using this as a mask to form source / drain regions of each transistor;

(e) performing an interlayer insulating film and metal film wiring process on the entire surface of the resultant product;

According to another aspect of the present invention, there is provided a method of operating a shared bit line cell having the above-described configuration,

An operation method for reading the selection cell may include a read voltage for turning on a depletion type string select transistor among string select transistors connected to the string select lines, and a read voltage of the depletion type string select transistor. It is characterized by applying a voltage above the threshold voltage. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

10 is a plan view of a NAND flash memory cell having a shared bit line in accordance with the present invention, and FIG. 11 is an equivalent circuit diagram of FIG.

10 and 11, a memory cell according to the present invention comprises a plurality of data storage memory cells (QL1, WL2, ... WL6) consisting of a pair of incremental transistors connected in series, and among these cells. Two string select lines (SS1, SS2) in which a pair of depletion and incremental transistors are connected in series to select at least one particular cell, and a ground select transistor for fail relief in standby state. The connected ground select line GSL is constituted in series circuits between the bit line BL and the source line CSL to form one unit string.

The present invention having such a configuration has a shared bitline cell structure in which two cell strings adjacent in the wordline direction share one bitline contact and have improved design rules compared to a single bitline cell. The string select transistors for selecting any one of the two strings that share a? Are alternately arranged in a depletion type having a threshold voltage of '-' and an incremental type having a '+' value.

In addition, the threshold voltages of the string selection transistors connected in series to the two string selection lines SSL1 and SSL2 constituting one unit string, respectively, are composed of different values, that is, depletion type and increase type, and thus, There is no difference in shared bitline cell structure and planar layout.

The features of the present invention will be described with reference to the process sectional views shown in FIGS. 12A to 12D taken along the line AA ′ of FIG. 10.

Referring to FIG. 12A, after forming the n-well 13 in the p-type substrate 11, the pocket p-well 15 is formed in the n-well 13. Subsequently, the gate oxide film 42 of a thick film having a thickness of about 150 to 300 microseconds is formed on the entire surface of the exposed active region by limiting the active region by a conventional device isolation process. Subsequently, the depletion ion implantation is performed by defining the active region of the memory cell and the channel region of the string selection transistor SSL2 Tr. Adjacent thereto using the single mask pattern PR.

At this time, the depletion ion implantation is performed at 1.5-2.0 × 10 ¹² ions / cm 2, 50 KeV using n-type impurities such as arsenic (As) or phosphorus (P).

Referring to FIG. 12B, after wet etching the gate oxide layer 42 exposed by the mask pattern PR, quantum mechanical tunneling is performed on the memory cell region and the channel region of the selected string selection transistor SSL2 Tr. A tunnel oxide film 52 having a thickness of about several tens is formed as possible.

Referring to FIG. 12C, the active region of the memory cell in which the string select transistor SSL1 Tr. And the ground select transistor GSL Tr. And the tunnel oxide layer 52 in which the thick gate oxide layer 42 is grown is selected and selected. A floating gate polysilicon, an interpoly ONO dielectric layer, and a control gate polysilicon are sequentially stacked on the front surface of the string selection transistor SSL2 Tr. To form a accumulation gate.

Subsequently, a high concentration n-type impurity is implanted into each transistor using the accumulation gates as a mask to form a source / drain region. Finally, as shown in FIG. 12D, the wiring process between the interlayer insulating film 24 and the metal film 26 is performed to complete the fabrication of the cell array.

Unlike the conventional structure, the flash memory cell completed through the above process has a thinner thickness than the gate oxide layer of the increased select transistor when the threshold voltage is depleted among the transistors connected to the two string select lines SSL1 and SSL2. That is, it is composed of a tunnel oxide film having a quantum mechanical tunneling, and when the threshold voltage is increased, it is formed of a gate oxide film of a thick film as in the prior art.

This is to reduce the thickness of the gate oxide film so as to suppress the decrease in read current through the depletion type string select transistor added in the shared bit line cell. In addition, in the process, the addition of the mask can be prevented by performing the depletion ion implantation and the formation of the tunnel oxide film together using a single mask.

Hereinafter, a method of operating a memory cell according to the present invention will be described with reference to the timing charts of FIGS. 13A to 13C summarizing the schedules in each operation.

Referring to FIG. 13A, the erase operation for erasing electrons in the floating gate to make the threshold voltage of the cell at about -3V is the same as in the conventional method. That is, the erase voltage Vers of about 18V is applied to the bulk BULK in which the cell array is formed, and the same voltage as the erase voltage is applied or floated to the SSL1, SSL2, GSL, and unselected word lines, and the selected word line W is applied. When / L) is set to OV and the bit line and the source line are floated, the electrons in the floating gate are erased in bulk by the voltage induced across the tunnel oxide film about 90 degrees between the bulk and the floating gate of the selected cell.

Referring to FIG. 13B, a program operation of selectively injecting electrons into the floating gate of the cell to shift the threshold voltage of the cell to '+1 V' may be performed by selecting the selected cell (see FIG. 11) located in the right string of B / L2. Programming is described as an example.

First, Vcc is applied to all bit lines (B / L1, B / L2), Vcc is applied to SSL of the selected string and word lines in the selected string, and the selected string is shared with GSL, bulk, and CSL as OV. After voltage charging below Vcc is applied to the channel region of the cell to which the wordline is connected, 18V is applied to the select wordline (W / L2) and Vpass is lower than Vpgm and higher than Vcc to the unselected wordline in the select string. When a voltage is applied, the channel voltage of the cell increases above the precharge level to have a self boosting voltage.

In addition, if the SSL! Is set to OV and the selection bit line (B / L2) is set to OV to discharge only the boosting voltage of the channel region of the selection string to OV for programming, the channel voltage of the selection string is switched to the OV of B / L2. And electrons are injected from the bulk through the tunnel oxide into the floating gate by the Vpgm voltage applied to the selected word line.

At this time, the boosted channel voltage in the neighboring string sharing the word line reduces the potential difference with the Vpgm voltage of the word line to prevent the unwanted cell from being programmed, and the Vpass voltage applied to the unselected word line of the selected string is Lowering the Vpgm voltage also prevents unselected cells in the select string from being programmed.

Referring to FIG. 13C, the operation of reading a selection cell applies a read voltage of Vcc or more to SSL2 and GSL to increase Vcc or a read current to SSL2 and GSL for string selection, and to OV or more to SSL1. Applying Vx, a voltage of Vcc RAM that does not turn on the incremental string select transistor, increases the current and voltage that can flow to the source line through a string select transistor with a depletion threshold voltage of around -1V.

In addition, when the threshold voltage of the increased string select transistor is increased to 1V or more, the voltage applied to the gate of the depletion transistor may be further increased. At this time, the voltage applied to the gate of the unselected word line or the increased string select transistor at the time of read may be increased to Vcc or more so that the flow of current and voltage through the increased transistor is not restricted.

In addition, if Vcc or Vread voltage is applied to the unselected word line in the select string, OV is applied to the select word line, and 1 V is applied to the select bit line B / L2, current flows through the cell when the select cell is in a program state. If the cell is in an erased state, a bit line current is generated through the selected cell and the source line and read out through the sense amplifier.

As described in the above operation method, according to the present invention, when the read current of the cell decreases due to the reduced cell active width due to the high integration of the cell, the bit line voltage is increased to 1 V or more and the transistor of the string selection transistors is increased. After setting the threshold voltage of 1V or more, the voltage applied to the incremental string select transistor is set to Vread voltage of Vcc or higher and the voltage applied to the depleted string select transistor is also 1V or higher, so that the string select transistor with added bit line voltage or current It can be applied to highly integrated flash memory cells because it can not be limited by.

As described above, according to the present description, the thickness of the gate oxide film of the depletion type string select transistor is reduced to the thickness of the gate oxide film of the increase type string select transistor, thereby adding and increasing integration of a process mask, which is a problem in a conventional shared bit line cell. The reduction of the read current through the string select transistor can be solved. In addition, the cell string current can be increased by operating the read voltage applied to the string select transistor in the shared bit line cell above Vcc and OV at Vcc and OV.

Claims (7)

(Correction) a plurality of data storage memory cells comprising a pair of transistors connected in series, two string select lines in which depletion and increment transistors are connected in series to select at least one of the cells, and The ground select line to which the ground select transistor is connected is composed of a series circuit between a bit line and a source line to form a unit string, and the neighboring unit strings share a bit line contact. In a non-fly cell, The gate insulating layer of the depletion type string selection transistor connected through the same string selection line may be formed of a tunnel oxide thinner than the gate insulating film of the incremental string selection transistor and having a thickness capable of quantum mechanical tunneling. . 2. The flash memory cell of claim 1, wherein a thickness of the gate oxide layer of the memory cell transistor is equal to a thickness of the gate oxide layer of the depletion type string select transistor. 3. The flash memory cell of claim 2, wherein the gate structure of the memory cell transistor is a stating gate in which floating gates / ONO dielectric films / control gates are sequentially stacked to enable electrical rewriting. Forming a gate oxide film in an active region of a semiconductor substrate on which pocket wells are formed; Simultaneously defining the active region of the memory cell and the channel region of the depletion type string select transistor adjacent thereto using a single mask, and then performing depletion ion implantation; Removing the exposed gate oxide layer to form a tunnel oxide layer capable of quantum mechanical tunneling; Forming an accumulation gate on the entire surface of the resultant, and then using this as a mask to form source / drain regions of each transistor; And A method of fabricating a cell array, comprising the step of performing an interlayer insulating film and a metal film wiring process on the entire surface of the resultant product. The method of manufacturing a cell array according to claim 4, wherein the accumulation gate is sequentially stacked with a floating gate / ONO dielectric film / control gate to enable electrical reorganization. A plurality of data storage memory cells consisting of a pair of transistors connected in series. Deselective and incremental transistors are connected in series to select at least one of these cells, and two string select lines and a ground select line connected with a ground select transistor are connected in series with each other between the bit line and the source line. A method of operating a shared bitline cell configured to constitute one unit string, wherein the neighboring unit strings share one bitline contact. An operation method for reading the selection cell is an increase of OV or more adjacent to the depletion type string selection transistor to turn on a depletion type string selection transistor among the string selection transistors connected to the string selection lines. A neighboring depletion type is applied by applying a voltage having a value less than or equal to the threshold voltage of the type string select transistor as a read voltage, and applying a voltage equal to or greater than the threshold voltage of the increased string select transistor to turn on the incremental string select transistor. And operating the string select transistor at the same time. 7. The method of claim 6, wherein the read voltage for turning on the incremental string select transistor is greater than or equal to Vcc.