JPH10189781A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having an NAND type memory block in which gate disturb can be suppressed by reducing the voltage being applied to the word line of a nonselect memory cell at the time of reading, threshold voltage of the nonselect memory cell has no effect on the verify operation of a select memory cell and the threshold voltage Vth can be made narrower. SOLUTION: Each memory cell MC in a memory cell block is connected in parallel with a transistor and formed to cover a part of a channel forming region in the breadthwise direction of gate on each channel forming region. The transistor is formed in a region where the memory cell MC is not formed and a thin part is formed in an insulation layer between the memory cell MC and a semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a NAND nonvolatile semiconductor memory device in which a plurality of electrically rewritable storage elements are connected in series.

[0002]

2. Description of the Related Art A NAND-type nonvolatile semiconductor memory device in which a plurality of storage elements each having a charge storage layer are connected in series has a N
Although it has a drawback that random access is slower than an OR type nonvolatile semiconductor memory device, it is suitable for high integration because the area of a memory element per bit can be reduced.
A charge storage layer of a storage element of a NAND-type nonvolatile semiconductor storage device includes, for example, a floating gate or a MONO
S (Metal Oxide Nitride Oxide Semiconductor) type, M
A multilayer insulating film such as a NOS (Metal Nitride Oxide Semiconductor) type is used. Here, FIG. 13 and FIG.
FIG. 15 shows an example of the structure of a memory cell block of a NAND nonvolatile semiconductor memory device using a floating gate as a charge storage layer, and FIGS. 15 and 16 show a case where a multilayer insulating film is used as a charge storage layer. 1 shows an example of the structure of a memory cell block of a NAND nonvolatile semiconductor memory device.

FIG. 13 is a plan view of a floating gate type memory cell block, and FIG.
It is sectional drawing in the B 'line. As shown in FIGS. 13 and 14, diffusion layer regions 52 are formed at predetermined intervals in a storage element formation region partitioned by element isolation regions 51 such as LOCOS formed on a semiconductor substrate 58. A floating gate 56 is formed between the respective diffusion layer regions 52 via an insulating film 59, and a control gate 55 as a word line is formed on the floating gate 56 via an interpoly insulating film 60. .
That is, the floating gate 56 serves as a charge storage layer to constitute a memory cell. The memory cells are connected in series by sharing the diffusion layer region 52 with each other. The gate electrode located on the side of the bit contact 53 connected to the bit line is a selection gate 54.

FIG. 15 shows a MONOS (Metal Oxide).
FIG. 15 is a plan view of a (Nitride Oxide Semiconductor) type memory cell block, and FIG. 15 is a cross-sectional view taken along line BB ′ of FIG. As shown in FIGS. 15 and 16, an ONO film composed of an oxide film 61, a nitride film 62, and an oxide film 63 is formed as a charge storage layer, and the other structure is basically a floating gate type. Has the same structure as the nonvolatile semiconductor memory device of

[0005]

Here, FIG. 13 to FIG.
FIG. 17 shows an example of an equivalent circuit of the memory cell block of the nonvolatile semiconductor memory device shown in FIG. As shown in FIG. 17, the unit memory cell block of the NAND nonvolatile semiconductor memory device includes a plurality (eight in this case) of memory cells MC1 to MC8 between the select transistors TR1 and TR2.
Are connected in series, and the selection transistors TR1, TR1
2 is connected to the bit line BL and the source line SRL, respectively.

In such a read operation in the memory cell block, for example, when the memory cell MC5 is selected, a voltage of 0 V is applied to the word line WL5 of the selected memory cell MC5, and the word line W of the non-selected memory cell is selected.
A voltage for turning on each non-selected memory cell is applied to L1 to WL4 and WL6 to WL8. Then, it is determined whether or not a current flows through the word line WL5 of the selected memory cell MC5 at this time.

At the time of reading the selected memory cell MC5, the unselected memory cells MC1 to MC4, MC6 to MC8
Are voltages applied to the word lines WL1 to WL4, WL6 to WL8 of the unselected memory cells functioning as pass transistors.
The voltage must be sufficiently higher than the highest threshold value of C8. For example, FIG. 18 shows an example of the distribution of the threshold voltage Vth in the case of using a multi-level technique for storing two bits, that is, four values, in one memory cell in a floating gate type memory cell. Reference numeral 19 indicates the distribution of the threshold voltage Vth in the MONOS type memory cell. In FIG. 18, the word lines WL1 to WL4, W
The voltage to be applied to L6 to WL8 is, for example, 5V,
In FIG. 19, for example, it is 2.5V. For this reason, there is a problem that the gate disturbance of each memory cell increases and the reliability of the nonvolatile semiconductor memory device decreases.

In addition, the NAND type memory cell has a problem in that the threshold voltage Vth of the non-selected memory cell affects the verify operation of the selected memory cell due to its structure. That is, when data is written to another memory cell in the memory cell block after that, the cell current decreases when the verify check is completed and the writing is completed. May appear to rise. This has led to an increase in the spread of the threshold distribution. In particular, when a floating gate type memory cell is used as a multi-valued memory cell, it is necessary to control the distribution of the threshold voltage Vth at a fine level, and to narrow the distribution of the threshold voltage Vth. was there.

The present invention has been made in view of such a conventional problem. In a nonvolatile semiconductor memory device having a NAND-type memory cell block, a non-selected memory cell is connected to a word line at the time of reading. The applied voltage can be reduced, and gate disturbance can be reduced.
It is an object of the present invention to provide a nonvolatile semiconductor memory device in which a threshold voltage of an unselected memory cell does not affect a verify operation of a selected memory cell and a threshold voltage Vth can be narrowed.

[0010]

The present invention relates to a nonvolatile semiconductor memory device having at least one memory cell block in which a plurality of storage elements each having a charge storage layer are connected in series,
A transistor is connected in parallel to each storage element of the memory cell block, and each storage element is formed via a diffusion layer region formed at a predetermined interval in a storage element formation region of a semiconductor layer. The charge storage layer is formed so as to cover a part of the channel formation region in a gate width direction on each channel formation region formed between each diffusion layer region of the semiconductor layer, The transistor is formed in a region where the charge storage layer is not formed on each channel formation region, and an insulating film between the charge storage layer and the semiconductor layer has a reduced thickness. A part is formed.

[0011] Thus, when the transistor connected in parallel to the non-selected storage element is turned on during the read operation of the NAND type memory cell block, it is not necessary to use the non-selected storage element as a pass transistor. Disturb is reduced. Further, in the unselected storage element, the current of the transistor connected in parallel becomes dominant, so that the unselected storage element does not affect the verify operation of the selected storage element. Further, when the gate electrode is shared by the transistor and the storage element, if the threshold voltage of the transistor is set lower than the threshold voltage of the storage element, gate disturb during reading is reduced. In addition, when the charge storage layer is formed and is misaligned with the position of the charge storage layer, the potential of the charge storage layer is expected to vary,
In the present invention, by partially reducing the thickness of the insulating film between the semiconductor layer and the charge storage layer, the potential of the charge storage layer does not vary and the writing / erasing speed does not vary.

The present invention is a nonvolatile semiconductor memory device having at least one memory cell block in which a plurality of storage elements each having a charge storage layer and capable of storing three or more values are connected in series. Each storage element in the block has
Transistors are respectively connected in parallel, each of the storage elements is formed via a diffusion layer region formed at a predetermined interval in a storage element formation region of a semiconductor layer, and the charge storage layer is In the gate width direction on each channel formation region formed between each diffusion layer region of the layer, the transistor is formed so as to cover a part of the channel formation region. The threshold voltage of each transistor is formed in a non-formation region of the storage layer, and the threshold voltage of each transistor is the highest threshold voltage and the second highest threshold voltage among the plurality of threshold voltages of the storage element. Between the voltage.

That is, by setting the threshold voltage of each transistor between the highest threshold voltage and the second highest threshold voltage among the plurality of threshold voltages of the storage element, Gate disturb in the multi-level memory at the time of reading is reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the nonvolatile semiconductor memory device of the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a plan view showing a first embodiment of a memory cell block of a nonvolatile semiconductor memory device of the present invention, and FIG. 2 is a memory cell block of the nonvolatile semiconductor memory device of FIG. A
It is sectional drawing in the -A 'line. The memory cell block shown in FIGS. 1 and 2 is obtained by connecting floating gate type memory cells in series. In this embodiment, a case where a floating gate type memory cell is used as a multi-level memory cell will be described.

That is, on the silicon substrate 8,
For example, a diffusion layer region 1 is formed at a predetermined interval in a memory cell formation region partitioned by an element isolation region 2 formed by the LOCOS method or the like. _A floating gate 6 made of, for example, polysilicon is formed via an insulating film 9 made of an oxide film such as ₂ .

The floating gate 6 is formed so as to cover a part of the channel formation region in the gate width direction on each channel formation region formed between each diffusion layer region formed on the silicon substrate 8. That is, one side of the floating gate 6 is formed so as to ride on the element isolation region 2. A control gate 5 made of polysilicon is formed as a word line on the floating gate 6 and the insulating film 9 via the insulating film 10.

As shown in FIG. 2, a memory cell is formed in a region B covered by the floating gate 6, and a control gate 5 is directly formed on a channel forming region of a silicon substrate 8 via an insulating film 9. In the formed area A,
A transistor will be formed. The memory cell and the transistor are connected in parallel because the diffusion layer region 1 serving as the source / drain is shared. In the insulating film 9, a tunnel window 9 a which is a thinned portion is formed between the silicon substrate 8 and the floating gate 6.

The threshold voltage Vth of each memory cell is distributed, for example, as shown in FIG. 4, and the threshold voltage Vth of each transistor is equal to the threshold voltage Vth of the memory cell. It is between the highest threshold voltage and the second highest threshold voltage, for example, 3.0 V.

The threshold voltage Vth of the memory cell and the transistor is set in each diffusion layer region 1 in the silicon substrate 8.
Can be arbitrarily set by adjusting the impurity concentrations of the region corresponding to the memory cell and the region corresponding to the transistor when the impurity is formed by ion implantation of impurities.

On the other hand, the memory cells formed as described above are connected in series by sharing the diffusion layer region 1 with each other to form a memory cell block. At one end of the diffusion region 1, the control gate located on the side of the bit contact 3 connected to the bit line is the selection gate 4, and the selection transistor TR1 is formed. Similarly, a select gate (not shown) is formed at the other end to form a select transistor TR2.

Here, an example of an equivalent circuit of the memory cell block shown in FIGS. 1 and 2 is shown in FIG. As shown in FIG. 3, the unit memory cell block of the NAND nonvolatile semiconductor memory device has n memory cells MC1 to MCn connected in series between select transistors TR1 and TR2 having word lines SL1 and SL2. Along with
The transistors PTR1 to PTRn are connected in parallel to the memory cells MC1 to MCn. The selection transistors TR1 and TR2 are connected to the bit line BL and the source line SRL, respectively.

Hereinafter, based on the equivalent circuit shown in FIG.
A read operation of the nonvolatile semiconductor memory device according to the embodiment will be described. For example, when the memory cell MC5 is selected as a memory cell to be read, the voltage of the word line WL5 which is the control gate 6 of the memory cell MC5 is set to, for example, 0V,
The voltage is sequentially changed to 1.5 V and 2.8 V to change the memory cell MC.
It is determined which threshold voltage Vth distribution is based on whether or not 5 is turned on.

At this time, all of the select transistors TR1 and TR2 and the transistor PTR connected in parallel to the unselected memory cell MC from which no reading is performed are turned on.
I do. Here, the threshold voltage Vth of the transistor PTR formed in parallel is, as shown in FIG. 4, between the uppermost distribution and the second distribution of the threshold voltage Vth distribution of the memory cell MC. 3V, the unselected word line W
When a voltage of about 3.5 V is applied to all L, the transistor PTR connected in parallel to the non-selected memory cell MC is turned on regardless of whether the non-selected memory cell MC is on or off. Note that the voltage of the selected word line WL5 is set to 0V,
Even if the voltages are sequentially changed to 1.5 V and 2.8 V, the transistor PTR5 connected in parallel to the selected memory cell MC5 is turned off.
It remains in the F state.

As a result, when the selected memory cell MC5 is turned on at one of the voltages 0V, 1.5V, and 2.8V, the bit line BL is connected in parallel with the unselected memory cell MC through the selection transistor TR1. Connected transistors PTR1 to PTR4, selected memory cell MC5,
A current flows to the source line SRL through the unselected memory cells MC6 to MCn and TR2, and it is possible to determine which threshold voltage Vth distribution the memory cell MC5 has.

Therefore, in the present embodiment, it is not necessary to set the potential of the word line WL of the unselected memory cell MC higher than the uppermost distribution of the threshold voltage Vth (for example, about 5 V), and it is lower than the conventional case. It is possible to set. For this reason, gate disturb when a high voltage is applied to the word line WL of the non-selected memory cell MC can be suppressed, so that the reliability of the nonvolatile semiconductor memory device can be increased. Further, since the current of the non-selected memory cell MC is dominated by the current of the transistor PTR formed in parallel, the threshold voltage Vth of the non-selected memory cell MC has little effect on the verify operation of the selected memory cell MC5. As a result, it is possible to narrow the distribution of the threshold voltage Vth as compared with the related art. When the threshold voltage Vth can be narrowed, the voltage of the word line WL of the unselected memory cell MC at the time of reading can be further reduced, so that the gate disturbance can be further reduced.

In a floating gate type memory cell, when the position of the floating gate 6 is misaligned when the floating gate 6 is formed,
It is expected that the area of the insulating film 9 varies, the capacitance coupling ratio with the insulating film 10 changes, and the potential of the floating gate 6 varies. Therefore, the amount of charge injected into each floating gate 6 under the same bias condition may vary, and the writing / erasing speed may vary.

However, in the present embodiment, since the tunnel window 9a in which the insulating film 9 is partially thinned is formed, it is not affected by the misalignment of the floating gate 6, so that the write operation is not performed. -Erasing speed does not vary.

Second Embodiment FIG. 5 is a plan view showing a memory cell block of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, and FIG. 6 is a sectional view of the memory cell block taken along line AA '. It is.
The difference between the memory cell block of the present embodiment and the memory cell block of the first embodiment is the formation position of the floating gate 6. In other words, the floating gate 6 is formed at a substantially central position in the gate width direction on each channel formation region formed between the diffusion layer regions 1 with a width smaller than the width of the channel formation region. For this reason,
The floating gate 6 is formed so as to cover only the central portion of the channel region without covering the entire surface of the channel region, and a memory cell is formed in the region B of the channel region.
The transistors connected in parallel to the memory cell are formed in two regions A1 and A2 of the channel region, and the memory cell and the two transistors are formed in parallel.

Further, as in the first embodiment, the insulating film 9 has a tunnel window portion 9a which is a thinned portion between the silicon substrate 8 and the floating gate 6, which is a thinned portion. ing.

With the above configuration, even if the floating gate 6 is misaligned with the channel forming region in the lithography process, the floating gate 6 is formed at a substantially central position on the channel forming region, Since the portion is not in contact with the element isolation region 2, the capacitance coupling ratio between the area of the insulating film 9 and the insulating film 10 does not change. Therefore, the potential of the floating gate 6 does not vary, the amount of charge injected into each floating gate 6 does not vary, and there is no variation in the writing / erasing speed.

In this case, since the area of the insulating film 9 and the area of the insulating film 10 are almost the same, the capacitance coupling ratio becomes very small, and there is a concern that the voltage at the time of writing / erasing must be increased. . However, since the tunnel window 9a, which is a thinned portion, is formed, the capacitance coupling ratio can be increased, so that the voltage at the time of writing / erasing can be reduced.

Further, even if the position of the floating gate 6 is misaligned, the floating gate 6 is formed at a substantially central position on the channel forming region, and the end is not in contact with the element isolation region 2. Since there is no variation in the storage capacitance and the sum of the gate widths of the two transistors formed on both sides is always equal, the amount of current of the transistors does not vary and does not affect the verify operation. Note that the equivalent circuits of the memory cell blocks shown in FIGS. 5 and 6 are the same as those of the first embodiment, and the read operation is also the same, so that the description will be omitted.

Third Embodiment FIG. 7 is a plan view showing a first embodiment of the memory cell block of the nonvolatile semiconductor memory device of the present invention, and FIG. 8 is a memory cell block of the nonvolatile semiconductor memory device of FIG. A
It is sectional drawing in the -A 'line. The memory cell blocks shown in FIGS. 7 and 8 are MONOS type memory cells connected in series. In the present embodiment, the MON
A case where an OS-type memory cell is used as a binary memory cell will be described.

7 and 8, the silicon substrate 8
(A P-type substrate or a P-type well is usually used because an NMOS is used for a memory transistor.) A first insulating film 11 made of an oxide film of about 2 nm and a first insulating film 11
A multilayer insulating film including a second insulating layer 12 serving as a charge storage layer and a third insulating film 13 formed of an oxide film of about 4 nm is formed so as to be in contact with the element isolation region 2. The multilayer insulating film including the first insulating film 11, the second insulating film 12, and the third insulating film is provided in a gate width direction on each channel forming region formed between the respective diffusion layer regions 1 of the silicon substrate 8. It is formed so as to cover a part of the channel formation region. As a result, a MONOS type memory cell is formed. An insulating film 9 is formed adjacent to the side of the multilayer insulating film, and a control gate 5 is formed so as to cover the multilayer insulating film and the insulating film 9. Thus, a transistor connected in parallel with the MONOS type memory cell is formed.

The MONOS type memory cell described above utilizes the fact that the threshold voltage Vth of the memory cell (memory transistor) changes according to the amount of charge stored in the second insulating layer 12 made of a nitride film. By doing so, the upper part is memorized. The second insulating layer 12 often uses SiN, and retains electric charge by trapping electrons in the film. For writing at low voltage, the film thickness is 10 nm
The following are used:

On the other hand, the memory cells formed as described above are connected in series by sharing the diffusion layer region 1 with each other to form a memory cell block. At one end of the diffusion region 1, the control gate located on the side of the bit contact 3 connected to the bit line is the selection gate 4, and the selection transistor TR1 is formed. Similarly, a select gate (not shown) is formed at the other end to form a select transistor TR2.

The equivalent circuit of the memory cell block configured as described above is the same as that shown in FIG. 3 as the equivalent circuit of the first and second embodiments. Next, a read operation of a memory cell block in which a transistor is connected in parallel to such a MONOS type memory cell will be described with reference to an equivalent circuit shown in FIG.

Here, the distribution of the threshold voltage Vth of the MONOS type memory cell MC is, for example, as shown in FIG. At this time, the threshold voltage Vth of the transistor PTR formed in parallel with the memory cell MC is lower than the higher threshold voltage Vth distribution of the memory cell MC. In this case, for example, it is set to 0.5V. I have.

For example, when the memory cell MC5 is selected as a memory cell to be read, the voltage of the word line WL5 which is the control gate 6 of the memory cell MC5 is set to 0V.
"1" or "0" is determined depending on whether or not the memory cell MC5 is turned on. At this time, the select transistors TR1 and T
R2, and unselected memory cells M that do not perform reading
Turn on all the transistors PTR connected in parallel to C. When a voltage of about 1.5 V is applied to the unselected word lines WL, the transistors PTR formed in parallel are turned on regardless of whether the memory cells are on or off. The transistor PTR connected in parallel to the selected memory cell MC5
5 remains OFF.

Thus, the selected memory cell MC5
Is turned on, the bit line BL switches the selection transistor TR
1, the transistors PTR1 to PTR4 connected in parallel to the unselected memory cell MC, and the selected memory cell M
C5, unselected memory cells MC6 to MCn and TR2
Current flows to source line SRL through memory cell MC
It is possible to determine whether 5 holds data “1” or “0”.

If there is no transistor PTR connected in parallel, the memory cell MC in which "0" data is written
It is necessary to set the threshold voltage to a sufficiently higher value, for example, 2.5 V, than the threshold voltage Vth distribution (the higher threshold distribution). However, according to the present embodiment, the memory cell MC
The transistor PTR is connected in parallel with the memory cell MC, and its threshold voltage Vth is set lower than the higher threshold voltage Vth distribution of the memory cell MC. Can be set low, so that gate disturb is less likely to occur and reliability can be improved.

Further, the NAND type memory cell block has a problem in that the threshold value of the non-selected memory cell affects the verify operation of the selected cell.
That is, based on the time when the verification is passed and the writing is completed, if data is subsequently written to another cell in the NAND string, the cell current becomes smaller, so that the threshold value seems to rise at the time of reading. Looks like.
This has led to an increase in the spread of the threshold distribution.

However, according to the present embodiment, since the current of the non-selected memory cell is dominated by the current of the transistor formed in parallel, the threshold value of the non-selected memory cell affects the verify operation of the selected memory cell. Nothing. Therefore, it is possible to narrow the threshold distribution more than before,
The margin can be increased, or the word line voltage of a non-selected memory cell at the time of reading can be further reduced to reduce gate disturb.

Fourth Embodiment FIG. 10 is a plan view showing a first embodiment of a memory cell block of a nonvolatile semiconductor memory device according to the present invention.
FIG. 11 is a cross-sectional view of the memory cell block of the nonvolatile semiconductor memory device of FIG. 10 taken along line AA ′. The difference between the memory cell block of the present embodiment and the memory cell block of the third embodiment is the formation position of the multilayer insulating film including the first insulating film 11, the second insulating film 12, and the third insulating film 13. .

That is, the multilayer insulating film is formed in each diffusion layer region 1
At a substantially central position in the gate width direction on each of the channel formation regions formed therebetween, the width is smaller than the width of the channel formation region. Therefore, the multilayer insulating film is formed so as to cover only the central portion of the channel region without covering the entire surface of the channel region, and the memory cell is formed in the region B of the channel region. Further, the transistors connected in parallel to the above-mentioned memory cells include the channel regions A1 and A2.
And the memory cell and the two transistors are formed in parallel. Note that the equivalent circuits of the memory cell blocks in FIGS. 10 and 11 are the same as those in the above embodiment, and are as shown in FIG. The read operation is the same as that of the third embodiment, and the description is omitted.

Since the multilayer insulating film in the third embodiment is formed at a position in contact with the element isolation region 2, if misalignment occurs in the lithography step, the area of the multilayer insulating film will vary, and the memory cell size will be reduced. The threshold may vary. In addition, since the gate widths of the transistors formed in parallel also vary, the current amount of the pass transistor varies, which may affect the verify operation.

However, in the present embodiment, when forming a multilayer insulating film composed of the first insulating film 11, the second insulating film 12, and the third insulating film 13, the multilayer insulating film is formed only in the central portion of the channel region. Even if the position of the insulating film is misaligned, the area of the multilayer insulating film does not vary, and the threshold voltage Vth of the memory cell does not vary. Further, the total length of the gate width of the two transistors formed in parallel is always constant, so that the current amount of the transistors varies and does not affect the verify operation.

Further, the memory cell according to the present embodiment
Since the end is not formed at a position in contact with the element isolation region 2, incomplete writing and erasing at the end of the multilayer insulating film including the first insulating film 11, the second insulating film 12, and the third insulating film 13 are prevented. Can be avoided.

[0050]

As described above, according to the present invention, at the time of reading from each storage element of a memory cell block in which a plurality of storage elements each having a charge storage layer are connected in series, the word of an unselected storage element is read. It is not necessary to set the potential of the line higher than the top distribution of the threshold voltage, and it is possible to set the line potential lower than in the conventional case. Therefore, when a high voltage is applied to the word line of the non-selected storage element, Since gate disturbance can be suppressed, the reliability of the nonvolatile semiconductor memory device can be increased.

Since the current of the non-selected storage element is dominated by the current of the transistors formed in parallel, the threshold voltage of the non-selected storage element has little effect on the verify operation of the selected storage element. . As a result,
The band width of the threshold voltage distribution can be narrowed, and the gate disturbance can be further reduced.

In the present invention, since the insulating film of the floating gate type storage element is partially thinned, it is not affected by misalignment of the floating gate. Will not occur.

Further, according to the present invention, each storage element is formed at a substantially central position in the gate width direction on each channel formation region with a width smaller than the width of the channel formation region, and the transistors connected in parallel are formed. Since it is formed on both sides of the storage element forming position, even if the storage element is misaligned, the area of the charge storage layer of the storage element does not vary, and the threshold voltage of the storage element is reduced. Variation does not occur. Also, the total length of the gate width of the two transistors formed in parallel is always constant,
The amount of current of the transistor is constant, and does not affect the verify operation.

Further, according to the present invention, each storage element is formed at a substantially central position in the gate width direction on each channel formation region with a width smaller than the width of the channel formation region, and the transistors connected in parallel are formed. Since it is formed on both sides of the storage element formation position and the end is not formed at a position in contact with the element isolation region, incomplete writing and erasing at the end of the charge storage layer can be avoided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a cross-sectional view taken along line AA ′ of the nonvolatile semiconductor memory device of FIG.

FIG. 3 is an equivalent circuit diagram of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2;

FIG. 4 is a diagram showing an example of a distribution of threshold values of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 5 is a plan view showing a second embodiment of the nonvolatile semiconductor memory device of the present invention.

6 is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 5 taken along line AA ′.

FIG. 7 is a plan view showing a third embodiment of the nonvolatile semiconductor memory device of the present invention.

8 is a cross-sectional view of the nonvolatile semiconductor memory device of FIG. 7 taken along line AA '.

9 is a diagram showing an example of a distribution of threshold values of the nonvolatile semiconductor memory device of FIG. 7;

FIG. 10 is a plan view showing a fourth embodiment of the nonvolatile semiconductor memory device of the present invention.

11 is a cross-sectional view of the nonvolatile semiconductor memory device of FIG.
It is sectional drawing in a line.

FIG. 12 is a plan view showing an example of the structure of a NAND nonvolatile semiconductor memory device.

FIG. 13 is a cross-sectional view of the nonvolatile semiconductor memory device of FIG.
It is sectional drawing in a line.

FIG. 14 is a plan view showing another example of the structure of the NAND nonvolatile semiconductor memory device.

FIG. 15 is a cross-sectional view of the nonvolatile semiconductor memory device of FIG.
It is sectional drawing in a line.

FIG. 16 is an equivalent circuit diagram of the nonvolatile semiconductor memory device shown in FIGS. 12 to 15;

17 is a diagram illustrating an example of a distribution of threshold values of the nonvolatile semiconductor memory device of FIG. 12;

18 is a diagram illustrating an example of a distribution of threshold values of the nonvolatile semiconductor memory device of FIG. 14;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Diffusion layer area, 2 ... Element isolation area, 3 ... Bit line contact, 4 ... Select gate, 5 ... Control gate, 6 ... Floating gate, 8 ... Silicon substrate, 9 ... Insulating film, 9a
... Tunnel window, 10 ... Insulating film, 11 ... First insulating film, 1
2 ... second insulating film, 13 ... third insulating film.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115

Claims (11)

[Claims] 1. A nonvolatile semiconductor memory device having at least one memory cell block in which a plurality of storage elements each having a charge storage layer are connected in series, wherein each storage element of the memory cell block includes a transistor. The storage elements are connected in parallel, and each of the storage elements is formed via a diffusion layer area formed at a predetermined interval in a storage element formation area of a semiconductor layer, and the charge storage layer is each of the semiconductor layers. In the gate width direction on each channel formation region formed between the diffusion layer regions, the transistor is formed so as to cover a part of the channel formation region. A non-volatile semiconductor formed in a non-formation region, wherein a thinned portion having a reduced thickness is formed in an insulating film between the charge storage layer and the semiconductor layer;憶 apparatus. 2. The semiconductor device according to claim 1, wherein each of the storage elements is formed via a diffusion layer region formed at a predetermined interval in a storage element formation region of a semiconductor layer. A width smaller than a width of the channel formation region at a substantially central position in a gate width direction on each channel formation region formed between the layer regions; and the transistor is formed on both sides of a position where the charge storage layer is formed. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is formed. 3. The storage device and the transistor,
2. The nonvolatile semiconductor memory device according to claim 1, wherein said diffusion layer region is shared between adjacent storage elements and transistors. 4. The nonvolatile semiconductor memory device according to claim 1, wherein each of said charge storage layers and each of said transistors connected in parallel to each other share a gate electrode of each other. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage layer is a floating gate formed on said semiconductor layer via an insulating film. 6. The nonvolatile semiconductor memory device according to claim 1, wherein said charge storage layer comprises a multilayer insulating film. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a threshold voltage of said transistor is lower than a threshold voltage of a storage element having said charge storage layer. 8. A nonvolatile semiconductor memory device having at least one memory cell block in which a plurality of storage elements each having a charge storage layer and capable of storing three or more values are connected in series, wherein: A transistor is connected to each storage element in parallel, and each storage element is formed via a diffusion layer region formed at a predetermined interval in a storage element formation region of a semiconductor layer, The charge storage layer is formed so as to cover a part of the channel formation region in a gate width direction on each channel formation region formed between the respective diffusion layer regions of the semiconductor layer. A threshold voltage of each of the transistors is formed in a non-formation region of the charge storage layer over a channel formation region; The nonvolatile semiconductor memory device that is between the high threshold voltage and a high threshold voltage to the second well. 9. Each of the storage elements is formed via a diffusion layer region formed at a predetermined interval in a storage element formation region of a semiconductor layer, and the charge storage layer is formed by a diffusion layer of the semiconductor layer. A width smaller than a width of the channel formation region at a substantially central position in a gate width direction on each channel formation region formed between the layer regions; and the transistor is formed on both sides of a position where the charge storage layer is formed. 9. The non-volatile semiconductor storage device according to claim 8, wherein the non-volatile semiconductor storage device is formed as follows. 10. The nonvolatile semiconductor memory device according to claim 8, wherein each of said storage elements and each of said transistors share said diffusion layer region between adjacent storage elements and transistors. 11. The nonvolatile semiconductor memory device according to claim 8, wherein each of said charge storage layers and each of said transistors connected in parallel to each other share a gate electrode.