KR100190014B1 - Eeprom semiconductor memory apparatus - Google Patents

Abstract

Disclosed is a 3-bit shared flash memory cell that shares three bit lines and can maintain the same cell area as in the prior art. According to the present invention, a plurality of string selection transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection transistors for fail relief in a standby state are provided with a bit line and a ground. The unit circuits are configured in series circuits between voltage terminals to form one unit string. The three neighboring unit strings share one bit line contact and are connected to each unit string through the same string select line. Threshold voltages of the string select transistors connected to each other are formed by repeating three different values.

Description

Nonvolatile Semiconductor Memory Device

1 is a plan view of a conventional single bit NAND flash memory cell.

2 is an equivalent circuit diagram of FIG.

FIG. 3 is a table summarizing the memory cell operating voltages of FIG.

4 is a plan view of a NAND type flash memory cell having a conventional shared bit line.

5 is an equivalent circuit diagram of FIG.

6A through 6C are timing diagrams summarizing each operation schedule of the memory cells of FIG.

7 is a plan view of a NAND flash memory cell according to the present invention.

8 is an equivalent circuit diagram of FIG.

9A and 9B are timing charts summarizing each operation schedule of a memory cell according to the present invention.

The present invention relates to a nonvolatile memory device, and more particularly to a memory cell sharing three bit lines.

Non-volatile memory capable of electrically storing and erasing data generally forms a unit cell in a stacked structure of a floating gate and a control gate, and a plurality of cells are connected to a plurality of bit lines, word lines, and source lines. Bit lines, word lines, and source lines are formed at regular intervals to form a cell array.

In particular, an array of NAND flash EEPROMs in which a plurality of word lines exist between a bit line and a source line includes a bit line and a source line select transistor for connecting the bit line and the source line to a unit cell. A plurality of unit cells form a unit string in series and connect each source / drain, and a plurality of unit strings are connected in parallel to a bit line.

This conventional structure is contained in a paper entitled A 4-Mbit NAND EEPROM with tight programmed vt distribution, published in 1990 Symposium on VLSI circuits, pp. 105-106. , pp. 128-129, A 3.3V 32Mb nand flash memory with incremental step pulse programming scheme.

1 is a layout of a NAND flash memory cell described in the paper, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is an erase, program and read selection cell in an equivalent circuit of FIG. When reading, the table summarizing the operating voltage of each node.

Referring to the drawings, the cell operation is as follows.

The erase operation, which erases the electrons in the floating gate and stores the holes to set the cell's threshold voltage to -3V, applies a 0V voltage across all word lines of the string containing the selected cell and 20V for bulk, GSL, and SSL. The internal and external erase voltages are applied respectively, and the bit lines, source lines, and word lines of the unselected strings are floated, so that the electrons in the floating gates are caused by the erase voltage applied to the bulk of the selected cell and the 0V voltage applied to the word line. It is erased in bulk through a thin tunneling oxide layer of around 100 microseconds formed between the silicon.

The program operation of injecting electrons into the floating gate of the selected cell to move the threshold voltage of the cell (hereinafter referred to as Vth) to + 1V is confused by stress when the cell connected to the selected word line and the unselected bit line is programmed. There is a method of applying a constant voltage (Vpi) of Vcc or more to an unselected bit line, and a method of self boosting the Vpi voltage. The latter method is described in FIG. .

The program first applies Vcc to all bit lines and selected SSL, 0V to SSL and bulk, and Vpgm to select word lines and Vpgm and Vcc to unselected word lines to automatically boost a constant voltage across all cell channels. Vpss) is applied. When such a voltage is applied, the channel region electrically separated from the bit line and the source line by the SSL and GSL voltages is automatically boosted to a constant voltage of Vcc or more by the word line voltage, and then the select cell with the select bit line as 0V. Only the cells of the word line to which Vpgm is applied by discharging the channel voltage of the included string to 0V, the electron tunnels the oxide film from the bulk to the floating gate by the voltage difference in the opposite direction to the erase between the floating gate and the bulk silicon. Is injected.

At this time, the channel voltage of the cell connected to the selected word line and the unselected bit line is not boosted during the program time because a discharge path through the bit line is not formed by the Vcc and SSL Vcc voltages applied to the unselected bit line. Even if Vpgm is applied to the word line, the voltage difference with the floating gate is reduced by the bulk voltage, thereby preventing tunneling of electrons through the tunnel oxide, thereby preventing the programming of unwanted cells.

On the other hand, the read operation for reading the stored data of the cell is performed by applying the selected word line, the common source and the bulk to 0V, applying the Vcc to the non-selected word line, SSL and GSL and 0.7V to the selected line, respectively. If Vth is 0V or less and erased, current flows through the cell. If Vth is 0V or more, the selected cell is programmed to determine the cell state through the sense amplifier.

Due to the above-described improved cell operation and the reduction of the active pitch due to the recent high integration of cells, the typical layout structure of the conventional single bit line NAND flash described above is a unit string cell having one bit line and one bit line. It is connected via a line contact. As a result, the active region of the string and the contact overlap region of the metal for the contact and the bit line form one pitch of the cell as shown in a planar layout shown in FIG. .

In order to overcome this problem, a complicated modified process using a poly pad layout for a contact region is required instead of a general metal process, which causes a problem such as adding a process step.

To overcome this limitation, a shared bit line cell technology that shares one bit line of two neighboring strings is disclosed in U.S. Patent No. 4,962,481. It is listed in TRANSISTORS CONNECTED IN SERIES. However, in the above-described technique, the cell operation is different from the prior art, in which the electrons are discharged from the floating gate of the cell to the drain of the cell through the tunnel oxide during programming. It works by injecting electrons in the floating gate through the oxide.

This shared bit line structure, as shown in the cell layout of FIG. 4, adds one SSL to the existing single bit line cell, which is for selecting one of two strings that share a bit line contact. Each of the two string select transistors Vth connected to the two SSLs is configured differently.

That is, as shown in the equivalent circuit diagram of FIG. 5, when Vth of the left transistor of SSL1 is 1V, Vth of the neighboring right select transistor of the same SSL is set to -2V. In addition, Vth of the left transistor of SSL2 was -2V and Vth of the right transistor was + 1V.

In addition, the ground select line (GSL), which is not used in the conventional shared bit line, is applied as a single bit line cell for improved cell operation.

The operation of the memory cell having such a configuration will be described with reference to FIGS. 6A to 6C which summarize each operation scale of the selected cell.

First, an erase operation will be described with reference to FIG. 6A, which shows a timing diagram during an operation of erasing a selected cell (in FIG. 5, 'A').

An erase voltage of about 20V is applied to the bulk and an erase voltage is applied to SSL and GSL to prevent the gate oxide from being destroyed by eliminating the voltage difference between the bulk and the gate. The word line of the selection string is 0V, the word line of the non-selection string is floating, and electrons in the floating gate are discharged through the bulk due to the voltage difference between the selection word line and the bulk. As a result, it is moved to Vth -3V of the cell.

Referring to FIG. 6B, which shows a timing diagram during program operation, the program first applies Vcc to B / L and SSL1 and SSL2, and applies a Vpss voltage higher than Vcc or Vcc and lower than Vpgm to B / L and B. The voltage applied to / L is precharged to the cell channel. Subsequently, when voltages of Vpgm are selected to the selected W / L, 0 V to the SSL2, and 0 V to the B / L1 are sequentially applied, the precharge voltage induced in the selected cell channel is discharged through the B / L to maintain 0 V, and W By Vpgm of about 18V applied to / L, electrons are injected from the bulk into the floating gate through the tunnel oxide, thereby changing the cell Vth to 1V.

At this time, the erase cell connected to the selected W / L of the unselected B / L is stressed, but the cell channel connected to the unselected bit line is precharged to the B / L and C / S lines by the SSL and GSL voltages. The voltage is maintained on the channel during the program time after the channel voltage is automatically boosted to Vcc or higher by Vpss and Vpgm applied to the selected W / L while the channel is floating. Therefore, tunneling from bulk is prevented by the Vpgm and Vpss voltages applied to the W / L.

The read operation for reading the data storage state of the cell applies a voltage of 0.7 V to B / L, a Vcc voltage to SSL1 and unselected W / L and GSL, and a 0 V voltage to CSL, SSL2 and select W / L, respectively. If Vth of the selected cell is programmed to be 0V or more, there is no current flow of B / L through the cell.

If Vth is erased below 0V, Vcc is applied to SSL1 where Vth of the string select transistor is + 1V and 0V is applied to SSL2 where Vth of the select transistor is -2V. B / L current is generated through the select cell of the select string and sensed by the sense amplifier.

The implementation of a shared bit line cell using the above technique shows that two neighboring strings are connected through one bit line contact, thus facilitating the process in terms of bit line pitch density, bit line contact, and metal bit line formation. have.

However, the above-described shared bit line cell has improved design rules related to bit line contact, compared to a single bit line cell. However, in accordance with the recent rapid high integration, the above-described shared bit line cell alone is a bit line contact related design. Rules can no longer be used plainly.

That is, a single bit line forms one contact at one bit line pitch, and a shared bit line forms one contact at two bit line pitches, but as the bit line pitch decreases, one contact is made at two bit line pitches. Even when forming the process, it is not easy to secure the space between the metal overlap and the contact overlap of the metal layout surrounding the contact during the process.

For example, when a contact line of 0.7 μm is formed within 1.4 μm when the bit line direction pitch of a unit cell is actually 0.7 μm, the metal distance surrounding the contact should be 0.2 μm or more to prevent misalignment during masking. A process margin can be secured during each layout etching.

Therefore, when the metal width is 1.1 μm and the metal-to-metal distance is 0.6 μm, and the design rule is reduced in some cases, the structure alone may not completely remove the scale down limiting element of the contact process.

As described above, in spite of its advantages, the shared bit line cell according to the prior art increases in the same number as the number of selection transistors as the number of shared bit lines increases, and thus, the actual cell size by the number of selection transistors increased. It also has the problem of increasing.

Accordingly, the present invention has been made to solve this problem, and an object thereof is to provide a 3-bit shared flash memory cell that can share three bit lines but can maintain the same cell area as in the prior art.

In order to achieve the above object, the present invention provides a plurality of string selection transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection for fail relief in a standby state. Transistors are configured in series circuits between the bit line and the ground voltage terminal to form one unit string, and the three neighboring unit strings share one bit line contact and share the same string select line. Threshold voltages of the string selection transistors connected to the respective unit strings may be repeatedly formed with three different values.

Preferably, two strings among three string select transistors having different threshold voltages connected to one bit line contact through the same string select line have upper and lower threshold voltage values, and one string Is characterized in that the upper and lower are configured to have the same threshold voltage value.

In addition, the voltage applied to the string select line to select a specific cell is preferably composed of three levels for selectively turning on the string select transistor having three different threshold voltages.

In the present invention, while sharing three bit lines in the existing two bit line shared structures, as the number of shared bit lines increases, the number of selection transistors increases to the same number, and the actual cell size also increases by the number of increased selection transistors. To solve the problem, a cell structure capable of maintaining the same number of selection transistors by adjusting the threshold voltage of the selection transistor has been proposed.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

7 is a plan view of a NAND flash memory cell according to the present invention, and FIG. 8 is an equivalent circuit diagram of FIG.

As shown in FIG. 7, the present invention is conventional in that three cell strings neighboring in the word line (W / L) direction share one bit line contact so that two cell strings share one bit line contact. Compared to the shared bit line cell (hereinafter referred to as SBL), the bit line related design rule is improved.

The string select transistor of SBL is a string select line that is a gate of the string select transistor, in which Vths of neighboring transistors are alternately arranged in increasing and depletion form to select one of two neighboring strings that share a bit line contact. (SSL) is composed of two, and the Vths of the two string select transistors connected in series to one string are configured to have different values, that is, depletion type and increment type, up and down.

On the other hand, in the SBL of the present invention, the Vths of three neighboring transistors have a relative value of depletion type and low incremental value so that one of three neighboring strings sharing a bit line contact can be selected using only two SSLs. Are alternately arranged in a form having a high incremental value, and the Vth of the string select transistors are arranged in the reverse order to the Vth array of the three transistors.

That is, as shown in the layout of FIG. 8, the three stting SSL1 transistors Vth sharing one bit line contact are 2.5V, 0.5V, and -1.5V from the left, and the Vth of the transistors of the SSL2 are -1.5V from the left. , 0.5V, 2.5V will connect only the selected string to the bit line.

If you select node A, apply Vcc to SSL1 and 0V to SSL2, if you select node B, apply 2V to SSL1, 2V to SSL2, and if you select C node, apply 0V to SSL1 and Vcc to SSL2. This allows only one string to be electrically connected to the bit line.

9A and 9B, the erase, program, and read operations of the selected cell A will be described as follows.

First, the erase operation applies Vers to the bulk about 20V as in the prior art, and then discharges electrons in the fluting gate to the bulk silicon through the tunnel oxide to shift the threshold voltage of the cell to -3V by applying the selected word line to 0V. .

In order to program the cell A, Vcc is applied to B / L, SSL1, and 2, 0V is applied to GSL and CSL, and Vpass voltage higher than Vcc or Vcc and lower than Vpgm is applied to W / L. After precharging the voltage applied to / L to the cell channel, and sequentially applying voltages to Vpgm, SSL2, 0V, and B / L1 to 0V to the selected W / L, the precharge voltage induced to the selected cell channel is B. It is discharged through / L to maintain 0V.

Vpgm of about 18V applied to the W / L causes electrons to be injected from the bulk into the floating gate through the tunneling oxide film, thereby changing the cell Vth to 1V. At this time, the erase cell connected to the selected W / L of the non-selected B / L is stressed, but the cell channel connected to the unselected bit line is precharged and the B / L and C / S lines by the SSL and GSL voltages. And electrically separated. Therefore, after the channel voltage is selfboosted above Vcc by Vpass and Vpgm applied to the selected W / L while the channel is floating, the voltage is maintained on the channel for the program time, so that Vpgm, Tunneling from the bulk by the Vpass voltage is prevented.

The read operation to read the data storage state of the cell is selected by applying 0.7 V for B / L1, V1 for SSL1 and unselected W / L, and 5 V for GSL, and 0 V for CSL, SSL2 and optional W / L. If the cell's Vth is programmed above 0V, there is no current flow through the cell. If Vth is erased below 0V, Vcc is applied to SSL1 where Vth of the string select transistor is + 2.5V, and 0V is applied to SSL2 where Vth of the string select transistor is -1.5V. B / L current is generated through the select cell of the left select string and sensed by the sense amplifier.

Therefore, the contact related design rule of the conventional shared bit line cell according to the technology of the present invention can be increased while maintaining the same cell area, thereby providing a more advantageous structure for cell scale down.

In addition, the number of metal bit lines can be reduced to reduce capacitors between bit lines, and for this purpose, the string select lines are increased from two to three of the present invention, and the threshold voltages of the select transistors are depletion and increase. Enhancement Alternates two values, with three transistors connected to one string for -2V, -2V, and 1V from the top of the left string, and the middle string for -2V, 1V, and -2V from the top. The right string is 1V, -2V, and -2V from the top, and one string can be selected by combining three SSLs.

This technique also has the disadvantage of substantially increasing the cell area, but can be used in limited applications to increase the bit line contact design rules or to reduce the cap between bit lines.

Claims (4)

A plurality of string select transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection transistors for fail relief in a standby state are provided between the bit line and the ground voltage terminal. Are constructed in series circuits to form one unit string, wherein the three neighboring unit strings share one bit line contact and are connected to the respective unit strings through the same string select line. The threshold voltage of the string select transistor of the nonvolatile semiconductor memory device, characterized in that the three different values are formed repeatedly. The method of claim 1, wherein two strings among three string select transistors having different threshold voltages connected to one bit line contact through the same string select line have different upper and lower threshold voltage values. 1. The nonvolatile semiconductor memory device according to claim 1, wherein one string is configured to have the same threshold voltage value. The method of claim 1, wherein the voltage applied to the string select line to select a specific cell is configured with three levels for selectively turning on string select transistors having three different threshold voltages. Nonvolatile Semiconductor Memory Device. A plurality of string select transistors for selecting a specific cell, a plurality of memory cell transistors for data storage, and ground selection transistors for fail relief in a standby state are provided between the bit line and the ground voltage terminal. Are constructed in series circuits to form one unit string, wherein the three neighboring unit strings share one bit line contact and are connected to the respective unit strings through the same string select line. The threshold voltage of the string select transistor of is composed of an increment of one '+' value and two depletions of a '-' value, and the two depletion and one increment transistors are repeatedly configured. Threshold of three series connected string select transistors connecting the one unit string to a bit line contact Non-volatile memory, characterized in that the pressure is composed of two depletion type and one increment type, but different from the combination of threshold voltages of neighboring string select transistors connected through the same string select line with one bit line contact. Device.