KR100217905B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100217905B1 KR100217905B1 KR1019960009076A KR19960009076A KR100217905B1 KR 100217905 B1 KR100217905 B1 KR 100217905B1 KR 1019960009076 A KR1019960009076 A KR 1019960009076A KR 19960009076 A KR19960009076 A KR 19960009076A KR 100217905 B1 KR100217905 B1 KR 100217905B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 절연막으로 사용되는 SOG막을 도포한 후 이온 주입 공정으로 SOG막 내부에 잔존하는 불순물을 제거하므로써, 수분 발생의 원인이 되는 Si-CH3및 메틸이 이온 주입 에너지에 의해 파괴되어 수분 발생이 억제되는 효과를 가져오게 되며 이 결과로 인해 금속이 증착될 때 스텝 커버리지(Step Coverage)가 향상되고, 소자의 특성 및 수율 향상을 가져올 수 있는 반도체 소자 제조 방법이 개시된다.The present invention removes impurities remaining inside the SOG film by an ion implantation process after coating the SOG film used as the insulating film, thereby causing Si-CH 3 and methyl, which are the causes of water generation, to be destroyed by ion implantation energy, thereby producing water. Disclosed is a method of manufacturing a semiconductor device capable of bringing an effect that is suppressed, and as a result, when step metal is deposited, step coverage is improved, and the characteristics and yield of the device can be improved.
Description
제1(a)도는 내지 제1(c)도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2A : 제1층간 절연막1 silicon substrate 2A first interlayer insulating film
2B : 제2층간 절연막 2C : 제3층간 절연막2B: second interlayer insulating film 2C: third interlayer insulating film
3 : 제1 금속층 4 : SOG막3: first metal layer 4: SOG film
5 : 제2 금속층 6 : 콘택홀5: second metal layer 6: contact hole
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 절연막으로 사용되는 SOG막을 도포한 후, 이온 주입 공정으로 SOG막 내부에 잔존하는 불순물을 제거할 수 있도록 한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which an impurity remaining in an SOG film can be removed by an ion implantation process after coating an SOG film used as an insulating film.
일반적으로 반도체 소자 제조에 있어서, 절연막으로 사용되는 SOG는 실라놀컴파운드(Silanol Compound)와 솔벤트(Solvent)가 혼합되어 있는 액체 용액으로서 조성식은 다음과 같다.Generally, in manufacturing a semiconductor device, SOG used as an insulating film is a liquid solution in which a silanol compound and a solvent are mixed, and the composition formula is as follows.
이러한 SOG는 실라놀 컴파운드(Silanol Compound)에 CH3기의 존재 유무에 따라 실리사이트(Silicate)계와 실록산(Siloxane)계로 나뉘어지는데, 실록산계는 실리사이트계에 비해 점도가 커서 도포후에 평탄도가 우수하고 크랙(Crack)의 내성이 크다는 장점이 있다. SOG는 주로 스핀(Spin) 도포 방법에 의해 모재에 도포되며 차후의 베이크(Bake)나 큐링(Curing) 공정에서 실록산 래디컬(Siloxane Radical)들이 고체화되어 절연막 역할을 하게된다. SOG막은 IMO(Inter Metal Oxide)막 평탄화 공정에서 CVD(Chemical Vapor Deposition) 증착막만으로는 IMO막을 충분히 평탄화시킬 수 없을 때 금속 배선간의 간극을 메꾸어 상부 산화막을 평탄화시킨다. SOG막은 화학 증착막에 비해 막질이 열악하고 금속막과의 접착 불량 문제 때문에 SOG막의 상부와 하부를 플라즈마 화학 증착막으로 감싸주어 사용한다.SOG is divided into silicite and siloxane based on the presence or absence of CH 3 group in silanol compound.Since the siloxane is more viscous than silicite, the flatness after application It has the advantage of excellent crack resistance. SOG is mainly applied to the base material by a spin coating method, and siloxane radicals are solidified in a subsequent bake or curing process to serve as an insulating film. The SOG film makes up the upper oxide film by filling gaps between metal lines when the IMO film cannot be sufficiently flattened by the CVD (Chemical Vapor Deposition) film only in the IMO (Inter Metal Oxide) film planarization process. Since the SOG film has a poor film quality compared to the chemical vapor deposition film and the problem of poor adhesion with the metal film, the SOG film is used by wrapping the upper and lower portions of the SOG film with the plasma chemical vapor deposition film.
특히 종래에는 SOG막 도포 후, 막 내부에 있는 다량의 불순물 성분인 수소성분을 퍼니스 튜브(Furnace Tube)를 이용해 제거해 왔으나, 완전히 제거되지 않아 콘택홀 속으로 이 수소 성분들이 유출되어 제 2 금속층 스텝커버리지를 나쁘게 만들어 홀안에서 금속의 끊김 현상이 발생되어 소자의 특성을 저하시켜 수율을 저하시키는 단점이 있다.Particularly, after applying SOG film, hydrogen content, which is a large amount of impurities inside the film, has been removed using a furnace tube. However, since the hydrogen content is not completely removed, the hydrogen content flows out into the contact hole and the second metal layer step coverage. The disadvantage is that the breakage of the metal in the hole is caused to degrade the characteristics of the device to lower the yield.
따라서, 본 발명은 절연막으로 사용되는 SOG막을 코팅한 후, 이온 주입 공정으로 SOG막 내부에 잔존하는 불순물을 제거하므로써 상기한 문제점을 해결할 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the above problems by coating an SOG film used as an insulating film and then removing impurities remaining inside the SOG film by an ion implantation process.
상술한 목적을 달성하기 위한 본 발명은 실리콘 기판 상부에 제 1 층간 절연막, 제 1 금속층, 제 2 층간 절연막 및 SOG막을 순차적으로 증착하는 단계와, 상기 SOG막을 큐링한 후 이온 주입 공정을 실시하여 막내부의 불순물을 제거하는 단계와, 전체 구조 상부에 제 3 층간 절연막을 증착한 후 상기 제1금속층이 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀이 형성된 전체 구조 상부에 제 2 금속층을 형성하는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially depositing a first interlayer insulating film, a first metal layer, a second interlayer insulating film and SOG film on the silicon substrate, and after the SOG film is cured to perform an ion implantation process Removing negative impurities, depositing a third interlayer insulating film over the entire structure, forming a contact hole to expose the first metal layer, and forming a second metal layer over the entire structure in which the contact hole is formed. Characterized in consisting of steps.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1(a)도 내지 제1(c)도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.1 (a) to 1 (c) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the present invention.
제1(a)도는 실리콘 기판(1)상부에 제 1 층간 절연막(2A), 제 1 금속층(3), 제 2층간 절연막(2B) 및 SOG막(4)이 순차적으로 형성된 상태의 단면도이다.FIG. 1A is a cross-sectional view of a state in which the first interlayer insulating film 2A, the first metal layer 3, the second interlayer insulating film 2B, and the SOG film 4 are sequentially formed on the silicon substrate 1.
제1(b)도를 참조하면, SOG막(4)이 400 내지 450℃의 온도에서 1시간 동안 큐링(Curing)된 후, 전체 구조 상부에 이온 주입 공정이 실시된다. 이온 주입 공정에 의해 SOG막(4) 내부에 있는 불순물이 제거되어 막 자체가 조밀하게 되고, 수분 발생의 원인인 Si-CH3및 메틸이 이온 주입 에너지에 의해 파괴되어 수분 발생이 억제된다. 상기 이온 주입 공정 조건은 소오스에 상관없이 30keV 이상의 에너지와 1E14이상의 도우즈(Dose)이면 된다.Referring to FIG. 1 (b), after the SOG film 4 is cured at a temperature of 400 to 450 ° C. for 1 hour, an ion implantation process is performed on the entire structure. By the ion implantation process, impurities in the SOG film 4 are removed to densify the film itself, and Si-CH 3 and methyl, which are the causes of water generation, are destroyed by ion implantation energy, thereby suppressing water generation. The ion implantation process conditions may be an energy of 30 keV or more and a dose of 1E14 or more, regardless of the source.
제1(c)도를 참조하면, 전체 구조 상부에 제3층간 절연막(2C)이 증착된 후, 콘택 마스크를 이용한 식각 공정이 실시되어 제1 금속층(3)이 노출되도록 콘택홀(6)이 형성된다. 콘택홀(6)이 형성된 전체 구조 상부에 제2 금속층(5)이 형성된다.Referring to FIG. 1 (c), after the third interlayer insulating film 2C is deposited on the entire structure, an etching process using a contact mask is performed to expose the first metal layer 3 so that the contact hole 6 is exposed. Is formed. The second metal layer 5 is formed on the entire structure in which the contact hole 6 is formed.
상기 제1 금속층(3)을 노출시키는 식각 공정시 SOG막(4)이 에칭되는 반응식은 다음과 같다.The reaction scheme in which the SOG film 4 is etched during the etching process of exposing the first metal layer 3 is as follows.
SOG막(4)의 조밀도에 대한 여부는 막의 에칭 비율을 측정하므로써 알 수 있는데 주입한 경우가 8배 정도 조밀한 것으로 측정되었다.Whether or not the density of the SOG film 4 can be determined by measuring the etching rate of the film was estimated to be about 8 times denser when injected.
[표 1]은 이온 주입 조건에 따른 SOG막의 에칭 비율을 나타낸 것이다.Table 1 shows the etching rate of the SOG film according to the ion implantation conditions.
상술한 바와 같이 본 발명에 의하면 절연막으로 사용되는 SOG막을 도포한 후 이온 주입 공정으로 SOG막 내부에 잔존하는 불순물을 제거하므로써, 수분 발생의 원인인 Si-CH및 메틸이 주입 에너지에 의해 파괴되어 수분 발생시 억제되는 효과를 가져오게 되고 이 결과로 인해 금속이 증착될 때 스텝 커버리지(Step Coverage)가 향상되고, 소자의 특성 및 수율 향상을 가져올 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after the SOG film used as the insulating film is applied, the impurities remaining inside the SOG film are removed by the ion implantation process, thereby causing Si-CH and methyl, which are the causes of water generation, to be destroyed by the implantation energy. This results in an effect that is suppressed at the time of occurrence, and as a result, the step coverage is improved when the metal is deposited, and there is an excellent effect that can lead to improved characteristics and yield of the device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960009076A KR100217905B1 (en) | 1996-03-29 | 1996-03-29 | Method of manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960009076A KR100217905B1 (en) | 1996-03-29 | 1996-03-29 | Method of manufacturing semiconductor device |
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| KR970067700A KR970067700A (en) | 1997-10-13 |
| KR100217905B1 true KR100217905B1 (en) | 1999-09-01 |
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| KR1019960009076A KR100217905B1 (en) | 1996-03-29 | 1996-03-29 | Method of manufacturing semiconductor device |
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