TW457628B - Air gap formation for high speed IC processing - Google Patents

Abstract

The process of the present invention can be used for conventional processing or for the Damascene process. The key concept of the present invention is a functional ""filler"" material which can later be removed (decomposed) to leave an air gap between the conducting lines. The filler material can be deposited as a step during conventional metal etch processing or it can be deposited as a first step of the processing of a semiconductor wafer. Leakage currents can be reduced as part of the present invention by applying passivation layers.

Description

457628 .----------- --------- V. Description of the invention (1) Background of the invention: Field of the invention: The invention relates to the manufacture of integrated circuit devices, especially For the formation of organosiloxanes and silicones and the formation of air gaps as a low dielectric constant substance between conductive wires. Known technical know-how: The formation of air gaps between conductive lines in high-speed integrated circuits (1C) is typically a deposition of a metal layer to form a selective etch that requires a linear metal layer, and will be removed later to form Air-gap porous dielectric layer or combination of disposable liquid layer. Continuous efforts to reduce the size of a single transistor and other devices that are generally accumulated on a semiconductor wafer and increase the density of the integrated circuit produce a continuous decrease in the distance between conductive layers of the material, which reduces the capacitance between adjacent conductive lines of the semiconductor circuit The increase in the attenuation of the crosstalk, that is, the change in the potential on the first conductive line or the potential β on the second conductive line. This change in potential can cause the wrong potential level in the integrated circuit to make 1C greatly increase the wrong operation. Therefore, it is unavoidable to reduce the resistance-capacitance (RC) time constant and the attenuation of crosstalk between adjacent conductive lines. The capacitance between adjacent conductive lines is highly dependent on the insulation or dielectric used to isolate the conductive lines. Conventional semiconductor manufacturing typically uses silicon dioxide as a dielectric, which has a dielectric constant of about 3,9. Due to the fact that the equipment does not effectively properly handle the new dielectric materials in various integrated circuits, the use of many low dielectric constant materials is not feasible. The chemical or physical properties of many low dielectric constant materials are often difficult to match or

Page 4 457628 V. Description of the invention (2) I --- Adjusted to the manufacturing of conventional integrated circuits. The lowest possible and therefore ideal dielectric constant is 1 (), which is the dielectric constant of vacuum, while air has a dielectric constant of less than 〇, 〇〇 丨. The main purpose of IC design is to reduce the capacitive coupling and reduce the attenuation of capacitive crosstalk. The main purpose of IC design is to reduce the dielectric constant (k) of the insulating layer between adjacent conductive lines of a semiconductor circuit. The present invention provides a great contribution within the scope of this effort.

U.S. Patent No. 5,750,415 of Gnade et al. Shows a method of engraving a filling material C such as 'disposable liquid layer 18) to form a metal wire with an air gap between 6' discardable liquid layers. 8 by The porous porosity film 20 gelled to form the low porosity hair film 24 is removed from between the metal wires. The methods and materials used in this process are different from those used by the present invention.

U.S. Patent No. 5,461,003 to Havemann et al. Shows a method of forming an air gap between the metal wires 16 by etching a filling material (disposable liquid layer 18). The porous dielectric layer 20 of the disposable liquid layer 8 is removed from between the metal wires. The methods and materials used in this process are different from those used in this invention. This process is also different from the present invention in that no opening is formed in the overlapping dielectric layer to etch the filling material.

Havemann et al., U.S. Patent No. 5,668,398, the same comments made previously with respect to U.S. Patent No. 5,4,61,003 also apply to this patent, which uses a disposable solid layer 18.

U.S. Patent No. 5,324,683 to Fitch et al. Shows a method for forming air gaps by selectively removing lossy compartments (16: 16b) or by selectively removing lossy layers (28,40). This removal is done by etching, but the layer and compartment materials are different from those used by the present invention.

Page 5 457628

V. Invention Description (3)

The comments made by Pitch et al., USP 5,510,645, 3 2 4, 6, 8 3 also apply to this patent Disposable Solid Layer 18. I. Summary of the invention: | The main object of the present invention is to provide an effective and very manufacturable method for forming an air gap in a material. "Interlayer" Another object of the present invention is to reduce the dielectric constant of the material. k method. Another object of the present invention between layers is a method for reducing the amount of material inducted. Electricity between Electric Layers Another object of the present invention is a method for reducing the attenuation of full crosstalk induced by noise in materials. 另一 Another object of the present invention is to reduce circuit errors or untruths in 1C. ^ Logic Another object of the present invention is a method for reducing the resistance and capacitance (Rq delay) of the circuit in 1C. Another object of the present invention is to increase the switching speed of the circuit in the IC. New method for air gap between adjacent wires. The first embodiment of the present invention includes a method for forming an air gap between conductive lines of a semiconductor device. A honey-like conductive line is deposited on a base layer, and the filling layer can be discarded. First it is deposited between the conductive lines. The 'disposable filling layer' is the top surface of the type of etched back conductive lines. A layer of dielectric film, silicon oxide or siliconized silicon is deposited on the filling material, and the exhaust holes are Drive in this dielectric

Page 6 457628 V. Description of the invention (4) In the thin film, the interlayer dielectric deposited on the metal layer is polished after the process is completed, and the filling material is removed. FIG. 18 shows a second embodiment of the present invention, in which the passive layer 22 makes the side wall of the metal wire 11 and the exposed oxide layer 20 difficult to change chemically. FIG. 19 shows a third embodiment of the present invention, in which the pure state layer 2 2 makes the side wall of the metal wire 1 1 difficult to undergo chemical changes. This embodiment of the present invention includes exposing the metal wire to a gas to react, and forming The passive state layer only surrounds the metal wire i 1 "The fourth embodiment of the present invention includes a method of first depositing a filler material on a base material. After this deposition, metal deposition occurs, and this metal deposition forms a conductor wire A layer of silicon oxide is now deposited, a vent system is generated from this oxide layer, the filler material is removed, and a metal interlayer hafnium oxide is deposited which will be polished when the method is completed. The advantages of the present invention are: An effective method for forming an air gap between conductive layers of a material. A method for reducing the dielectric constant k between the conductive layers of a material. A method to reduce capacitive coupling between conductive layers of a material. A method for reducing the attenuation of capacitance crosstalk between conductive layers of materials. A way to reduce the chance of circuit errors or incorrect logic stages in 1C. A way to reduce the RC delay of a circuit in 1C. -A method for increasing the switching speed of the circuit in 1C β Brief description of the drawings: The first embodiment of the present invention includes a method for forming an air gap between conductive lines by first depositing the conductive lines, which can be decomposed later Functional

457628 I __-_________ 5. Description of the invention (5) The filling material will be added to the second and third embodiments of the present invention at a later step in the first embodiment of the present invention, providing a Method for reducing leakage current by conducting line and passive layer of oxide layer of base layer. A fourth embodiment of the present invention includes a method of forming an air gap between conductive lines by first depositing a functional filler material which can be decomposed later and remains in the air gap between conductive lines. Brief description of drawing number: 10 Semiconductor wafer 11 Metal conductive material 12 Silicon oxide gasket 13 Silicon oxide gasket 14 Disposable layer 15 Silicon oxide layer 16 Metal wire 17 Metal interlayer oxide layer 18 Air gap 20 Base layer 21 Base 2 2 Detailed description of the passive layer 2 4 embodiment of the low-porosity silicon thin film: The method and use of the preferred embodiment will now be described in detail below. However, this

Page 457628 ----—__ ____ V. Description of the invention (6) '^ 一 " " ---- ^, it is clear that the report can be combined with a wide range of applicable developments in specific areas. The specific embodiments discussed herein are only illustrative of specific methods of making and using the invention, and do not limit the scope of the invention. The following is a description of the examples, including manufacturing methods. Figures 1 to 9 show a first embodiment of the present invention. In particular, please refer to FIG. 1, which shows a cross-sectional view of a semi-circular circle 10 with a substrate 21 and a base layer 20. The substrate 2 can include, for example, electric dimers, diodes, and other semiconductor elements (not shown) familiar with this technology. 21 also includes a metal wire layer. The substrate 21 is preferably made of a single crystal, and the substrate can also be made of gallium and sapphire. The silicon-based layer 20 of the spar, dioxide insulator may also include other dielectric materials. In general, the base layer 20 indicates that the present invention formed in an air gap between adjacent conductive lines of a semiconductor circuit can be applied to an integrated circuit. The metal conductive material 11 is a conductive region in a T-type, such as a metal diacid .: A metal silicide, polycrystalline silicon, amorphous silicon, or any other suitable conductive layer 'This section can indicate any order of conductive wire that must be isolated and engraved in a predetermined pattern to form a metal wire. FIG. 3 shows the deposition of silicon oxide liner i 3, which is not necessary at this stage. FIG. 4 shows the deposition of the filling material 4. The filling material used in the present invention includes organic siloxane or silicone, and a deposition method Not critical

Page 457628 V. Description of the invention (7) and can be physical vapor deposition (PVD), chemical vapor deposition (CVD), spin coating materials, etc. For example, the disposable layer 14 can be spin-coated at low speed The height on the wafer to about twice the height of the metal wires is to fill all the space between the metal wires of the filler material. For the filler material, whether it is organic or inorganic, as long as the filler material has a melting point temperature of 7C can be used to deposit any material under the dazzling point of the filling material. The dazzling point temperature of the filling material must be lower than about 50 ° C (TC 'device wafer can withstand this temperature. This limits the melting point temperature of the filling material to The range between 50 and 50 ° C. The melting point of the filling material determines its coating process. Filling materials with high melting point PVD or CVD are better coating processes. Filling materials with low melting point Coating is the better coating process. Figure 5 shows the surface view after chemical or mechanical etchback is performed, for example, 'This etchback removes some filler material by rotating the wafer with a high grip. 1 4 While being implemented (to Centrifugal force), this etchback has removed the filler material and the upper part of the oxide film (the part farthest from the base layer). The top of the conductive material (the area farthest from the substrate) is nominally the only one affected by this etchback The silicon oxide liner and filler material that have been deposited between the conductive lines remain unaffected. Figure 6 shows the deposition of the silicon oxide layer (oxide cap) 15 and the choice of a conventional photoresist (PR) mask. Cross-sectional view after the holes 16 that are open in nature, the holes 16 that are selectively opened do not affect the bottom layer of the filling material or conductive wire. The heating process to remove the filling material is a vacuum or non-vacuum or rapid heating process The filling material is evaporated in this way.

Page 10 457628 V. Description of the invention (8) The radiation process to remove the filling material is an optical process in which electrons or ion beams are bombarded in a vacuum to remove the filling material. During this lighting period, it is a process using various Wavelength range of light illumination. Other methods to remove the filling material are a chemical removal process, such as the use of a hydrofluoric acid (HF) solution with a SiN pad and a cap. FIG. 7 shows a cross-sectional view of the removal of the filler material 14. This removal process step can use any method such as removal of heat (heat), electrons, optics, high-energy molecular beams, etc. The air gap 18 (shown in FIG. Figure 8) is now formed between the conductive lines. FIG. 8 shows the deposition of a metal interlayer oxide layer 17. Figure 9 shows the complete process of conventional chemical / mechanical grinding and planarization. For aluminum this temperature is approximately 67 ° C. Figures 18 (i) and i (9) show the second and third embodiments of the present invention, respectively. First refer to Section 18, 'The oxide layer 20 and the metal wire 11 may have an active surface.' The active surface can be used as a path for the remaining non-passivated leakage current. The figure shows another embodiment. 'One (eg, uniform) passivity The layer 22 passivates the exposed surfaces of both the oxide layer 20 and the metal wire 22 to prevent leakage between the wires. The 19th explanation states that the passive layer is formed only along the metal wire 22, which includes exposing the metal wire to a The gas' reacts and forms a passive layer 22. Figures 10 to 17 relate to a fourth embodiment of the present invention.

i 457628!: 5. Description of the invention (9) '~~~~-Figure 10 shows the base layer 20 on the surface of the semiconductor wafer 10, and the base layer 20 and the substrate 2 are described in detail in Figure i earlier. The same comments can be applied to the semiconductor wafer 10. Figure 11 shows a cross-sectional view after the filling material 12 has been deposited and the trench formation i 3 has been completed. 'The filling material used is an organosiloxane or stone glue.' Not critical and can be physical vapor deposition (PVD), chemical vapor deposition (CVD), spin-on materials, etc. The method used to form the trench is also not critical, such as photoresist (pR) masks Standard semiconductor trench formation techniques can be applied. In the purpose of this process, a silicon oxide liner can be deposited. This step is not necessary 'and therefore is not shown in the diagram part of the discussion. When the present invention is further expanded, there will be a supplementary passive layer for the present invention. Part of the need arises, if the leakage current between the deposited metal line and the oxide layer forming the base layer becomes a problem, this will generate 'these pure state layers can be deposited directly on the base layer, performing basic work to insulate adjacent conductive Line, further providing the passive layer along the filler material 'even after the filler material is removed from the substrate in the subsequent method steps. This passive layer after the sheath will remain as part of the structure. These process steps are similar to The steps shown in Figures 18 and 19 are slightly modified from these figures, so as to seal the electrical wires that will be deposited later at this point. Figure 13 shows the metal deposits 14 and the surface after etch back. It is not important to use the method of metal deposition, any current metal deposition method can be applied, and it is not important to use the method of metal etch back. Figure 14 shows a cross-sectional view after the silicon oxide layer (cap portion) 15 has been deposited and the exhaust hole 16 has been manufactured.

^ 7628 V. Description of the Invention (ίο)

Figure 15 shows the removal of the filler material 12, and any of the processing methods mentioned above can be used in this process step. Figure 16 shows the deposition of intermetallic oxide 17. Figure 17 shows a cross-sectional view after the final grinding and planarization is completed. Fig. 18 and Fig. 19 are related to the second and the first embodiment of the present invention. First, Fig. 18, the oxidized surface, the movable surface can be used as a left image to show another embodiment (Example 20). Exposure to both the metal wire 22 and FIG. 19 illustrate that the passivation layer is only exposed to a gas along the metal wire. According to the present invention, a neighboring dielectric with a low dielectric constant is used in a semiconductor circuit, and the reduction is caused. Crosstalk attenuation. Layer 20 and non-purified metal leaks are uniform) Surface-purified semiconductor electrical conductors formed by reacting with metal conductors and forming organosiloxane wires 1 1 Channels that can carry current The passive layer 22 prevents the formation of an oxide layer between the wires. This includes a method of using the passive layer 9 9 = glue as a filling material. The gap between adjacent conductive lines of the air gap circuit. Although the present invention is only implemented by illustration Examples to describe, but this description is not limited to a limited meaning. Modifications and combinations of these, as well as other embodiments of the invention, will be apparent to those skilled in the art of semiconductor manufacturing and will be designed by virtue of these narratives. Therefore, it is indicated here that the following patent application scope includes such modifications or examples β

Brief Description of the Drawings Figures 1 to 9 are sectional views showing a first preferred embodiment of the method of the present invention. Figures 10 to 17 show sectional views of a fourth preferred embodiment of the method of the present invention. Figures 18 and 19 refer to the second and third embodiments of the invention, respectively. Page 14

Claims (1)

457628 VI. Application Patent Scope 1 · One half of which includes a step-fixing half to form a base, a gold deposit, and a pattern with a top; the deposition can be: the gap between the metal wires of the body device is a conductor wafer; Layer on the semiconductor wafer; a layer on the base layer; etching the metal layer to form a metal wire, and a portion of the side wall where the base base layer is exposed to the exposed KI true charge material on the metal wire and The top of the base material's disposable filling material to reduce the disposable filling material. A material is deposited to a low level at least as the top of the metal wire. An oxygen filling material is removed by a pattern material sink to remove the filling deposition metal. Oxygen, such as applying for a special pattern, and a metal wire, such as applying for a special fossil layer, cover the layer of the metal wire and the disposable fill; 'The vent holes etched in the siliconized silicon layer, so that each fill The product has a channel that can lead to at least one exhaust hole; a material; a wide-area oxide layer covers the silicon oxide layer; and performs chemical mechanical planarization of the metallization layer. The method described in item 1 further includes a step of forming a passivation layer on the sidewall after the step of forming the metal wire with the metal layer. The method described in item 1 of the scope of interest includes HHH1 Page 15 4 57 8 28 ί; _Case No. 89109637 ___ Month _ Amendment _. VI. After applying the patent scope pattern etch the metal layer to form a metal wire, except for the side wall Step 4 of forming a passivation layer between the metal wire and the top of the exposed portion of the base base layer outside the passivation layer on the substrate 4. As described in item 1 of the patent application scope, the disposable filling material contains organic Sand burning. 5. The method as described in item 1 of the patent application scope, wherein the disposable filling material comprises silicone. 6 · The method described in item 1 of the scope of patent application, the disposable filling material comprises an organic or inorganic material having a melting point range between 50 and 50 0 ° C 7. The method described in item 1 of the scope of patent application, Wherein the filling material is deposited using PVD or CVD process technology to exhibit high melting point characteristics. 8 · The method as described in item i of the patent application range, wherein the filling material is deposited using a spin-coating process technique to display the low melting point characteristic. Beam bombardment • The method described in item 1 of the patent application for discarding the filling material, including the use of the wavelength in item 1, is based on the use of high-energy beam technology, using the method described in item 1 to use optical technology Wafer lighting. ’Where the disposable electron or ionic molecular light is removed, including the electron beam in a vacuum’ where the removal can be performed by technology, the technology package Page 16 457628 11 12 13 The scope of patent application is as described in the scope of patent application. Method of discarding the filling material Process. The method described in item 1 of the scope of the patent application, the method of discarding the filling material is to use the method described in the fhai filling material item u ® 4 1 where the disposable can be removed for roasting with kiwi. …, The raft is carried out, and the technology package method includes removing the disposable using heating technology, which includes removing the disposable chemical removal 1 4 • If the patent application contains a nitride. 1 5 · If the patent application contains an II compound. 1 6 * If the shift of the patent application material 17 *-a method of forming a semiconducting step described in item 2 'where the passive state layer surrounds the method described in item 3, the pure state in After the first layer is divided, it is fixed to form a semiconductor, a base layer deposited on a filling material wafer, and a semi-conductive material on the material layer is a type of metal material on the top of the filling material. The method described in the exposed section further includes the step of depositing a structural dielectric layer on the fill. The method of the air gap between adjacent metal conducting greens is on the wafer; on the base layer; a pattern 'which is to be etched into a mirror image of a semi-metal wire pattern; the filling material and the surface of the base layer can be discarded; ——— 457628 6. Scope of patent application ----- Move = the top of the metal material to lower the metal material to a level as low as the top surface of the disposable filling material; deposit oxide stone Layer on the metal wire layer and the disposable filling material; opening a vent hole in the silicon oxide layer: removing the filling material through the vent hole to form an air gap between the metal wire under the silicon oxide layer Depositing a metal interlayer oxide layer; and performing chemical mechanical planarization of the metal interlayer oxide layer. 18. The method according to item 17 of the scope of patent application, wherein the disposable filling material comprises an organosiloxane. 19. The method according to item 17 of the scope of patent application, wherein the disposable filling material comprises Mengsheng. 20. The method according to item η of the patent application scope, wherein the disposable filling material comprises an organic or inorganic material having a melting point between 50 and 5001. 21. The method according to item η of the scope of patent application, wherein the method of removing the disposable filling material is based on the use of high-energy molecular beam technology. 22. The method according to item 7 of the scope of patent application, wherein the method of removing the disposable filler material is performed using optical technology. 23. The method as described in item n of the patent application scope, wherein the method of removing the disposable filler material is based on the use of high-energy molecular beam technology. 24. The method as described in claim 17 of the scope of patent application, wherein the method of removing the disposable filler material is performed using thermal, radiological or chemical techniques. Page 457628 6. Application for Patent Scope 25. The method described in item 17 of the patent application scope further includes the step of etching the filler material with a mirror image of the metal wire pattern of the semiconductor circuit after the step of filling the filler material. A step of forming a passivation layer on the deposited sidewall. 26. The method according to item 17 of the scope of patent application, further comprising the step of depositing a structured electronic layer after the step of removing the disposable filler material. Page 19