KR100199006B1 - 1:n interpolation fir filter - Google Patents

Abstract

The present invention relates to a 1: N interpolation finite impulse response (FIR) filter, and in particular, used in the QPSK modulation scheme adopted in code division multiple access (CDMA) digital mobile communication. A 1: N interpolation FIR filter, wherein a ROM storing an integration coefficient of a finite impulse response filter stores only a part of the integration coefficient, and another integration coefficient is stored in the ROM through an address operation. Characterized by the integration factor, the circuit configuration is simple, the size of the chip can be minimized, and the power consumption can be minimized.

Description

1: N Interpolation FIR Filter

1 is a circuit diagram of a 1: 4 interpolation FIR filter for a QPSK modulator according to the present invention.

2 is a timing diagram of a 1: 4 interpolation FIR filter for a QPSK modulator according to the present invention.

* Explanation of symbols for main parts of the drawings

11, 12, 13, 14, 15, 16, 17, 18: D-Flip Flop

20: inverter 30: MUX

40: ROM 50: Adder

The present invention relates to a 1: N interpolation finite impulse response (FIR) filter, and more particularly, to use in a QPSK modulation scheme adopted in code division multiple access (CDMA) digital mobile communication. A 1: N interpolation FIR filter.

Typically, the FIR filter is made by combining a delay, a multiplier, and an adder. In the conventional method, the longer the number of taps of the FIR filter is, the larger the amount of circuits used.

Therefore, conventionally, in order to make up for this drawback, the multiplier obtained by multiplying the input signal and the filter coefficient is obtained in advance and stored in the ROM, thereby omitting the multiplier included in the existing FIR filter, thereby minimizing the circuit configuration.

However, in the conventional QPSK modulation scheme, in order to perform 1: N interpolation, an I-channel FIR filter and a Q-channel FIR filter are required, respectively. Recently, a scheme for reducing the two FIR filters into one has been developed. In this case, two ROM tables are required.

As described above, a conventional method implemented by one FIR filter including two ROM tables will be described below.

If the number of taps in the FIR filter is 48 taps and the interpolation ratio is 1: 4, the 48 coefficients are {c0, c1, c2,... , c46, c47} and the order of input data is d0, d1, d2, d3,. If the filter output is Ym, the general formula of the filter is as follows.

Y0 = d0 * c0

Y1 = d0 * c1

Y2 = d0 * c2

Y3 = d0 * c3

Y4 = d1 * c0 + d0 * c4

Y5 = d1 * c1 + d0 * c5

Y6 = d1 * c2 + d0 * c6

Y7 = d1 * c3 + d0 * c7

······

Y (4m-3) = dm * c0 + d (m-1) * c4 + d (m-2) * c8 +... + d (m-11) * c44

Y (4m-2) = dm * c0 + d (m-1) * c5 + d (m-2) * c9 +... + d (m-11) * c45

Y (4m-1) = dm * c2 + d (m-1) * c6 + d (m-2) * c10 +... + d (m-11) * c46

Y (4m-0) = dm * c0 + d (m-1) * c7 + d (m-2) * c11 +... + d (m-11) * c47

In this equation, the coefficients simultaneously input to 12 multipliers are divided into groups as follows.

The first group of coefficients to be multiplied

{c0, c4, c8, c12, c16, c20, c24, c28, c32, c36, c40, c44}

to be.

The second group of coefficients to multiply

{c1, c5, c9, c13, c17, c21, c25, c29, c33, c37, c41, c45}

to be.

The third group of coefficients to be multiplied

{c2, c6, c10, c14, c18, c22, c26, c30, c34, c42, c46}

to be.

The fourth multiplying coefficient group

{c3, c7, c11, c15, c19, c23, c27, c31, c35, c39, c43, c47}

to be.

Therefore, if a coefficient is calculated in advance for each coefficient group and stored in a ROM table, the FIR filter can be implemented without complicated circuit configuration.

However, when one integration factor ROM is used in the configuration of the ROM table, there are 4096 cases in which 12 input data can occur and four coefficient groups exist, requiring a large ROM of 16,384 * 10 bits. have.

Therefore, to solve this problem, the present invention solves this problem by dividing four coefficient groups in half, and then storing them in two ROM tables, replacing them with two 256 * 10-bit ROM tables and an 11-bit adder. The two divided coefficient groups are as follows.

First coefficient group = {c0, c4, c8, c12, c16, c20} + {c24, c28, c32, c36, c40, c44}

Second coefficient group = {c1, c5, c9, c13, c17, c21} + {c25, c29, c33, c37, c41, c45}

Third coefficient group = {c2, c6, c10, c14, c18, c22} + {c26, c30, c34, c42, c46}

Fourth coefficient group = {c3, c7, c11, c15, c19, c23} + {c27, c31, c35, c39, c43, c47}

In this case, when the two divided coefficient groups are symmetrically around the center tap, the upper coefficient integrated value of the first coefficient group ({c0, c4, c8, c12, c16, c20}) and the lower coefficient of the fourth coefficient group The coefficient integration values {c27, c31, c35, c39, c43, c47} are the same, and the lower coefficient integration value of the fourth coefficient group is the same as the upper coefficient integration value of the first coefficient group.

Similarly, the upper coefficient integrated value of the second coefficient group and the lower coefficient integrated value of the third coefficient group are equal, and the lower coefficient integrated value of the second coefficient group and the coefficient integrated value of the third coefficient group are equal.

According to this rule, the address of the ROM table is appropriately manipulated so that the coefficient group having the same integrated value is stored in the ROM so that one FIR filter is formed by one ROM.

That is, the present invention provides a 1: N interpolation FIR filter for a QPSK modulator that can be implemented by one FIR filter including one ROM table, thereby simplifying circuit configuration and minimizing power consumption and chip size. There is a purpose.

In order to achieve the above object, the present invention multiplies the FIR filtering coefficients divided into four groups by the order of multiplying by the upper bits of the I-channel signal or the Q-channel signal inputted to the FIR filter, and multiplies the integrated value. ROMs divided into four groups of accumulation groups based on coefficient groups, and sequentially stored by dividing the I-channel signal into upper bits and lower ratios, and then clock signals for identification of integration groups in the ROM. A first storage means for outputting each of the upper and lower bits, and storing the Q channel signal into upper and lower bits sequentially and then storing a clock signal for identifying an integration group in the ROM. A second storage means included in the upper / lower bits, respectively, and output; and one signal of each of the signals divided into upper / lower bits and output from the first and second storage means. A mux for outputting the selected signal to a ROM so as to identify an integration group of the ROM based on a clock signal included in the selected signal and extract the corresponding integrated value, and the ROM; It is characterized in that it consists of an adder for outputting the channel signal by adding up the high / low integration value for each channel extracted from the).

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; 1 is a circuit diagram of a FIR filter for QPSK modulation according to the present invention.

Referring to FIG. 1, the FIR filter of the present invention multiplies the FIR filtering coefficients divided into four groups by the order of multiplication and the upper bits of the I channel signal or the Q channel signal inputted to the FIR filter, and multiplies the integrated value. ROM (40) for dividing and storing into four groups of integration groups based on coefficient groups, and sequentially storing the 12-bit I-channel signal into upper 6 bits and lower 6 bits, and then storing the ROM (ROM). A first D-flip-flop group (11, 12) for outputting a clock signal (ck8, ck4 or / ck8, / ck4) for identifying the integration group in the 40 in the upper / lower bits, respectively, and 12; After sequentially storing the Q channel signal of the bit into upper 6 bits and lower 6 bits, the clock signal (ck8, ck4 or / ck8, ck4) for identification of the integration group in the ROM (ROM) 40 is sequentially stored. Second 2D flip-flop groups 13 and 14 included in the lower bits and outputted; In the first and second D-flip-flop groups 11, 12, 13, and 14, one signal of each signal divided into upper / lower bits is selected, and the ROM is selected by a clock signal included in the selected signal. A mux 30 for outputting the selected signal to the ROM 40 to identify the integration group of the ROM 40 and extract the corresponding integrated value; and extract from the ROM 40. And an adder 50 for summing up the high / lower integrated values for each channel and outputting the corresponding channel signal.

In the FIR filter having the above configuration, first, the input data and the coefficient value of the FIR filter are multiplied in advance and stored in the ROM 40, where the integration groups are centered on the center tap. Since the left / right symmetry, the integration group of each lower bit is configured to have the same value as any one upper bit.

Therefore, in the present invention, when the ROM is configured, only the accumulated value for the upper bits of all data is stored to configure the ROM table, thereby reducing the capacity of the FIR hardware.

That is, in Fig. 1, ck1, ck2, ck4, and ck8 are clock signals, ck1 \, ck2 \ and ck8 \ are signals inverted ck1, ck2 and ck8, respectively, and I and Q are respective channel data. In addition, the filter according to the present invention starts under the assumption that the upper and lower tap coefficients are symmetric about the center tap.

The operation of the FIR filter according to the present invention will be described as an example. When the I-channel data is sequentially stored in the upper and lower bit regions 11 and 12 of the 1D-flip flop group, the ROM 40 In order to find the corresponding integrated group stored in the integrated clock group, the clock signal for identifying the integrated group input to the first D flip-flop groups 11 and 12 is as follows.

If '00' indicating the first group is input to the upper bit region 11 of the first D-flop flop group, the fourth group symmetrical to the lower bit region 12 of the first D flip-flop group is input. When '11' is input and '01 indicating a second group is input to the upper bit region 11, '10' indicating a third group symmetrical to the lower bit region 12 is input.

The clock signals input to the upper / lower bit regions 11 and 12 are performed by the clock signals ck4 and ck8 and the inverter 20 connected thereto.

The same applies to the second 2D flip-flop groups 13 and 14.

In this way, when the corresponding output values are output from the first and second D flip-flop groups 11, 12, 13, and 14, the MUX 30 may identify a high / low bit of an I channel or a Q channel. One of the four signals is outputted to the ROM 40 by the clock signals ck1 and ck2.

Then, the ROM 40 outputs the corresponding contents among the contents of the table stored by the signal according to the signal, and the ROM 40 calculates the integrated value of the upper / lower bits for each channel output from the ROM 40. After being distributed and stored in the D-flop flops 15 and 16, they are added as a single channel signal by the adder 50 and output to the D-flip flops 17 or 18 connected to the rear end of the adder.

Thus, by appropriately manipulating the addresses in the ROM table, that is, when generating the address, the lower group assigns the inverted ck8 and ck4 to the MSB 2 bits, and the upper group assigns the ck8 and ck4 to the 8-bit address higher bits, thereby multiplying the coefficient group By storing one accumulated value of the upper or lower coefficients in the ROM 40, a desired 1: 4 interpolation FIR filter can be implemented.

FIG. 2 is a timing diagram of the circuit shown in FIG.

FIG. 2a shows ck1 of FIG. 1, FIG. 2b shows ck2 of FIG. 1, FIG. 2c shows ck4 of FIG. 1, FIG. 2d shows ck8 of FIG. 2, FIG. Indicates the filter output signal for the channel.

The present invention described above has the effect of simplifying the circuit configuration, minimizing the size of the chip, and minimizing global consumption.

Claims (2)

A FIR filter that receives a plurality of clock signals input from outside and I and Q channel signals, and performs a finite impulse response (FIR) filtering, wherein the FIR filtering coefficients divided into four groups in order of multiplication are input to the FIR filter. A ROM 40 for multiplying the upper bits of the I Chanan signal or the Q channel signal and dividing the integrated value into four groups of integrated groups based on the coefficient group, and storing the I channel friend into upper bits and lower bits. First storage means (11, 12) and the Q-channel signal for outputting the clock signal for identifying the integration group in the ROM (40) in the upper / lower bits, respectively, after dividing and sequentially storing the divided signal; Second storage means (13, 14) for sequentially storing the divided into upper bits and lower bits, and then include a clock signal for identifying an integration group in the ROM (40) in the upper / lower bits, respectively, and output the same. And selecting one of the signals output from the first and second mortgage means 11, 12, 13, and 14 divided into upper / lower bits, and then using the clock signal included in the selected signal. (MUX) 30 for identifying the integration group of the (ROM) 40 and outputting the selected signal to the ROM (ROM) 40 so as to extract the corresponding integration value, and in the ROM (ROM) 40. 1: N interpolation finite impulse response filter, characterized in that consisting of an adder 50 for summing the extracted upper and lower integration value for each channel to output the corresponding channel signal. 2. The integrated group identification clock signal included in the lower bits of the first and second storage means indicates an integration group in which the integration group included in the upper bit and the integrated value of the lower bit are symmetrical. 1: N interpolation finite impulse response filter.