KR100333337B1 - Digital filter device and filtering method in mobile communication system - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

A technology related to a finite impulse response (FIR) filter used in a mobile communication system.

I. The technical problem to be solved by the invention

Provided are an apparatus and a method for simplifying a hardware configuration in a filtering apparatus for receiving and filtering a plurality of data at the same time as an IMT-2000 system among mobile communication systems.

All. Summary of Solution of the Invention

An apparatus of the present invention is a device for filtering digital signals by receiving at least two signals at the same time in a mobile communication system, and receiving a PN code of a long PN code and a short I channel and a PN code of a short Q channel. A quadrature spreading code generator for generating PN codes of I and Q channels for spreading, a filtering block for processing a corresponding signal among the input signals, and a signal filtered from the filtering block It is made up of an adder,

The filtering blocks;

A first multiplier for multiplying corresponding data among the input data and an I-channel PN code of the quadrature spreading code generation unit, a second multiplier for multiplying the corresponding data with a Q channel PN code of the quadrature spreading code generation unit; A selector for alternately outputting the outputs of the first and second multipliers, a baseband filter for filtering the output of the selector, and a gain multiplier for multiplying the gain of the channel with data output from the baseband filter. Characterized in that configured.

la. Important uses of the invention

It is used in a high speed data processing device that receives data of several channels at the same time.

Description

DIGITAL FILTER DEVICE AND FILTERING METHOD IN MOBILE COMMUNICATION SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter apparatus and method for a mobile communication system, and more particularly, to a finite impulse response (FIR) filter apparatus and a filtering method for filtering multiple bits.

In general, a mobile communication system is a system that wirelessly services voice and data in association with a mobile station. Many kinds of such mobile communication systems are currently used. To illustrate this example, there are a Digital Cellular System (DCS) and a Personal Communication System (PCS). In such a system, the data to be transmitted is composed of a single bit, and thus the data can be transmitted in a very simple way when filtering the data. This will be described with reference to FIG. 1.

1 is a block diagram of a FIR filter for filtering multi-bit channel data according to the prior art. n bits of input data are sequentially input to the right shift register unit 10 by 1 bit. Then, the input 1-bit data is sequentially moved from the first register A1 to the twelfth register A12. The registers A1, A2, ..., A11, except for the last register A12, sequentially output the input data to the input terminal of the next register. At the same time, the outputs of the registers A1, A2, ..., A11 are branched and input to the multipliers B1, B2, ..., B11 configured to correspond to each register. The output of the register A12 located at the last end of the shift register unit 10 is input to a multiplier B12 corresponding to the register A12. Each of the multipliers B1, B2, ..., B11, and B12 receives the outputs of the corresponding coefficient selectors C1, C2, ..., C11, and C12, respectively, and multiplies the outputs of the corresponding registers. The multiplied value is output to the adder 20. Here, the first multiplier B1 corresponds to the first coefficient selector C1, the second multiplier B2 corresponds to the second coefficient selector C2, and in this way, the twelfth multiplier B12 corresponds to the twelfth coefficient. Corresponds to selector C12. Each of the multipliers B1, B2, ..., B11, B12 multiplies the input data and outputs the multiplier 20 to the adder 20. The adder 20 adds and outputs data output from each of the multipliers B1, B2, ..., B11, B12, and the output is a filter output. When the input data is 1-bit data, the multipliers B1, B2, ..., B11, B12, the coefficient selectors C1, C2, ..., C11, C12 and the adder 20 are used. The output of can be used as a memory to store the precomputed values. That is, the reference numeral 30 shown by a dotted line may be used as one memory.

Referring to the operation according to the configuration of Figure 1 as follows. Assume that the number of the FIR filter is 12, the coefficient of the FIR filter is N bits, and the channel gain G is M bits. Then, when a single bit of data is input, the data is delayed and stored for a predetermined period determined according to the number of taps and the up-sampling ratio of the FIR filter. That is, data that is delayed while being moved by the registers A1, A2,..., A11, and A12 is stored. When the up-sampling is performed, if there is no valid data, data of '0' is input. Therefore, the coefficients multiplied by the delayed channel data, that is, the data stored in the respective registers A1, A2, ..., A11, A12, that is, the values output from the respective coefficient selectors C1, C2, ..., C11, C12. Is expressed as follows. The outputs of the selectors C1, C2, ..., C11, C12 are sequentially C (S * 0 + s), C (S + s), C (S * 2 + s),... , C (S * (11) + s), where s is 0, 1, 2,... According to the order of input data. It can be expressed as S-1. Therefore, the coefficients sequentially multiplied by the FIR filter for the data of the first D0 are C (0), C (1), C (2),... , C (S-1) is sequentially multiplied, and the coefficients sequentially multiplied by the FIR filter for the second data D1 are C (S), C (S + 1),... It becomes the value of C (S + S-1). Therefore, when x (,) is expressed as channel data and c (,) is expressed as a filter coefficient, the output value M of the FIR filter may be expressed by Equation 1 below.

Where s = 0, 1, 2,... , S-1.

In the FIR filter displayed as described above, the coefficient selector selects the filter coefficients according to the up-sampling phase and adjusts the gain ratio according to the data rate. This method reduces the hardware burden by multiplying the channel gain value G in advance if the transmission rate is full rate according to the coefficient of the filter by the number of taps. In this way, the coefficients selected by the coefficient selectors C1, C2, ..., C12 are multiplied by the channel data. In addition, since the channel data are single bits, the single bits are bipolar mapped to 0, 1, or -1, 1 using a code converter (not shown in FIG. 1) to multiply the selected filter coefficients.

In such systems, a single bit of channel data has a rate of one of full rate, half rate, quarter rate, and eighth rate. Therefore, in the case of the overall ratio, if the channel gain has a value of G, if the transmission rate is 1/2, the channel gain is If the data rate is 1/4, the channel gain is G / 2. If the data rate is 1/8, the channel gain is Has the value That is, since the transmission speed is adapted to the transmission and reception of the voice signal, and the ratio is also very simple as described above, the filter can be simply configured using the memory structure.

However, in the mobile communication system currently in use, since data transmission basically consists of voice signals, there is a problem that high-speed data cannot be serviced. Therefore, development is being made to provide a system capable of transmitting more data while providing various services. An example of such a system is the IMT-2000 system.

In the system according to the IMT-2000, high speed data and voice channel transmission is possible. In the wideband DS-CDMA system of the IMT-2000, the above-mentioned types are opened simultaneously with a high-speed data channel, a voice channel, and a pilot channel for improving the synchronization acquisition of the receiver. Can transmit data at the same time. In this case, each channel has a power gain, that is, channel gain, determined according to the data rate of the open channel, the type of the channel, and the frame size of the coding method of the channel. Multi-bits channel data adjusted according to the channel gain is generated as base band data through a digital FIR filter. In such an IMT-2000 system, a FIR filter having a structure as shown in FIG. 2 is configured in a system for transmitting wireless data such as a base station to simultaneously perform various services. Next, the configuration and operation of the FIR filter proposed in the IMT 2000 will be described with reference to FIG. 2.

2 is a block diagram of an FIR filter configured to provide various services to a wireless transmitter of the IMT-2000 system.

Data of the pilot channel and data of the power control are spread by Walsh codes and input to the PCH gain multiplier 101. Data of the dedicated control channel spread by the Walsh code is input to the DCH gain multiplier 103. The data spread by the Walsh code is input to the SCH gain multiplier 105 of the Supplemental Channel, and the data spread by the Walsh code is input to the FCH gain multiplier 107 of the Fundamental Channel. do. Data of the gain measured by the PCH gain multiplier 101 and data output from the DCH gain multiplier 103 are input to the first adder 109, and the two input data are input to the first adder 109. It is added by and outputs. Data output from the SCH gain multiplier 105 and the FCH gain multiplier 107 is input to the second adder 111, and the two input data are added and output. In this way, the data sum_ch0 added and output from the first adder 109 is input to the first multiplier 113 and the fourth multiplier 119. The data sum_ch1 added and output from the second adder 111 is input to the second multiplier 115 and the third multiplier 117.

On the other hand, the output of the I-channel PN code generator 131 for generating the short PN code of the I-channel, and the output of the Q-channel PN code generator 133 for generating the short PN code of the Q-channel, The quadrature spreader code generator 139, which receives the output of the long PN code generator 135 for generating the long PN code, receives the signals and receives the PN code of the I channel. Generates and outputs the PN codes of the and Q channels. At this time, the PN code of the I channel output from the quadrature spreading code generator 139 is input to the first multiplier 113 and the second multiplier 115. Accordingly, the first multiplier 113 multiplies the output data sum_ch0 of the first adder 109 by the I-channel data output from the quadrature spreading code generator 139. The second multiplier 115 multiplies the output of the second adder 111 by the PN code data of the I channel output from the quadrature spreading code generator 139. The third multiplier 117 multiplies the output of the second adder 111 by the Q channel data output from the quadrature spreading code generator 139, and the fourth multiplier 119 is a first adder 109. The signal output from the multiplier and the Q-channel data output from the quadrature spreading code generator 139 are multiplied and output.

Then, the data output from the first multiplier 113 and the data converted from the value multiplied by the third multiplier 117 into negative values are input to the third adder 121. Therefore, the third adder 121 adds and outputs two data. In addition, the data output from the second multiplier 115 and the data output from the fourth multiplier 119 are input to the fourth adder 123. Therefore, the fourth adder 123 adds and outputs two signals. The data flt_in_I output from the third adder 121 is input to one input terminal 1 of the selector 125, and the data flt_in_Q output from the fourth adder 123 is the other one of the selector 125. It is input to the input terminal (0). The selector 125 uses a transmission clock Tx_clk as a selection signal, and two signals are alternately output by the selection signal. The signal output as described above is input to an input terminal of the base band filter 127. The baseband filter 127 filters and outputs a signal output from the selector 125.

However, when the structure shown in FIG. 2 is used, since the single bit data is not output from the selector 125 and the multiple bit data is output, the volume of the baseband filter 127 is increased and is very complicated. . In addition, when the multi-bit data is output as described above, the memory structure as described in FIG. 1 cannot be used. That is, a problem arises in that the burden on the circuit becomes large and the memory structure cannot be used at the same time.

Accordingly, an object of the present invention is to provide a filter device and a filtering method which can be applied to an IMT-2000 system which is inexpensive, can reduce the burden of hardware, and can process multiple bits of data.

Another object of the present invention is to provide an optimized FIR filter device and a filtering method that can handle the change in channel gain of transmitted data and minimize the burden on hardware.

An apparatus of the present invention for achieving the above object is a device for filtering digital signals by receiving at least two signals at the same time in a mobile communication system, a PN code and a short (PN code) of a short I channel and a short I channel A quadrature spreading code generator for receiving a PN code of a Q channel and generating a PN code of an I channel and a Q channel for spreading, a filtering block for processing a corresponding signal among the input signals, and filtering in the filtering block It is made up of an adder that adds and outputs the received signal.

The filtering blocks;

A first multiplier for multiplying corresponding data among the input data and an I-channel PN code of the quadrature spreading code generation unit, a second multiplier for multiplying the corresponding data with a Q channel PN code of the quadrature spreading code generation unit; A selector for alternately outputting the outputs of the first and second multipliers, a baseband filter for filtering the output of the selector, and a gain multiplier for multiplying the gain of the channel with data output from the baseband filter. Characterized in that configured.

A method of the present invention for achieving the above objects is a method of receiving at least two signals at the same time in the mobile communication system to filter the digital signal, the PN code and short Q of the long PN code and short I channel Receiving PN codes of channels and generating PN codes of I and Q channels for spreading; multiplying the input signals by PN codes of the I and Q channels according to data types; Outputting the data of the I and Q channels sequentially divided by the type and multiplying the signals; and filtering the signals sequentially divided according to the type to the baseband; Multiplying the corresponding channel gain value, and adding and outputting the data multiplied by the channel gain value;

If the channel gain of the input signals is changed, the process of dividing the channel gain into data and the channel gain unchanged data and outputting the channel gain in the baseband filtering; Multiplying the previous channel gain value, the data after the channel gain change is characterized by consisting of multiplying the channel gain value after the channel gain change to add the two multiplied values.

1 is a block diagram of a FIR filter for filtering multi-bit channel data according to the prior art;

2 is a block diagram of an FIR filter configured to provide various services to a wireless transmitter of an IMT-2000 system;

3 is a block diagram of an FIR filter serving as the equivalent model of FIG. 2 according to the present invention;

4 is a conceptual diagram of a filter structure for explaining the operation of the filter according to the present invention;

5 is a block diagram of a filter unit and a gain control unit according to an exemplary embodiment of the present invention;

6 is a block diagram for classifying data according to a change in channel gain of a filter unit according to the present invention;

7 is a timing diagram according to the block configuration of FIG. 6;

8 is a detailed circuit diagram illustrating a channel gain calculation block according to an embodiment of the present invention;

9 is a timing diagram according to the block configuration of FIG.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an FIR filter serving as the equivalent model of FIG. 2 according to the present invention. Hereinafter, a block configuration and operation according to the present invention will be described in detail with reference to FIG. 2.

First, the configuration will be described. Data of the pilot channel and data of the power control are input to the first multiplier 201 and the second multiplier 203 by a signal spread by a Walsh code. The data in which the dedicated control channel data is spread by the Walsh code is input to the third multiplier 205 and the fourth multiplier 207, and the data of the supplemental channel is the Walsh code. The data spread by is input to the fifth multiplication unit 209 and the sixth multiplication unit 211. In addition, data in which the data of the fundamental channel is spread by the Walsh code is input to the seventh multiplier 213 and the eighth multiplier 215.

On the other hand, the output of the I channel PN code generator 219 for generating the short PN code of the I channel, and the output of the Q channel PN code generator 221 for generating the short PN code of the Q channel, The quadrature spreading code generator 223 which receives the output of the long PN code generator 135 generating the long PN code receives the signals and converts the PN code of the I channel and the PN code of the Q channel. Generate and print. In this case, the PN code of the I-channel output from the quadrature spreading code generator 139 is input to the first multiplier 201, the third multiplier 205, the fifth multiplier 207, and the seventh multiplier 209. do. The PN code of the Q channel output from the quadrature spreading code generator 139 is input to the second multiplier 203, the fourth multiplier 207, the sixth multiplier 211, and the eighth multiplier 215. . Each of the multipliers 201, 203, 205, 207, 209, 211, 213, and 215 multiplies two input signals and outputs the multiplied signals. The signals output from the first multiplier 201 and the second multiplier 203 are input to the first selector 225, and the signals output from the third multiplier 205 and the fourth multiplier 207 are output to the second selector ( 227, the signals output from the fifth multiplier 209 and the sixth multiplier 211 are input to the third selector 229, and output from the seventh multiplier 213 and the eighth multiplier 215. The received signal is input to the fourth selector 231.

Therefore, the signal output from the first selector 225 is input to the first baseband filter 233 by the selection signal, and the signal output from the second selector 235 is input to the second baseband filter 235. do. The signal output from the third selector 229 is input to the third baseband filter 237, and the signal output from the fourth selector 231 is input to the fourth baseband filter 239.

Each baseband filter 233, 235, 237, and 239 filters and outputs an input signal. The signal output from the first baseband filter 233 and the second baseband filter 235 is input to the first adder 243, and the third baseband filter 245 and the fourth baseband filter ( The signal output from 247 is input to the second adder 251. The two adders 243 and 251 add the input signal to the third adder 253, and the third adder 253 adds the two input signals and outputs the transmitted data.

2 and 3 first prove that the equivalent model in the case where there is no variation in channel gain with reference to FIGS. 2 and 3. When the outputs of the first adder 109 and the second adder 111 of FIG. 2 are represented by Equations 2, Equation 2 may be illustrated.

Then, the PN codes are multiplied by the first multiplier 113 to the fourth multiplier 119 and output the data of the equation shown in Equation 2 above. The values multiplied and output as described above are also added by the third adder 121 and the fourth adder and output, so that the output values of the third adder 121 and the fourth adder 123 may be expressed by the following equation. It can be shown as Equation 3>.

Since data such as Equation 3 is input to the selector 125, the data filtered by the baseband filter 127 is shown as Equation 4 below.

In this way, the data is output, and the output of the filter is sequentially output from the data of the third adder 121 and the data of the fourth adder 123 by the selector 125. The output of TX_Q is filtered out sequentially.

In general, the FIR filter of FIG. 1 may be generalized as shown in Equation 5 below.

When the equation 5 is developed and solved, it is shown as Equation 6 below.

If all channel gains are the same as described above, that is, the values of G _pch [n], G _dch [n], G _sch [n], and G _fch [n] are constant, TX_I and TX_Q It is arranged as in Equation 7>.

The above equations are developed under the assumption that the gain of each channel is kept constant. Detailed description of the conversion of the channel gain other than this will be described with reference to FIGS. 4 to 9.

Then, when the configuration of the hardware block of FIG. 3 is represented by Equation 8, Equation 8 may be illustrated.

D [N] · PN_I [n] + j · D [n] · PN_Q [n] = D [n] · (PN_I [n] + jPN_Q) shown in Equation (8), and PN is diffused. Say that. In addition, as in the description of FIG. 2, the data output from the selectors 225, 227, 229, and 231 are also alternately output one by one. This should be applied to the above equation, and this multiplexing of I and Q data is performed after PN spreading. If the equation (8) is solved and shown, the equation (9) may be shown.

Equation (9) is divided into data of I and Q, and the transmission data shown in FIG. 3 can be shown as shown in Equation (10).

Equation 10 is an equation solved to prove that the model according to FIG. 3 is equivalent to FIG. 2. Therefore, the following Equation 10 is equivalent to FIG. 2, and is proved by the following Equations 11 and 12. Therefore, in Equation 11, the data of TX_I is solved and shown, and in Equation 12, the data of TX_Q is shown.

As shown in Equations 11 and 12, spreading is performed by PN_I and PN_Q and then filtered. Subsequently, the gain of each channel is multiplied. Subtraction is performed when the result of the multiplication is data of TX_I, and addition is performed when the result of the multiplication of the gain is data of TX_Q. The result is TX_DATA. 2 and 3 demonstrate that the equations are equivalent while the channel gain is kept constant.

In the block diagram of FIG. 3, the multipliers and the adders 249, 251, and 253 of the baseband filters 233, 235, 237, and 239 and the respective gain multipliers 241, 243, 245, and 247 are used. The structure becomes the structure of the filter. Therefore, if the structure of FIG. 3 is simply shown as Equation 13, it may be shown as Equation 13 below.

As shown in Equation 13, since FO_ [j] is a single bit input delay data D [j] is ± 1, FO_ [j] may add and subtract the filter coefficient Cj according to the data. That is, since the number of taps of the filter and the number of upsampling are predetermined, the possible values of FO [j] are also predetermined. These values can be tabulated into the memory using ROM, etc., and when adjacent delay data is input, the calculated filter values can be read using sample values as addresses. That is, the memory structure as described in FIG. 1 may be used. This will be described as a specific embodiment. Referring to the case where the number of taps is 48 and the upsampling ratio is 4, the number of ROM tables is changed according to Equation (14).

In Equation 14, k has values of 0, 1, 2, and 3. In this way, the system can be flexibly designed according to the number of taps, the number of upsampling, and the number of divisions in the memory table. However, in the case of configuring the memory table as described above, when the channel gain is changed, a section in which the data of which channel gain is changed and the data of which channel gain is not changed coexist and are calculated. This means that when data is input to each register of FIG. 1, data is sequentially moved to each register, resulting in a section in which channel gain is changed and a section in which the channel gain is not. However, when the above structure is simply adopted, such data coexistence section is lost. This is shown in Equation 15.

In Equation 15, k is 0, 1, 2,... , Has a value of S-1. As shown in Equation 15, when the channel gain is changed, a section in which data coexists disappears, and the channel gain is calculated as a value of the channel gain immediately changed from the moment when the channel gain is changed. This is a factor that causes a decrease in performance because a high data rate causes a few symbols of data continuously to cause a data error. Therefore, when using a memory structure, a method for compensating for this channel gain is required. In the following, a configuration for compensating for channel gain when using a memory structure will be described.

4 is a conceptual diagram of a filter structure for explaining the operation of the filter according to the present invention. In FIG. 3, data input from the first selector 225 is illustrated as the data of FIG. 4, and each input data is input to four shift registers 261, 263, 265, and 267. The nth input data is input to the first register of the first register part 261, and the n-11th input data is input to the last register of the fourth register part 267. Each register section divided into four parts stores three bits of data. That is, it consists of three registers. In addition, the registers 261, 263, 265, and 267 respectively store the data in advance so as to correspond to the filtered values in the ROM 1 (269), ROM 2 (271), ROM 3 (273), and ROM 4 (275). ). The ROM 1 269 and the ROM 2 271 provided as described above output data to the first adder 277. The ROM 3 273 and the ROM 4 275 output data to the second adder 279. At this time, the output data is added and input to the next third and fourth adders 283 and 285. In addition, the filter coefficient Cn and the data whose channel gain is changed are multiplied and input to the third and fourth adders 283 and 285. At this time, the data input to the third adder 283 of the output f_comf of the first multiplier 281 is input with a positive value, and the data input to the fourth adder 285 is negative. It is entered with a negative value. Therefore, the input data are further divided and output after being divided into a value after the gain is changed and a value before the gain is changed in the third and fourth adders. That is, the third adder 283 after the gain is changed is output as the value of F1, and the gain value before the gain is changed is output as the value of F2 at the fourth adder 285. Therefore, the second multiplier 287 located after the third adder 283 is multiplied by the gain value G _new after the gain is changed, and the third multiplier 289 next to the fourth adder 285 has the gain changed. The gain value G _now is multiplied before it is obtained. The multiplied data is input to the fifth adder 291, and the data is added and output. In addition, the data input to the first multiplier 281 moves together according to the start position of the data whose gain is changed. In addition, in FIG. 4, the start position of the data whose gain is changed is illustrated in the n-6th embodiment. However, when the n-5th position is located, only the data of the ROM 1 269 is output to the first adder. Data of the ROM 2 263, the ROM 3 265, and the ROM 4 267 is input to the second adder 279.

In FIG. 4, data after the gain is changed and before the gain is changed are divided, added to their values, and multiplied by the corresponding channel gains. For example, a case where the number of taps is 48, the upsampling is 4, and the number of ROM tables is 2 will be described as an example. The filter is 48 taps as described above, but multiplies the coefficients by zero inserting the data after 4 times oversampling, so the number of data multiplied over the actual 48 taps Becomes 12 contiguous data. Therefore, if the gain is changed at the time of j, the output until the gain is changed may be shown as Equation 16 below.

In Equation 16, the k value has a value of 0, 1, 2, and 3. In addition, if the output data for a period of 12 consecutive data after the gain is changed, it can be shown as shown in Equation 17 below.

In Equation 17, k = 0, 1, 2, and 3, and m = 1, 2,. , Has a value of 11. In addition, if the output data from the time after the 12 data input after the gain is changed by the equation can be shown as shown in the following equation (18).

Where k has the same value as in Equation 18. Therefore, as described above, in the 12 consecutive data intervals after the gain is changed, the data to be multiplied by G _now and the data to be multiplied by G _new coexist and must be classified and calculated to output accurate data. Can be. Then, the generalization of such a case will be described with reference to FIG. 5.

5 is a block diagram illustrating a filter unit and a gain control unit according to an exemplary embodiment of the present invention. Hereinafter, the configuration and operation of the filter unit and the gain control unit according to the present invention will be described in detail with reference to FIG. 5.

In the configuration of FIG. 3, data output from the selectors 225, 227, 229, and 231 becomes 1-bit data. Each 1-bit data output as described above is input to a division block 330 for distinguishing a gain conversion. In the division block 330, one bit of data is input to an input terminal of the shift register unit 331. The shift register unit 331 is bundled for several units and outputs data of the corresponding buffers, for example, D ₀ to D _(ms-1) , to the buffer 335. The input value k is outputted so that the same value is input to each buffer. Where k is 0, 1, 2,... , has a value of s-1. In addition, although only two buffers 333 and 335 are illustrated in FIG. 5 for convenience, the number of buffers is actually equal to the number of the register portions 331 as shown in FIG. 4. A value of k and a value output from the register unit 331 are stored together, and both values are output at the same time. In addition, one memory is provided to correspond to one buffer in a 1: 1 manner. That is, the memory corresponding to the buffer 335 is 337, and the buffer and the memory are sequentially configured to correspond. The memories are pre-stored according to the output from the respective buffers, and the data of the corresponding address is output to the adder 341 using the data output from the buffers as addresses.

The data output as described above is output to the channel gain calculation block 300 with the value of FO_now [j] when there is no gain change in the adder, and when the gain of the channel is changed, the output is divided into two. In detail, when the gain of the channel is changed, the data before the channel gain change is output as FO_now [j], and is input to the second adder 307 of the channel gain calculation block 300, and the data after the channel gain is changed is FO_new [ j] to the first adder 305 of the channel gain calculation block 300.

In addition, the register unit 310 storing the respective filter coefficients outputs data to the channel gain separation unit 303, and the counter 301 is provided in the register unit 331 of the division block 330. It consists of a counter that counts one less than the number of jitter. That is, in FIG. 5, the counter 301 becomes an IS-1 binary counter. When the channel gain is changed by the output from the counter 301, the channel gain separation unit 303 can distinguish the place where the first data whose channel gain is changed in the register unit 331 moves. Accordingly, the channel gain separator 303 accordingly outputs the data of the filter coefficient to the first adder 305 that adds the data whose channel gain is changed, and outputs the positive data, and the second adder 307. ) Is output as negative data. This is to distinguish previous data from subsequent data as described in FIG. 4. The data output from the first and second adders 305 and 307 are input to the first multiplier 309 and the second multiplier 320, and each multiplier multiplies the input data with a channel gain value. To the third adder. At this time, the channel gain value input to the first multiplier 309 is inputted Gnew, which is the changed channel gain, and the channel gain value input to the second multiplier 320 is inputted Gnow, which is the channel gain before the change. Data multiplied by each of the multipliers 309 and 320 as described above is added by the third adder 311 and output to the output of the filter.

The configuration and operation of the division block 300 among the components as shown in FIG. 5 will be described in more detail with reference to FIG. 6. 6 is a block diagram for classifying data according to a change in channel gain of a filter unit according to the present invention. Hereinafter, the configuration and operation of the filter unit according to the present invention will be described in detail with reference to FIG. 6.

The shift register 400 corresponds to the shift register portion 331 of FIG. 4, and is embodied in twelve registers 400a, 400b, 400c,..., 400l without generalizing as in FIG. 4. . Therefore, the shift register unit 400 receives one bit of data, and the farther from the input terminal of each register, the previously input data. And since the output of the register is composed of 12 registers will be described by dividing into two bundles. That is, the resistor unit 400 is divided into two to distinguish it from that described in the conceptual diagram of FIG. 4. Accordingly, the 6-bit signal output from the six registers 400a, 400b, ..., 400f close to the input terminal of the data is output to the buffer 410. The 6-bit signals output from the remaining six registers 400g, 400e, ..., 400l are input to another buffer 420. In addition, the two buffers 410 and 420 store k values together with the output of each register. In the embodiment configured as described above, the k value has a value of 0, 1, 2, and 3. Therefore, the k value is represented by 2 bits, and the values of the two bits are stored together in the buffer. The two buffers 41 and 420 store 6 bits of data output from the registers and k values received in 2 bits, and output 8 bits of data. The 8-bit data becomes an address and outputs data that is stored in a table in the memories 430 and 440 using the address. At this time, when the data stored in the memory 430 is shown in a table as shown in Table 1, the data stored in the other memory 440 may be shown in a table as shown in Table 2 below.

address value 0x000x010x020x030x040x05... 0xFC0xFD0xFE0xFF + C0 + C4 + C8 + C12 + C16 + C20 + C1 + C5 + C9 + C13 + C17 + C21 + C2 + C6 + C10 + C14 + C18 + C22 + C3 + C6 + C11 + C15 + C19 + C23 + C0 + C4 + C8 + C12 + C16-C20 + C1 + C5 + C9 + C13 + C17-C21. -C0-C4-C8-C12-C16-C20-C1-C5-C9-C13-C17-C21-C2-C6-C10-C14-C18-C22-C3-C6-C11-C15-C19-C23

address value 0x000x010x020x030x040x05... 0xFC0xFD0xFE0xFF + C24 + C28 + C32 + C36 + C40 + C44 + C25 + C29 + C33 + C37 + C41 + C45 + C26 + C30 + C34 + C38 + C42 + C46 + C27 + C31 + C35 + C39 + C43 + C47 + C24 + C28 + C32 + C36 + C40 + C44 + C25 + C29 + C33 + C37 + C41 + C45. -C24-C28-C32-C36-C40-C44-C25-C29-C33-C37-C41-C45-C26-C30-C34-C38-C42-C46-C27-C31-C35-C39-C43-C47

That is, as shown in Table 1 and Table 2, the filter coefficients are sequentially stored, and the calculated filter coefficient values are stored at the addresses shown on the left side of Tables 1 and 2. The calculated value is 8 bits of data, and the 8 bits of data are input to the first adder 450 and the second adder 460. The first adder 450 adds up to the data stored at the address of the ROM designated by the ROM selection signal, and the output of the added data is FO_new [j]. The second adder 460 adds the stored data from the end to the end of the ROM designated by the ROM selection signal. The output of the added data is FO_now [j]. 6, the output of the filter has only two outputs as shown in Equation 19 below.

In Equation 19, if m has a value of 1 to 5 dml, the data to be multiplied by G _new is in the result value read from the first memory. Therefore, referring to FIG. 5 again, the value of F_COMP is expressed as Equation 20 below.

In Equation 20, m has values of 1, 2, 3, 4, and 5. Therefore, if the data of F1 and F2 shown in FIG. 4 are represented by Equation 21, Equation 21 is obtained.

In Equation 21, the value of m has a value of 1-5. As can be seen from Equation 21, even when the channel gain is changed, the above-described problem can be solved by being divided into a section according to the previous channel gain and a section according to the changed channel gain.

The above operation will be described with reference to the timing diagram of FIG. FIG. 7 is a timing diagram according to the block configuration of FIG. 6. Hereinafter, the operation of the filter unit according to the present invention will be described in more detail with reference to FIGS. 6 and 7.

From the time point T _{1 to the} time point T ₈ , the selection signal of chip 2 (CHIP 2) is sequentially outputted with a low signal and a high signal, and the selection signal of chip 1 (CHIP 1) is the chip 2. It is outputted with a period that is twice the selection signal of, and at the same time when the low signal is output from the time point T _{1 to} the time point T ₃ , the k values are sequentially input from 0 to 3. And jth data is input. In this case, the data stored in each register of the register unit 400 is stored in the same order as the data stored at the time point T _{1 to the} time point T ₅ at the bottom of FIG. 7. It is assumed that only the j th data is 1, and the remaining data is 0. As described above, if data is stored and the next data is input as 0, the same as the data stored from the time point T _{5 to} the time point T ₈ in FIG. 7. That is, data is stored one by one. In this case, the address values of the memories 430 and 440 output from the buffers 410 and 420 according to the k value may be shown in Table 3 below.

output of k Buffer (410) Buffer (420) 0 10000000 00000000 One 10000001 00000001 2 10000010 00000010 3 10000011 00000011 0 01000000 00000000 One 01000001 00000001 2 01000010 00000010

That is, as shown in Table 3, the last two bits of the address change according to the change of k value, and the addresses of the memories 430 and 440 are sequentially selected one by one according to the input data.

8 is a detailed circuit diagram illustrating a channel gain calculation block according to an embodiment of the present invention. Hereinafter, the configuration and operation of the channel gain calculation block according to the present invention will be described in detail with reference to FIG. 8.

The filter coefficient storage unit 503 stores the filter coefficients, and outputs the stored filter coefficients to the channel gain compensator 505. The channel gain compensator 505 receives a count signal output from the hex counter 501. The decimal counter corresponds to the IS-1 binary counter of FIG. The channel gain compensator 505 receives a count signal, filter coefficients, and an address, and outputs data F_COMP according to channel gain compensation. At this time, the output data F_COMP is bifurcated and input to the first adder 507 with a positive sign. The other branched data is input to the second adder 513 with a negative sign. The first adder 507 is input with data of FO_new [j] output from the first adder 450 of FIG. 6 and the positive sign output from the channel gain compensator 505. The signal is added and output. The second adder 513 is input with the data of FO_now [j] output from the second adder 460 of FIG. 6 and the negative sign output from the channel gain compensator 505. The added signal is added and output.

Also, the hex counter 501 generates and outputs a ROM selection signal ROM_SEL, outputs an activation signal to the first channel gain unit 509 that outputs a new channel gain value G _new, and outputs a signal for updating. The second channel gain unit 515 outputs the previous channel gain value G _now . The data output from the first adder 507 and the data output from the channel gainer 509 are input to the first multiplier 511 to output a multiplied value. In addition, the second adder 513 has a negative signal at the data of the FO_now [j] output from the second adder 460 shown in FIG. 6 and the output of the channel gain compensator 505. The sum is output to the second multiplier 517. Then, the second multiplier 517 receives the output of the second adder 513 and the output of the second channel gain unit 515 and outputs a multiplied value. Here, the output of the first channel gain unit 509 is G _new of 8 bits, and the output of the second channel gain unit 515 is G _now of 8 bits. The output calculated by the second multiplier 517 and the output calculated by the first multiplier 511 by inputting such a value are input to the third adder 519 so that both signals are positive (+). Add to and output the value of. The data output at this time becomes the output of the filter.

Then, the operation according to the configuration of FIG. 8 will be described with reference to the timing diagram of FIG. 9. 9 is a timing diagram according to the block configuration of FIG. 8. Hereinafter, the operation of FIG. 8 will be described in detail with reference to the timing diagram of FIG. 9.

A case where the channel gain is changed at the position where the count value CNT is '1' will be described as an example. When the count value is '0', the channel gain value output from the first channel gain unit 509 becomes '0'. In addition, the channel gain value output from the second channel gain unit 515 is G _now . That is, when the channel gain is changed at the position where the count value CNT is 1, the channel gain value output from the first channel gain unit 509 has the value of G _new only from the position of '1' to the position of '11'. , The rest of the intervals have a value of 0. In addition, the value output from the second channel gain unit 515 has a G _now value from the previous interval of '0' to the interval of 11, and from the interval of '0' after the count ends. It has the value of G _new . Therefore, after that, G _new becomes G _now .

The value of F_COMP output from the channel gain compensator 505 has a value of 0 in a section where the count value is '0', and in a section of 1 to 6 and a section of 7 to 11, Equation 22 Has the same value as>

The ROM selection signal ROM_SEL has a value of 0 until the count value CNT is 6 and a value of 1 through 7 is 11. After that, it has a value of 0 again. Therefore, the value of FO_now in FIG. 6 reads and processes the data of the ROMs ROM # 1 and ROM # 2, which are memories from 0 to 6, wherein the value of FO_new is 0. Have When the value of the counter is 7 to 11, the value of FO_now is read from the ROM (ROM # 2) of the second memory 440 according to the value of F_COMP, and the value of FO_new is the first memory 430. Read the value of the ROM (ROM # 1). In order to easily express this, the block according to the channel gain before the change and the channel gain after the change when the count value is 2 and the count value is 11 is shown in the upper portion of FIG. 9. That is, even if the channel gain is changed through the above process, the filter output in the section where the two different channel gains coexist is output to have the same value as that of FIG.

As described above, in the system of the IMT-2000, one terminal can handle not only a voice channel but also a high-speed data channel, and at the same time, adopting a memory structure in configuring an FIR filter can reduce hardware load more. There is this. In addition, in the case of adopting such a memory structure, a circuit for compensating for the change of the channel gain is provided so that the output of the filter is the same even if the channel gain is changed.

Claims (8)

In the device for filtering digital signals in a mobile communication system, A quadrature spreading code generator for receiving a PN code of a long PN code and a short I channel and a PN code of a short Q channel to generate PN codes of I and Q channels for spreading; A first multiplier for multiplying the input data with the I-channel PN code of the quadrature spreading code generator; A second multiplier for multiplying the input data by the Q channel PN code of the quadrature spreading code generator; A selector for alternately outputting the outputs of the first and second multipliers; A baseband filter for filtering the output of the selector; And a gain multiplier for multiplying the gain of the data channel output from the baseband filter. The method of claim 1, wherein the baseband filter, Digital filter device in a mobile communication system, characterized in that the FIR (Finite Impulse Response) filter. In the apparatus for filtering digital signals by receiving at least two signals at the same time in a mobile communication system, A quadrature spreading code generator for receiving a PN code of a long PN code and a short I channel and a PN code of a short Q channel to generate PN codes of I and Q channels for spreading; A filtering block for processing a corresponding signal among the input signals; An adder configured to add and output the signal filtered by the filtering block; The filtering blocks; A first multiplier for multiplying corresponding data among the input data by the I-channel PN code of the quadrature spreading code generator; A second multiplier for multiplying the corresponding data by the Q channel PN code of the quadrature spreading code generator; A selector for alternately outputting the outputs of the first and second multipliers; A baseband filter for filtering the output of the selector; And a gain multiplier configured to multiply the gain of the corresponding channel by the data output from the baseband filter. The method of claim 3, wherein the baseband filter, Digital filter device in a mobile communication system, characterized in that the FIR (Finite Impulse Response) filter. The method according to claim 3 or 4, The baseband filter has a memory structure, When the channel gain of the input data is changed, the channel gain-changed data and the channel gain-unchanged data are classified and output to the gain multiplier. The gain multiplier is a digital filter device in a mobile communication system, characterized in that for multiplying the channel gain value corresponding to the data input separately. The method of claim 3, The baseband filter; Shift registers for sequentially moving and storing the input data, The data is output by dividing the registers into predetermined units, and data is calculated in advance according to values output from the registers of the predetermined unit, and the calculated values are previously determined based on the output of the registers. Memories that store the calculated values, A third adder for adding the data of the memory corresponding to the output of the registers to output the data of which the channel gain value is not changed to the output of the memories; A fourth adder configured to add data of a memory corresponding to an output of registers for outputting data whose channel gain value is changed to the output of the memories; The gain multiplier; A first multiplier for multiplying and outputting the channel gain value before the channel gain is changed to the output of the third adder; And a second multiplier for multiplying and outputting a channel gain value after the channel gain is changed to the output of the fourth adder. In the method for receiving at least two signals at the same time in the mobile communication system to filter the digital signal, Receiving a PN code of a long PN code and a short I channel and a PN code of a short Q channel to generate PN codes of I and Q channels for spreading; Multiplying the input signals by PN codes of the I and Q channels according to data types; Sequentially outputting the signals of the I and Q channels by multiplying and multiplying the signals according to the type; Filtering the signals sequentially divided according to the type and sequentially output to the baseband; Multiplying channel gain values corresponding to the filtered signals; And filtering the data obtained by multiplying the channel gain values. The method of claim 7, wherein When the channel gain of the input signals is changed, dividing the channel gain into data with the channel gain changed and data with the channel gain unchanged during the baseband filtering; And multiplying the channel gain value before the channel gain change by the data of which the channel gain is not changed, and adding the two multiplied values by multiplying the channel gain value after the channel gain change by the data after the channel gain change. Digital filtering method in a mobile communication system characterized by.