KR19990043484A - Simultaneous 4 Outputs 1: 4 Interpolation F Eye Filter in Single Structure - Google Patents

Abstract

In the design of a mobile communication modem, a modulation method such as Quadrature Phase Shift Keying (QPSK) is used for modulation of a digital signal, and at this time, pulse shaping is performed to suppress inter-symbol interference. Pulse shaping) requires interpolation filtering. Typically, two filters are required for single-channel modulation. In the case of a wireless local loop modem, four or more filters are required because the modulation of two or more channels is required within a single chip.

The present invention proposes a new VLSI filter design technique which simultaneously outputs four different filter output values by simultaneously processing four 1: 4 interpolation FIR filter operations in a single filter structure. The design method using the look-up table design and the pipeline technique uses a single filter structure, so that the design area can be reduced even if four filter operations are performed. In addition, the power consumption is not increased by being operated by the clock of the same speed as a general single filter that performs one filter operation in a single structure.

Description

Simultaneous 4 Outputs 1: 4 Interpolation F Eye Filter in Single Structure

The present invention relates to a 1: 4 interpolation finite impulse response (FIR) filter. In particular, a single filter structure simultaneously processes four simultaneous four-output 1: four interpolation FIR filter operations, and thus four different filter output values. A 1: 4 interpolation FIR filter for simultaneously outputting the same.

In general, when designing a wireless mobile modem, a modulation method such as Quadrature Phase Shift Keying (QPSK) is used for modulation of a digital signal, and at this time, inter-symbol interference is suppressed. Pulse shaping interpolation filtering is required.

In single-channel modulation, two filters are required for in-phase and quadrature-phase pulse shaping. For modems for wireless local loops, more than two channels of modulation must be handled within a single chip. More than one filter is required.

Therefore, when designing such a modulator, designing using a general filter design technique inevitably increases the design area or increases the frequency of the operation clock.

1 is a block diagram of a conventional transverse FIR filter.

As shown in FIG. 1, the conventional transverse FIR filter has an input signal (h44, h45, h46, h47), (h40, h41, h42, h43), ..., (h4, h5, h6, h7), respectively. , multiplexers (1-1), (1-2), ..., (1-11), (1-12) for selecting one signal from (h0, h1, h2, h3), and each of the above Multiplier (2-1) multiplies the output signal selected from the multiplexers (1-1), (1-2), ..., (1-11), (1-12) and the input signal (x (n)). , (2-2), ..., (2-11), (2-12) and a summer (3-1) for summing the output signal of the multiplier (2-1) and the input signal of zero level. And registers 4-1a, 4-2b, 4-2c, and 4-3d for storing the summation signal of the summer 3-1 for a predetermined time, and the register 4-1a. (4-2b), an adder (3-2) for summing the output signals of the multipliers (2-2) and the output signals of the (4-2b), (4-2c) and (4-3d), and four registers A summer 3-11 for summing the output signal of the multiplier 2-11 and the output signal of the summer 3-11 for a predetermined time. 4-11a, 4-12b, 4-13c, 4-14d, and 4-11a, 4-12b, 4-13c, 4-14d. Delay the output signal of the summer (3-12) and the output signal of the summer (3-12) for a predetermined time, and then add the delayed signal (y). and (n)) to output a register 4-13.

The operation of the conventional transversal FIR filter configured as described above is as follows.

First of all, the transversal FIR filter is the most basic and classical method of designing, and it is a hardware implementation of the filter calculation method as it is. As shown in FIG. 1, since the hardware has a single structure, only one filter operation needs to be performed, and the hardware has a large size. For example, when designing a pulse shaping FIR filter that performs 48 tap 1: 4 interpolation, where the number of bits in the input signal is 1 and the number of bits in the output signal is 8, typically 12 10-bit adders and 47 10-bit registers are required. .

2 is a block diagram of a FIR filter of a look-up table method.

As shown in FIG. 2, the FIR filter of the look-up table method includes 6-bit serial-parallel registers 10-1 and 10-2, and 6-bit I / Q selectors 11-1 and 11. -2), multiplexers 12-1, 12-2, ROMs 13-1, 13-2 for storing filter output values in a look-up table manner, and 11-bit adder 14 It consists of.

The operation of the conventional look-up table type FIR filter configured as described above is as follows.

First, the 1: 4 interpolation 48 tap FIR filter shown in FIG. 2 stores the filter output values in the ROMs 13-1 and 13-2 for all cases that may occur during the filter operation. A filter that reads an output value from memory using the value as a memory address.

Since there are 12 one-bit input data used for the filter operation, a 12-bit serial-to-parallel shift register is required.

The coefficient of the filter used for the first filter output is G0 = {C0, C4, C8, C12, C16, C20, C24, C28, C32, C36, C40, C44}, and the coefficient of the filter used for the second filter output is G1 = {C1, C5, C9, C13, C17, C21, C25, C29, C33, C37, C41, C45}.

The coefficient of the filter used for the third filter output is G2 = {C2, C6, C10, C14, C18, C22, C26, C30, C34, C38, C42, C46}, and the coefficient of the filter used for the fourth filter output is G3 = {C3, C7, C11, C15, C19, C23, C27, C31, C35, C39, C43, C47}.

That is, four coefficient groups G0, G1, G2, and G3 are used for the filter operation, and the number of output values that can occur in the filter operation for each group is 2 ¹² It is a dog. Therefore, the size of the look-up table is different for each group. 2 ¹² It should be x 8 bits, but for efficiency of design area, divide the look-up table by 2 and add one adder, as shown in Figure 2 2 ⁶ We can design a look-up table with a size of 8 bits.

Finally, the final look-up table size for a filter that performs four coefficient group operations is 4 × 2 × 2 ⁶ X 8 = 2 x 256 x 8 bits.

The twelve filter inputs are divided into two 6-bit serial-to-parallel conversion registers 10-1 and 10-2 and used as addresses of two look-up tables 13-1 and 13-2, respectively. . The two look-up 13-1 and 13-2 table outputs are added by the adder 14 to become the output of the filter. This process is performed sequentially for four groups of coefficients, thus performing a 1: 4 interpolation filter operation with four outputs for one input.

In the hardware implementation of such a single structured simultaneous four output 1: 4 interpolation FIR filter, the structure is simple, the design area can be reduced according to the usage of memory, and it is suitable for high-speed operation.

However, the conventional FIR filter has a problem in that the disadvantage of the conventional pulse shaping filter design method is that the hardware efficiency is lowered because only a single filter operation is performed in a single structure. In addition, the conventional look-up table FIR filter has a disadvantage in that the speed of the operation clock must be increased by N times in order to perform simultaneous N output interpolation filtering.

SUMMARY OF THE INVENTION An object of the present invention is to provide a 1: 4 interpolation FIR filter that simultaneously outputs four different filter output values by simultaneously processing four simultaneous four output 1: four interpolation FIR filter operations in a single filter structure. have.

Means for achieving the object of the present invention is a first to fourth input register for storing four filter inputs input in the period of the first clock, and the first to fourth in accordance with the first and second clock value An input divider for selecting one of four 12-bit input data stored in an input register, and first to fourth look-ups for performing a filter operation on the first to fourth coefficient groups of the input data selected by the input divider. Filter of each of the first to fourth look-up tables to sequentially output a table and filter outputs for each of four coefficient groups simultaneously generated in parallel in the first to fourth look-up tables in series. One of a first pipeline register outputting a delayed output by a predetermined clock and a filter output output from the first look-up table and the pipeline register by the first and second clock values; For selecting the output group arranged, delays the clock by a predetermined filter output which is output from the output aligner is configured to include a second pipeline register for outputting.

1 is a block diagram of a conventional transversal FIR filter.

2 is a block diagram of a conventional look-up table type FIR filter.

3 is a schematic diagram of a simultaneous four output 1: 4 interpolation FIR filter in a single structure according to an embodiment of the present invention.

4 is a detailed view of the look-up table in FIG.

* Explanation of symbols for main parts of the drawings

100-103: input register 104: input divider

105-108: Look-up table 200,202: Pipeline registers

201: output sorter

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a simultaneous 4-output 1: 4 interpolation FIR filter having a single structure according to an embodiment of the present invention.

As shown in FIG. 3, the 1: 4 interpolation FIR filter according to an embodiment of the present invention includes four filter inputs inputted at a period of the first clock CK1. f _i 0, f _i One, f _i 2, f _i 3) four 12-bit input data stored in the input registers 100-103 according to values of the input registers 100-103 storing the first and second clocks CK1, CK2. f _i 0, f _i One, f _i 2, f _i 3) a look-up table for performing a filter operation on the input divider 104, which is a 4x1 multiplexer for selecting one of the above, and each coefficient group GO-G3 of the input data selected by the input divider 104; 105-108 and the look-up table 106 to sequentially output filter outputs for each coefficient group G0-G3 simultaneously generated in parallel in the look-up table 105-108. A pipeline register 200 for delaying and outputting each filter output of -108), and the look-up table 105 and the table according to the first and second clocks CK1 and CK2. An output sorter 201 composed of 8-bit multiplexers 115-118 for selecting one of the filter outputs output from the pipeline register 200, and a filter output output from the output sorter 201 by a predetermined clock. Delay the output filter ( f _o 0, f _o One, f _o 2, f _o It consists of a pipeline register 202 to output to 3).

The pipeline register 200 is provided with a delay 109 for delaying the filter output of the look-up table 106 by one clock by a third clock CK4 and an input third clock CK4. Delays 110 and 111 for delaying the filter output of the look-up table 107 by one clock, and a filter of the look-up table 108 by an input third clock CK4. And delayers 112, 113, and 114 that delay the output by one clock.

As shown in FIG. 4, the look-up tables 105-108 each have four 2 ³ 8 bits memory 105-1, 105-2, 105-3, 105-4, and adder 105-5.

The operation of the 1: 4 interpolation FIR filter according to the embodiment of the present invention configured as described above will be described in detail as follows.

First, the design specification for the FIR filter is a 1: 4 interpolation 48-tap Finite Impulse Response (FIR) filter, with 1 bit on the input and 8 bit on the output. In the 1: 4 interpolation filter, four data are output each time one data is input. Thus, in the case of the 48 tap filter, the number of input data used for each filtering is 12.

Four inputs are input according to the input frequency CK1 shown in Fig. 5C, and the filter operation value is 4 according to the output frequency CK4 shown in Fig. 5A which is four times faster than the input frequency. 16 outputs are generated one by one, which is the basic operation of the filter proposed in the present invention. Therefore, to perform simultaneous four output 1: 4 interpolation filter operations, four filter operations must be performed for each output clock.

To do this, four filter operations are performed at the same time by dividing the lookup table into four, and the pipeline technique is introduced to match the timing of the output data.

The detailed filter operation is as follows.

The input registers 100-103 have four filter inputs inputted at a cycle of the clock CK1 shown in Fig. 5C. f _i 0, f _i One, f _i 2, f _i 3) is stored as four 12-bit serial-to-parallel conversion shift registers.

The input divider 104, which is a 12-bit 4 × 1 multiplexer, has four filter inputs ( f _i 0, f _i One, f _i 2, f _i When 3) is input in the clock CK1 period shown in FIG. 5C, the filter input stage is selected to sequentially perform four filter operations according to the clock CK2 shown in FIG. 5B. do. That is, four 12-bit input data according to the values of the clocks CK1 and CK2 ( f _i 0, f _i One, f _i 2, f _i 3) Select one.

In four separate look-up tables 105, 106, 107, and 108, a filter operation is performed for each coefficient group G0-G3. That is, the filter operation is performed on the coefficient group G0 in the look-up table 105, the filter operation is performed on the coefficient group G1 in the look-up table 106, and the coefficient group is performed on the look-up table 107. A filter operation is performed on G2 and a filter operation on coefficient group G3 is performed in look-up table 108.

Thus, all four interpolation filter operations for one input are processed at the same time.

Each group of look-up tables is divided into four groups as shown in FIG. 2 ³ 8 bits memory 105-1, 105-2, 105-3, 105-4, and adder 105-5. In other words, the 12-bit input register is divided into four 3-bit registers, the filter operation is performed by four look-up tables, and all four output values are added to obtain filter output values for each group.

The pipeline register 200 finally outputs the filter outputs for the four groups generated simultaneously in parallel in the look-up table in series sequentially. Therefore, each output must be delayed in the corresponding coefficient group order.

Register 109 delays the filter output of G1 by one clock, registers 110, 111 delay the clock output of G2 by two clocks, and registers 112, 113, and 114 filter the G2. Delay the output three clocks.

The output sorter 201 sorts the output of each filter distributed by the four look-up tables 105, 106, 107, and 108, finally by filter. . For this purpose, an output aligner 201, which is a 4 x 1 multiplexer 115, 116, 117, 118, is used.

The multiplexer 115 can filter f _i As the filter output sorter for 0), the filter output of G0 is selected when the values of clocks CK1 and CK2 are "0", and the filter output of G1 is selected when "1", and " In case of "10", the filter output of G2 is selected, and in case of "11", the filter output of G3 is selected.

In the same way, filter input ( f _i One, f _i 2, f _i The output of the filter for 3) is sorted by multiplexers 116, 117, and 118, respectively, with the value of the selector being cyclically shifted.

That is, the filter input ( f _i The multiplexer selector for 0) switches from "0" to "1" to "10" to "11" according to clock CK4, while the filter input ( f _i 1) is changed to "11" → "0" → "1" → "10" and the filter input ( f _i 2) is converted into "10" → "11" → "0" → "1" and filter input ( f _i 3) changes from "1" to "10" to "11" to "0".

The pipeline register 202 is for output time alignment.

The outputs of the multiplexers 115, 116, and 117 have a delay difference of one clock each. Filter input ( f _i Filter output for filter output (0) f _i It is output 3 clocks ahead of the filter output for 3). Therefore, since the time alignment must be completed in order to have four filter outputs performed simultaneously, delay pipeline registers 119-124 are used.

The present invention can simultaneously process four filter operations as a single filter structure while maintaining the existing operating clock speed. For example, when designing a 48-tap 1: 4 interpolation pulse shaping FIR filter with an input signal frequency of 1 MHz, the operating frequency required to perform only a single filter operation on the transversal filter is 4 MHz, and the look-up table method is used. When performing simultaneous two-output filter operation on FIR filter, the required operating frequency should be 8MHz. However, the design structure proposed in the present invention has the effect of performing simultaneous four output filter operation at an operating frequency of 4 MHz.

The structure proposed in the present invention has the advantage that four filter operations can be performed at the same time without further speeding up the operation clock by applying the high speed operation method, which is an advantage of the pipelined method and the look-up table method.

According to the present invention, in the first single filter structure, the simultaneous four output 1: 4 interpolation FIR filter operation of four single structures can be performed at the same time, and since the second single structure is used, the design area does not increase significantly even if four filter operations are performed. Third, the power consumption does not increase even if four filter operations are performed by using the same operation clock as that of a single operation filter having a single structure.

Claims (6)

First to fourth input registers for storing four filter inputs input in a period of the first clock; An input divider for selecting one of four 12-bit input data stored in the first to fourth input registers according to first and second clock values; First to fourth look-up tables for performing a filter operation on the first to fourth coefficient groups of the input data selected by the input divider; Each filter output of the first to fourth look-up tables is predetermined to sequentially output filter outputs for each of four coefficient groups simultaneously generated in parallel in the first to fourth look-up tables. A first pipeline register for delaying clock output; An output sorter for selecting one of the filter outputs output from the first look-up table and the pipeline register according to the first and second clock values; And a second pipeline register configured to delay the filter output output from the output sorter by a predetermined clock and output the delayed filter output. The method of claim 1, 1: 4 interpolation FIR filter, characterized in that the input divider is a 4 × 1 multiplexer. The method of claim 1, And the first to fourth look-up tables comprise an adder for adding signals stored in the first to fourth memories and the first to fourth memories. The method of claim 1, The first pipeline register includes: a first delay unit delaying a filter output of the second look-up table by one clock by a third clock input; Second and third delayers sequentially delaying the filter output of the second look-up table by one clock by an input third clock; And a fourth, fifth, and sixth delay units configured to delay the filter output of the fourth look-up table by one clock by an input third clock. The method of claim 1, And the output sorter comprises first to fourth multiplexers. The method according to claim 1 or 4, The second pipeline register may include first, second and third registers for delaying the output signal of the first multiplexer by one clock; Fourth and fifth registers for delaying the output signal of the second multiplexer by one clock; And a sixth register configured to delay the output signal of the three multiplexers by one clock.