JPH114140A - Oversampling digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an oversampling digital filter by a small number of parts. SOLUTION: Input data in is synchronized with a clock clk and inputted to a shift register 10. The output signal S10-i of a flip-flop 10-i is transmitted from the shift register to a tap coefficient sum selecting circuit 20-i. The tap coefficient sum selecting circuit 20-1(i; 0-15) executes selection from a tap coefficient sum which is previously calculated with 64 tap coefficients as a source based on the values of S10-i and S10-(i+1) and the timings of timing signals Ti which are successively different in phase by one-forth of a cycle with pulse width being one-forth of the one cycle of the clock clk and transmits it to an adding circuit 30 as the output signal S20-i. The output signal S20-i is added by the clock of a frequency being four times as large as that of the clock clk.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code division multiple access (hereinafter, referred to as CD).
This is used in a digital modulation device or the like for mobile communication according to the MA system, and is provided in a stage preceding a D / A converter for converting a digital baseband signal into a digital / analog (hereinafter referred to as D / A) and transmitting the converted signal. It relates to a sample digital filter.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Reference 1: Data compression and digital modulation, (1993.10.1),
Nikkei BP, Jurg Hinderling et al., "Spread Spectrum Technology", P.253-264 Reference 2: Digital Mobile Communication System, (1993-2), Tokyo Denki University Press, Yuki Yamauchi, "Basic Digital Modulation / Demodulation Method" ”, P.24-31 CDMA Used in Digital Modulation Equipment for Mobile Communications
As described in the above-mentioned document 1, the method is to sequentially perform audio signal encoding, convolutional encoding, interleaving, scrambling, and spread spectrum modulation, and then perform n times the frequency of a clock synchronized with input data. In this method, a band component other than 1.25 MHz is cut using an oversampling digital filter that oversamples with a clock, and D / A conversion and high-frequency modulation are performed for transmission. This CD
According to the MA system, the same band can be shared by a plurality of communication channels, and the number of users that can be accommodated in mobile communication can be increased. Reference 2
The side lobes occur because the modulated baseband signal is too broad, as described in US Pat. For this reason, high frequency components are removed by using an oversampled digital filter to suppress side lobes. Since a filter for this purpose is required not to output a signal to an adjacent band, a digital filter having a steep cutoff characteristic is required. In particular, in the CDMA system, FIR (Finite Impulse Response) having linear phase characteristics
Filters are often used.

FIG. 2 is a block diagram showing an example of a conventional oversampled digital filter. This oversampled digital filter has an interpolation circuit 1 that outputs the input data x (n) during one cycle of the clock clk1 when the input data x (n) is input. A shift register 2 is connected to the output side of the interpolation circuit 1.
The shift register 2 has a clock cl of an oversampling frequency (for example, four times the frequency of the clock clk1).
Shift input data x (n) in synchronization with k2 6
Four flip-flops (hereinafter referred to as FFs) 2-i
(I; 0 to 63), and the FF2-i (i; 0 to 6)
The FF2- (i + 1) is connected to the output side of 2). Also, on each output side of FF2-i (i; 0 to 63),
The tap coefficient Ki (i; 0 to 63) is stored.
i based on the value of the output signal S2-i of the tap coefficient Ki
Is connected to a coefficient buffer group 3 having a coefficient buffer 3-i (i; 0 to 63) for outputting any one of positive, negative, and zero. On the output side of the coefficient buffer group 3,
A 64-input adder circuit 4 is connected. The adder circuit 4 has a 2-input adder (hereinafter referred to as ADD) 4-0-
0-4-0-31,4-1-0-0-4-1-15,4-2
-0 to 4-2-7, 4-3-0 to 4-3-3, 4-4-
0, 4-4-1 and 4-5-0 are connected in multiple stages, and the ADD4-5-0 outputs output data out. Next, the operation of the oversampled digital filter of FIG. 2 will be described. The interpolation circuit 1
The input data x (n) is sent to the shift register 2 during one cycle of the clock clk1. The shift register 2 shifts the input data x (n) in synchronization with the clock clk2 of the oversampling frequency,
From i (i; 0 to 63), the output signal S2-i is sent to the coefficient buffer 3-i. The coefficient buffer 3-i sends tap coefficients Ki, 0, and -Ki to the adder circuit 4 in accordance with the values of the output signal S2-i of 1, 0, and -1.
In the adder circuit 4, 6 output from the coefficient buffer 3-i is output.
The four tap coefficients are added in synchronization with a clock having the same frequency as the clock c1k2, and output data out is output.

[0004]

However, the conventional oversampled digital filter shown in FIG. 2 has the following problems. When a digital filter is used to implement a filter having a steep cutoff characteristic for performing band limiting, an enormous number of filter taps is required. For this reason, when manufacturing hardware, an adder circuit having the same number of input terminals as the number of tap coefficients of the filter is required, and there has been a problem that the circuit scale becomes enormous. For example, in the oversampled digital filter of FIG.
, And the number of input terminals of the adder circuit 4 is 64.
Then, the adder circuit 4 adds ADD4-0-0 to 4-0-3.
1 (32), 4-1-0 to 4-1-15 (16),
4-2-0 to 4-2-7 (8 pieces), 4-3-0 to 4-3
-4 (4), 4-4-0, 4-4-1 (2), 4-
It is composed of a total of 63 2-input ADDs of 5-0 (one).

[0005]

In order to solve the above-mentioned problems, the present invention relates to a method for converting digital input data sampled at a predetermined sampling frequency into a signal having a frequency of n times (n; a natural number of 2 or more) the sampling frequency. An oversampled digital filter that performs filtering at a sampling frequency includes the following means. It is composed of m (m: natural number) cascaded FFs, shifts the input data in synchronization with a first clock having the same frequency as the sampling frequency, and outputs an output signal from each FF in parallel. Shift register, and (m−
1) A group of tap coefficient sums obtained by calculating based on n tap coefficients sequentially selected n by n from the youngest of the x n tap coefficients is held in advance, and a cycle of 1 / n of the cycle of the clock is held. And selecting and outputting the corresponding tap coefficient sums from the tap coefficient sum group based on the value of the timing signal that changes in step (1) and the logical levels of two consecutive output signals of the output signals of the FFs. (m-1) tap coefficient sum selection circuits, and the (m-1) tap coefficient sum values output from each tap coefficient sum selection circuit as a second clock having the same frequency as the oversampling frequency. And an addition circuit for performing addition in synchronization.

According to the present invention, since the oversampled digital filter is configured as described above, input data is sequentially input to the shift register in synchronization with the first clock. The cascaded m FFs shift one bit at a time at the timing of the first clock, and transmit each output signal to the (m-1) tap coefficient sum selection circuits. Each tap coefficient sum selection circuit selects a corresponding tap coefficient sum from a tap coefficient sum group based on the value of the timing signal and each logical level of two consecutive output signals of the output signals of the FFs. To the adder circuit. The adder circuit synchronizes these (m-1) signals in synchronization with the second clock.
The sum of the tap coefficients is added and output. Therefore, the above problem can be solved.

[0007]

FIG. 1 is a block diagram of an oversampled digital filter according to an embodiment of the present invention. This oversampling digital filter uses the clock cl
It has a shift register 10 which receives digital input data in input in synchronization with k and shifts the input data in bit by bit with the clock clk. The shift register 10 has 17 FFs 10-i.
(I; 0 to 16), and the FF10-i (i; 0 to 1)
The data input terminal D of the FF 10- (i + 1) is connected to the output terminal Q of 5). FF10-i (i; 0 to 0)
The clock clk is input to the clock input terminal cp of 16). FF10-i (i; 0 to 0)
15) and an output terminal Q of the FF 10- (i + 1) are connected to a tap coefficient sum selection circuit (hereinafter referred to as SEL) 20-i (i; 0 to 15) in the tap coefficient sum selection circuit group 20. I have. Further, for example, a 4-bit timing signal Ti (i; 0 to 3) is input to the SEL 20-i. This timing signal Ti
It has a pulse width of 1/4 of one cycle of the clock clk, and each bit has a different phase by a quarter cycle. Furthermore,
SEL20-i (i; 0 to 15) has a tap coefficient sum K
_{A i, KB i, KC i} , memory (not shown) for storing the KD _i are connected. SEL20-i (i; 0 to 1)
5) is the value of the timing signal Ti (i; 0 to 3) and the FF
Tap coefficient sums ± KA _i , ± KB _i , ± K based on the logic levels of output signals S10-i, S10- (i + 1) of FF 10- (i + 1) and FF 10- (i + 1).
This circuit selects and outputs the corresponding tap coefficient sums from C _i and ± KD _i .

A 16-input adder circuit 30 is connected to the output side of the SEL 20-i. The adder circuit 30 includes two input ADDs 30-0-0 to 30-0-7 (eight), 30
-1-0 to 30-1-3 (4 pieces), 30-2-0, 30
-2-1 (two) and 30-3-0 (one) are connected in multiple stages, and operate with a clock having a frequency four times the frequency of the clock clk to output output data out.
FIG. 3 is a diagram illustrating a tap coefficient sum group stored in the memory. This tap coefficient sum group is based on 64 tap coefficients K _i (i; 0 to 63) of the conventional digital filter shown in FIG. 2 and is calculated in advance using the following equation (1). KA ₀ , KB ₀ , KC ₀ , KD ₀ , KA ₁ , K
B ₁ , KC ₁ , KD ₁ ,..., KA ₁₅ , KB ₁₅ , KC ₁₅ ,
KD is _15. KA _i = K _{(4i + 3)} + K _{(4i + 2)} + K _{(4i + 1)} + K _{(4i + 0)} KB _i = K _{(4i + 3)} + K _{(4i + 2)} + K _{(4i + 1)} −K _{(4i + 0)} KC _i = K _{(4i + 3)} + K _{(4i + 2)} -K _{(4i + 1)} -K _{(4i + 0)} KD _i = K _{(4i + 3)} -K _{(4i + 2)} -K _{(4i + 1)} -K _{(4i + 0)} where i; 1 to 15 (1) FIG. 4 shows the timing signal Ti and the output signal S1 in FIG.
Output signals S20-i of SEL20-i (i; 0 to 15) corresponding to the respective logic levels 0-i and S10- (i + 1)
FIG.

FIG. 5 is a time chart of the signals at various parts in FIG. 1, in which the vertical axis represents the logic level and the horizontal axis represents time. However, the input data in and the output signal S20-i
Is displaying data. The operation of FIG. 1 will be described with reference to FIG. 5 and FIGS. In FF10-0,
At the timing of the rising edge of clock clk, input data i
n (n), in (n + 1), in (n + 2),... are sequentially input. The FF 10-0 performs a 1-bit shift operation at the rising edge of the clock clk, and outputs the output signal S10-0 to the FF 10-1 and the tap coefficient sum selection circuit 2
Send to 0-0. FF10-i (i; 1 to 15)
A one-bit shift operation is performed at the rising timing of the clock clk, and each output signal S10-i (i; 1 to 15) is set to S.
EL20- (i-1) (i; 1 to 15) and SEL20
-I (i; 1 to 15). FF10-16 is
A one-bit shift operation is performed at the rising edge of the clock clk, and the output signal S10-16 is sent to the SEL 20-15. As shown in FIG. 4, when the timing signal T is "1000", the SEL 20-i (i; 0 to 15)
If the output signal S10- (i + 1) of F10- (i + 1) is "0" and the output signal S10-i of FF10-i is "0", the tap coefficient sum KAi shown in FIG. 3 is selected. When the timing signal T is "1000", the output signal S10- (i + 1) is "0" and the output signal S10-
If i is "1", SEL20-i (i; 0 to 15)
Selects the tap coefficient sum KBi. Timing signal T
Is "1000", if the output signal S10- (i + 1) is "1" and the output signal S10-i is "0", S
EL20-i (i; 0 to 15) is a tap coefficient sum KBi
Choose a negative value for. Timing signal T is "1000"
At this time, if the output signal S10- (i + 1) is "1" and the output signal S10-i is "1", the SEL 20-i
(I; 0 to 15) selects a negative value of the tap coefficient sum KAi. That is, SEL20-i (i; 0 to 15)
The tap coefficient sum in FIG. 4 is selected according to the value of the timing signal T, and the respective logic levels of the output signal S10- (i + 1) and the output signal S10-i, and sent to the addition circuit 30 as the output signal S20-i. However, in FIG. 5, this tap coefficient sum is represented by m + 0, m + 1, m + 2, m + 3,. The addition circuit 30 adds the output signal S20-i output from the SEL 20-i in synchronization with a clock having an oversampling frequency four times the frequency of the clock clk,
The output data out is output to a D / A converter (not shown).

Next, it will be described that the transfer characteristic of the oversampled digital filter of the present embodiment is equal to the transfer characteristic of the conventional oversampled digital filter of FIG. Assuming that the input data in is input in the order of x (16), x (15),..., X (1), x (0), FF2-i (i;
63), the following patterns (i) to (iv) are sequentially output at the rising edge of the clock clk2. (i) x (0), x (1), x (1), x (1), x (1), x (2), x (2), x (2), ..., x (15), x (16), x (16), x (16) (ii) x (0), x (0), x (1), x (1), x (1), x (1), x (2 ), x (2),…, x (15), x (15), x (16), x (16) (iii) x (0), x (0), x (O), x (1) , x (1), x (1), x (1), x (2),…, x (15), x (15), x (15), x (16) (iv) x (0), x (0), x (0), x (0), x (1), x (1), x (1), x (1), ..., x (15), x (15), x (15 ), x (15) As shown in these patterns (i) to (iv),
x (0), x (1),..., x (15), x (16) for each FF2-i (i;
0-63) is uniquely determined and sent to the coefficient buffer 3-i (i; 0-63). The corresponding tap coefficients are output from the coefficient buffer 3-i and added by the adding circuit 4. Addition circuit 4
Thereafter, the following patterns (I) to (IV) are sequentially output as output data out at the rising edge of the clock clk2.

[0011]

(Equation 1) On the other hand, SEL20-i (i; 0 to 15) in FIG. 1 is x (0), x of each output pattern of the above patterns (I) to (IV).
(1),..., X (16) are output and two consecutive FFs in FIG.
10- (i + 1) and the output signal S10- of the FF 10-i
A tap coefficient sum corresponding to (i + 1) and S10-i is selected and output at each timing of the timing signal Ti, and is transmitted to the addition circuit 30. The adding circuit 30 outputs the sum of the tap coefficients output from the SEL 20-i (that is, the output signal S20-i).
i) is added. Therefore, the output data o of the adder circuit 30
ut becomes the same as the output data out of the adding circuit 4 in FIG. 2, and the transfer characteristic of the oversampled digital filter of the present embodiment becomes the same as the transfer characteristic of the conventional oversampled digital filter of FIG.

As described above, this embodiment has the following advantages (1) to (3). (1) 17 FFs 10-i operating the oversampled digital filter at the timing of the clock clk having the same frequency as the sampling frequency of the input data in
And two consecutive FF10- (i + 1) and FF10-
The timing of the timing signal Ti having a pulse width of ４ of one cycle of the clock clk and having a different phase by a quarter cycle, depending on the values of the output signals S10- (i + 1) and S10-i of i SEL 20-i that selects and outputs the tap coefficient sum and the adder circuit 30 that operates with a clock having a frequency four times the frequency of the clock clk. For example, when the number of taps is 64, the conventional FIG. While the adder circuit 4 in the middle has 63 adders, the adder circuit 30 in FIG. 1 of the present embodiment can be composed of 63 adders, not more than one half and 31 or less. Therefore, an oversampled digital filter with a reduced circuit scale can be realized. (2) The number of FFs 10-i is FF2-
The number of i is reduced to 1/4 + 1, and the circuit size of the oversampled digital filter can be reduced. (3) The conventional interpolation circuit 1 in FIG. 2 becomes unnecessary, and the circuit scale of the oversampled digital filter can be reduced.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, the following modifications (a) to (c) are available. (A) In the embodiment, input data in with 64 taps
A digital filter having an oversampling frequency four times the frequency of the clock clk described above has been described, but the tap number and the oversampling frequency may be any values. (B) In the embodiment, the one-bit input data in has been described. However, the present invention can be applied even when the input data in has two or more bits. In this case, the shift register 10 has the same bit configuration as the number of bits of the input data in, and the tap coefficient sum selection circuit group 20
It is configured to select the tap coefficient sum according to the value of the output signal of F. (C) In the embodiment, the timing signal Ti has a pulse width obtained by dividing the frequency of the clock clk by four, and is constituted by a 4-bit signal having a different phase by a quarter period.
A signal having a pulse width obtained by dividing the clock clk by 4 and representing four phases, for example, a 2-bit signal “00”,
It may be composed of “01”, “10” and “11”.

[0014]

As described above in detail, according to the present invention, the oversampled digital filter is provided with m FFs operating at the timing of the clock having the same frequency as the sampling frequency of the input data, and the m FFs. Based on the logic level of each output signal of two consecutive FFs among the FFs and the value of the timing signal that changes at a period of 1 / n of the clock period, (m−1) × n tap coefficients are set in advance. Select and output the tap coefficient sum obtained from (m-1) S
EL and (m-1) output from (m-1) SELs.
1) Since an adder circuit for adding the values of the sum of tap coefficients in synchronization with a clock having the same frequency as the oversampling frequency is provided, an oversampled digital filter with a small number of components can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an oversampled digital filter according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional oversampled digital filter.

FIG. 3 is a diagram showing a tap coefficient sum group;

FIG. 4 is a diagram showing output signals of a SEL 20-i in FIG.

FIG. 5 is a time chart of FIG. 1;

[Explanation of symbols]

10 shift register 10-i (i; 0~16) FF ( flip-flop) 20-i (i; 0~15 ) SEL ( tap coefficient sum selection circuit) 30 adder circuit _{KA i, KB i, KC i} , KD i (I; 0 to 15) Sum of tap coefficients

Claims (1)

[Claims] An oversampled digital filter for filtering digital input data sampled at a predetermined sampling frequency at an oversampling frequency n times (n; a natural number of 2 or more) the sampling frequency, wherein m (m; A shift register that shifts the input data in synchronization with a first clock having the same frequency as the sampling frequency, and outputs output signals from the flip-flops in parallel. And a tap coefficient sum group calculated and calculated in advance based on n tap coefficients selected n by n from the (m-1) × n tap coefficients in ascending order. Of the value of the timing signal changing at a period of 1 / n and the output signal of each flip-flop. (M-1) tap coefficient sum selection circuits for selecting and outputting the corresponding tap coefficient sums from the tap coefficient sum group based on the respective logic levels of the two output signals to be executed, (M-1) output from the selection circuit
An adder circuit for adding a sum of tap coefficients in synchronization with a second clock having the same frequency as the oversampling frequency.