JPH07336402A - Modulation signal generating device - Google Patents

Abstract

PURPOSE:To provide a modulation signal generating device which can generate a QPSK signal, etc., without using a digital filter of a large circuit scale and a digital adder nor requiring any element of particularly high a precision. CONSTITUTION:A modulation signal generating device contains a data holding circuit 12 which divides the I and Q signals constructing a QPSK code into plural digital signals to hold these signals and outputs them in parallel to each other, a waveform shaping circuit 16 which has a ROM 17 to store the oversampling codes corresponding to the digital signals that can be outputted from the circuit 12 and reads the oversampling codes corresponding to those output digital signals out or the ROM 17 and outputs them as the waveform shaping signals, a modulator 18 which modulates the waveform shaping signals received from the circuit 16, an adder 22 which adds together the modulation signals received from the modulator 18, and a filter 23 which deletes the undesired components out of the addition signals received from the adder 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation signal generator used in a transmitter, and more particularly to a modulation signal generator for generating a modulation signal such as a QPSK signal.

[0002]

2. Description of the Related Art A conventional modulation signal generator, for example, QPS
The K signal generator is configured as shown in FIG. The input time series digital signal is first mapped by the mapping circuit 901.
Is converted into an I signal and a Q signal forming a QPSK code (reference: Radio Wave System Development Center, RCR-STD-27). These I signal and Q
The signal is waveform-shaped by the roll-off filters 902a and 902b in order to prevent intersymbol interference due to band limitation of the transmission path, and then converted into an analog signal by the D / A converters 903a and 903b, and a harmonic signal component is further converted. It is input to the multipliers 905a and 905b forming the quadrature modulator via the low-pass filters 904a and 904b for attenuation. In the multipliers 905 a and 905 b, the first carrier signal from the oscillator 906 and the second carrier signal obtained by passing it through the π / 2 phase shifter 907 are used as a low-pass filter 904.
Modulation is performed by multiplying the signals from a and 904b.

Roll-off filters 902a and 902b
Are generally realized by FIR type or IIR type digital filters. These digital filters are composed of a digital adder, a digital multiplier, a digital delay element, etc., and their circuit scale is generally large.

Incidentally, the QPSK signal is, for example, a combination of 0 phase, π / 2 phase, π phase and 3π / 2 phase as shown in FIG. 20, or π / 4 phase, 3π / 4 phase, 5π / 4 phase. ，
Since the sign is a combination of 7π / 4 phases, the types of input signals (I signal and Q signal) of the roll-off filters 902a and 902b are only four at most. Therefore, in order to simplify the digital roll-off filter having a large circuit scale, the configuration shown in FIG. 21 has been conventionally considered. FIG. 21 shows a roll-off filter 902a for the I signal.
Only showing. As shown in the figure, a plurality of ROMs 1
, 1103 stores the impulse response of the roll-off filter 902a for each input signal, and the impulse response for each input signal is stored in the ROM 110.
1, 1102, ..., 1103, read from the adder 11
The function of the roll-off filter 902a is realized by sequentially outputting through the 20.

Since the impulse response of the roll-off filter is an infinite response, it is necessary to store the impulse response of infinite length in the ROM. However, in reality, this is impossible, and therefore the influence on the output signal is affected. The impulse response length is cut off to the extent that it becomes sufficiently small. Even in this case, the impulse responses to the respective input signals overlap in time. That is, considering the case where A, B, C, and D are sequentially input as input signals, the impulse response to the signal A does not end in the time zone in which the signal A is input, and some subsequent signals, For example, the process continues until the signal D is input. Therefore, in order to store the impulse response, as shown in FIG. 21, a plurality of ROMs 1101, 1102, ... Corresponding to a plurality of input signals input during the duration of the impulse response to one input signal.
1103 is required, and accordingly, the ROMs 1101, 1
A digital adder 1120 for adding the outputs of 102, ..., 1103 is required.

Further, in order to improve the signal accuracy of the output modulation signal, the D / A converter 903 in FIG. 19 is used.
a, 903b and modulator (multipliers 905a, 905
It is necessary to improve the accuracy of b), and for this purpose, high accuracy is required for the circuit elements forming the D / A converter and the modulator.

[0007]

As described above, the conventional QPSK signal generator requires a digital filter having a large circuit scale as a waveform shaping circuit for preventing intersymbol interference, and the digital filter is a ROM. Even when simplified, the problem is that a digital adder with a large circuit scale is required, and high precision is required for the elements constituting the D / A converter and the modulator in order to improve the signal precision. There was a problem that

It is an object of the present invention to use a QPSK without using a digital filter or a digital adder having a large circuit scale and without requiring an element with high precision.
It is an object of the present invention to provide a modulation signal generator that can generate a modulation signal such as a signal.

[0009]

In order to solve the above problems, a modulation signal generator according to the present invention divides a time-series digital signal into a plurality of digital signals and holds them, and these plurality of digital signals are connected in parallel. Holding means for outputting,
The storage means has a storage means for storing a plurality of oversampling codes respectively corresponding to a plurality of digital signals that can be output from the storage means, and the storage means stores the oversampling codes corresponding to the plurality of digital signals output from the storage means. Waveform shaping means for reading from the waveform shaping signal and outputting it as a waveform shaping signal, modulating means for modulating a plurality of waveform shaping signals from this waveform shaping means, adding means for adding a plurality of modulated signals from this modulating means, and this addition Filter means for removing unnecessary components from the addition signal from the means.

Further, in the above basic structure, the present invention is provided with weighting means for weighting a plurality of modulation signals from the modulation means with a predetermined weighting coefficient, and the plurality of modulation signals weighted by the weighting means. Is input to the adding means for addition, and the added signal is input to the filter means for removing unnecessary components to obtain a modulated signal.

Further, the present invention is characterized in that, in the above basic structure, ΔΣ modulation data is used as an oversampling code. Further, the present invention, in the above basic configuration, uses ΔΣ modulation data as an oversampling code, and provides weighting means for weighting a plurality of modulated signals from the modulation means with a predetermined weighting coefficient, and weighting is performed by this weighting means. The plurality of modulated signals which have been subjected to the above are input to the adding means to be added, and the added signals are input to the filter means for removing unnecessary components to obtain the modulated signals.

Further, the modulated signal generator according to the present invention divides the time-series digital signal into a plurality of digital signals and holds them, and a holding means for outputting the plurality of digital signals in parallel, and an output from the holding means. Having a plurality of oversampling codes respectively corresponding to a combination of a plurality of digital signals that can be
Waveform shaping means for reading out an oversampling code corresponding to a combination of a plurality of digital signals output from the holding means from the storage means and outputting it as a waveform shaping signal, and a modulation for modulating the waveform shaping signal from the waveform shaping means. Means and filter means for removing unnecessary components from the modulated signal from the modulating means.

[0013]

In the modulated signal generator of the present invention, a time-series digital signal (for example, an I signal and a Q signal forming a QPSK code) is divided into a plurality of digital signals, which are held and output in parallel. After the signal is waveform-shaped as an oversampling code to prevent intersymbol interference, the waveform-shaped signal is modulated and added, and unnecessary components are removed from the added signal to obtain a final modulated signal (eg, QPSK signal). To occur.

The oversampling code is, for example, Yukawa.
As described in Akira "Oversampling AD Conversion Technology" (published by Nikkei BP), oversampling and noise shaping reduce quantization noise within a band, and 1 bit (binary level) to 3 It is a code that can express an in-band signal with high accuracy even in bits, and has pulse density information. Therefore, if the waveform shaping signal is expressed in the form of an oversampling code, an analog adder can be used as an adding circuit when modulating a plurality of waveform shaping signals and adding the obtained plurality of modulated signals. A large-scale digital adder becomes unnecessary. As a result,
The QPSK signal generator can be configured with a circuit scale smaller than the conventional one. Further, if the addition of the modulation signals is performed by current addition, the adding circuit can be realized only by wiring and no special hardware is required, so that the circuit scale is further reduced.

When the waveform shaping signal is expressed by an oversampling code, the input of the modulation circuit is a signal of about 1 bit to 3 bits, so that the modulation circuit can be composed of only switches, and the nonlinearity of the circuit element. The effect of is greatly reduced.

Further, if the waveform shaping signal is expressed by an oversampling code (ΔΣ modulation) obtained by a ΔΣ modulator, the quantization noise is reduced by varying the output amplitude according to the generated waveform, which is unnecessary. Out-of-band noise can also be reduced.

[0017]

【Example】

(Embodiment 1) FIG. 1 shows the configuration of a transmitter including a QPSK signal generator according to this embodiment. In FIG. 1, a time series digital signal is input to the input terminal 10. This time-series digital signal first has n bits (for example, 3 bits) that form a QPSK code by the mapping circuit 11.
Is converted into I and Q signals. These I signal and Q signal are input to an I channel signal generator and a Q channel signal generator having the same configuration, respectively. The I channel signal generator and the Q channel signal generator are configured as follows.

First, the I signal and the Q signal output from the mapping circuit 11 are respectively held in the data holding circuit 12.
a and 12b. Data holding circuits 12a, 12
b is composed of a plurality (m) of switches 13 and m memories 14 each of which is an n-bit latch connected to the switch 13. The switch 13 is sequentially turned on by the reference clock signal from the reference clock signal generator 15, and sequentially supplies the I signal or the Q signal to the memory 14 by n bits. The memory 14 simultaneously outputs the held n-bit data. That is, the data holding circuits 12a and 12b output m input signals (n × m bits) in parallel, each of which is an input time-series signal I signal and Q signal.

The m digital signals output from the data holding circuits 12a and 12b are waveform shaping circuits 16a and 1b.
6b, respectively. Waveform shaping circuits 16a, 16
Each b is composed of m ROMs 17, and the ROM 17 stores the impulse response of the digital roll-off filter for the digital signals that can be output from the data holding circuits 12a and 12b as oversampling codes. Then, the waveform shaping circuits 16a, 16
b outputs an oversampling code representing an impulse response corresponding to the digital signal input from the data holding circuits 12a and 12b as a waveform shaping signal.

As described in the section of the prior art, the impulse responses of the roll-off filter for the m digital signals output from the data holding circuits 12a and 12b overlap in time. That is, for example, in the impulse response to a digital signal which is an I signal or a Q signal, m digital signals are data holding circuits 12a, 1
It continues until it is input to 2b. Therefore, in this embodiment, in order to obtain the impulse response of the roll-off filter for the m digital signals, the data holding circuit 12a that holds the continuous m digital signals and outputs them in parallel,
12b is provided, and data holding circuits 12a and 12b are provided.
M ROMs storing impulse responses corresponding to m digital signals from the memory as oversampling codes
17 is provided in the waveform shaping circuits 16a and 16b.

The waveform shaping signals output from the waveform shaping circuits 16a and 16b are input to the modulation circuits 18a and 18b, respectively. Each of the modulation circuits 18a and 18b is composed of m multipliers (mixers) 19. Modulation circuit 1
8a performs modulation by multiplying the waveform shaping signal from the waveform shaping circuit 16a by the first carrier wave signal from the oscillator 20, and the modulation circuit 18b controls the waveform shaping signal from the waveform shaping circuit 16b and the first carrier signal from the oscillator 20. The carrier wave signal of 1 is passed through the π / 2 phase shifter 21, and the second carrier wave signal obtained is multiplied to perform modulation. Therefore, the modulation circuit 18
A and 18b form a quadrature modulator as a whole. The waveform of the carrier signal is preferably a rectangular wave.

The m modulation signals output from the modulation circuit 18a are added by the addition circuit 22a to obtain the modulation circuit 18a.
Similarly for the m modulation signals output from b, the addition circuit 2
2b is added. The added signals output from the adder circuits 22a and 22b are input to filters (generally bandpass filters) 23a and 23b, respectively, so that high frequency components that are out-of-band unwanted components generated in the modulator circuits 18a and 18b are generated. To be removed. Filters 22a, 2
The output signal of 2b is combined by the adder 24 to obtain the final Q
It becomes a PSK signal.

In this way, the mapping circuit 11, the data holding circuits 12a and 12b, the waveform shaping circuits 16a and 16b,
The modulation circuits 18a and 18b, the adder circuits 22a and 22b, the filters 23a and 23b, and the adder 24 make QPSK.
A signal generator is configured. QPS generated in this way
The K signal is amplified by the power amplifier 25 and transmitted by the antenna 26.

In the conventional QPSK signal generator, when adding a finite impulse response to a plurality of digital signals, since the signals are added in the preceding stage of the A / D converter, a digital adder is required. The scale was big. On the other hand, according to the present embodiment, since the waveform shaping signal is represented by the oversampling code, it is possible to configure the adder circuits 22a and 22b by analog adders, which is far more circuit than the digital adder. It is possible to reduce the scale. Therefore,
It is possible to reduce the size of the QPSK signal generator.

Furthermore, in the conventional QPSK signal generator, since the input signal of the modulation circuit is an analog signal, the modulation circuit needs to have excellent analog characteristics. On the other hand, in the present embodiment, by using the 1-bit code as the oversampling code of the waveform shaping signals output from the waveform shaping circuits 16a and 16b, the modulation circuits 18a and 18b are obtained.
Is a 1-bit code. Therefore, if a rectangular wave is used for the carrier wave signal, the modulation circuit can be configured mainly with a switch such as a MOS transistor.
The influence of the element accuracy of the analog circuit on the modulation accuracy of the PSK signal can be reduced.

If the modulation signals output from the modulation circuits 18a and 18b are represented by voltage signals, the adder circuit 22
Although a and 22b are voltage adders, if the modulation signal is expressed by a current signal, the addition circuits 22a and 22b are modulation signals only by connecting their input lines (output lines of the modulation circuits 18a and 18b). It is possible to add current signals. In this case, since the adder circuits 22a and 22b are realized only by simple wiring and no special hardware circuit such as a voltage adder is required, the configuration of the QPSK signal generator can be further simplified.

Next, another embodiment of the present invention will be described. In the following embodiments, the same or corresponding parts as those in FIG. 1 are designated by the same reference numerals, and different points will be mainly described. (Embodiment 2) FIG. 2 shows the configuration of a transmitter including a QPSK signal generator according to this embodiment. In this embodiment, FIG.
The adder circuits 22a and 22b in FIG.
Are integrated into. As a result, the filters 23a and 23b in FIG. 1 can be combined into one filter 23. Also in this case, the addition circuit 22 can be realized by current addition by connecting the modulation signals output from the modulation circuits 18a and 18b to current signals.

(Embodiment 3) FIG. 3 shows a QP according to this embodiment.
The structure of an SK signal generator is shown. Although only the I channel signal generator is shown in FIG. 3, the same applies to the Q channel signal generator. In the present embodiment, as shown in FIG. 3A, between the modulation circuit 18a and the addition circuit 22a, or as shown in FIG. 3B, the waveform shaping circuit 16a and the modulation circuit 1 are provided.
The D / A converter 24 is inserted between 8a and 8a. In the configuration of this embodiment, the waveform shaping signal output from the waveform shaping circuit 16a is 1 as in typical oversampling code.
It is effective not only when expressed by a bit code, but also when expressed by a relatively small number of plural bits such as a 2-bit or 3-bit code. The embodiment shown in FIG. 1 corresponds to the case where the waveform shaping signal is a 1-bit code and a 1-bit D / A converter is used as the D / A converter 24. In that case, the D / A converter in the usual sense can be omitted, and therefore is omitted in FIG.

FIGS. 4 and 5 are specific examples of the 1-bit D / A converter 24 when the waveform shaping signal is a 1-bit code. The D / A converter shown in FIG. 4 includes an inverter 41 and a resistance element 42. The D / A converter shown in FIG.
It is composed of a differential amplifier circuit 50. Differential amplifier circuit 50
Of the differential pair transistors 51 and 52 connected to the sources (or emitters) in common, and the current source 53 connected to the common source (or the common emitter). Alternatively, differential signals are given as inputs 1 and 2 to the base), and outputs are taken out in the form of differential signals from the drain (or collector).

(Embodiment 4) FIG. 6 shows a modification of the data holding circuits 12a and 12b shown in FIG. This data holding circuit is composed of (m-1) n-bit memories 61-1.
˜61-4 are connected in cascade. The n-bit data forming the I signal or the Q signal held in each memory is output to the waveform shaping circuits 16a and 16b, and at the same time, transferred to the subsequent memory in response to the reference clock signal.

Considering the case where the signals A, B, C, D consisting of n-bit data are sequentially input as the I signal or the Q signal, the signal A is first output from the output terminal 62-0, and the next reference clock signal is output. The signal A is output from the output terminal 62-1 of the memory 61-1 and the signal B is output from the output terminal 62-0 of the memory 61-1. In the next reference clock signal, the signal A is output from the output terminal 62-2 of the memory 61-2, the signal B is output from the output terminal 62-1 of the memory 61-1, and the signal C is output from the output terminal 62-0. . Further, in the next reference clock signal, the signal A is output from the output terminal 62-3 of the memory 61-3, and the signal B is output from the output terminal 62 of the memory 61-2.
-2, the signal C is output from the output terminal 61-2 of the memory 61-1.
, The signal D is output from the output terminal 62-0.

As described above, according to the data holding circuit of FIG. 6, the same signal is sequentially output from the different output terminals 62-0 to 62-4, and as a result, the time series signal I is input.
The signal or the Q signal is output in parallel every m (n × m bits). Therefore, when the data holding circuit in FIG. 6 is used, the waveform shaping circuits 16a and 16b in FIG.
The configuration can be simplified.

That is, in the case of the data holding circuits 12a and 12b shown in FIG. 1, the signals A, B, C, D, ... Are stored in m ROMs 17 forming the waveform shaping circuits 16a and 16b.
It is necessary to store the oversampling code corresponding to the impulse response of the digital roll-off filter for all of. On the other hand, in the case of the data holding circuits 12a and 12b having the configuration of FIG. 6, since the same input signal is repeatedly output from different output terminals, the waveform shaping circuit 16a,
In the m number of ROMs 17 constituting 16b, among impulse responses of the digital roll-off filter with respect to the same input signal, a part of impulse responses obtained by windowing different m / 1 intervals for a certain time is exceeded. It is sufficient to store the sampled data respectively.
Therefore, according to the configuration of the data holding circuit of FIG. 6, the capacity of the ROM 17 forming the waveform shaping circuits 16a and 16b is set to 1
/ M.

(Embodiment 5) FIG. 7 shows a QP according to this embodiment.
The structure of the main part of an SK signal generator is shown. In this embodiment,
The input time-series digital signal is converted into an I signal and a Q signal forming a QPSK signal by the mapping circuit 11 shown in FIG. 1, and then input to the address generation circuit 71 for each I and Q channel. The address generation circuit 71 generates address signals corresponding to various combinations of input I signals or Q signals and supplies them to the ROM 72. ROM7
2 stores the data of the impulse response of the digital roll-off filter for the I signal or the Q signal,
In accordance with the address signal from the address generation circuit 71, impulse response data corresponding to the I signal or the Q signal is read. The impulse response data read from the ROM 73 is converted into an analog signal by the D / A converter 73, and then input to the multiplier 74 that constitutes the modulation circuit.
It is multiplied by a carrier signal and modulated. The modulated signal output from the multiplier 74 becomes a QPSK signal by removing unnecessary components outside the band by the filter 23a or 23b as in FIG.

The address generation circuit 31 includes a shift register 81 including a plurality of delay elements (memory) DL connected in cascade as shown in FIG. 8 and an address conversion circuit (counter).
The shift register 81 is provided with the I signal or the Q signal and is input to the delay element at the first stage of the shift register 81. The address conversion circuit 82 outputs an address signal corresponding to the combination of the signals accumulated in each delay element DL.

The QPSK signal is represented as the sum (superposition) of the digital roll-off filter impulse responses for various combinations of I or Q signals. In this embodiment, the ROM 72 stores the sum of the impulse responses corresponding to each combination of the I signal and the Q signal, and the content of the ROM 72 is read according to the address signal from the address generation circuit 71. This allows
The functions of the data holding circuit 12a or 12b and the waveform shaping circuit 16a or 16b in FIG. 1 can be realized by one ROM 72, and the configuration is further simplified.

Also in this embodiment, the impulse response of the digital roll-off filter stored in the ROM 72 is set to 1-bit data such as a typical oversampling code so that the D / A converter 73 is set to 1-bit D / A. It can be a converter.

(Embodiment 6) FIG. 9 shows a QP according to this embodiment.
The structure of the main part of an SK signal generator is shown. The input time-series digital signal is converted into an I signal and a Q signal forming a QPSK signal by the mapping circuit 11 shown in FIG. 1, and then input to the address generating circuit 91 for each of the I and Q channels. The address generating circuit 91 sequentially and selectively generates a plurality of address signals according to the input I signal series or Q signal series and supplies them to the ROM 92. ROM9
In 2, data of impulse response of the digital roll-off filter corresponding to various I signals or Q signals is stored.

The impulse response data read from the ROM 92 in accordance with the address signal from the address generating circuit 91 is held in a plurality of memories (for example, latches) 94 constituting the data holding circuit 93. Data holding circuit 9
From 3, data stored in the memory addressed by the address generation circuit 91 is read out, input to a plurality of multipliers 95 forming a modulation circuit, and multiplied by a carrier signal to be modulated. The plurality of modulated signals output from the multiplier 95 are converted into analog signals by the D / A converter 96, and then added by the adder circuit 22a or 22 as in FIG.
By adding at b, the impulse response is superimposed on the modulated signal, and the unnecessary component outside the band is removed by the filter 23a or 23b.
It becomes the SK signal.

According to this embodiment, the impulse response of the digital roll-off filter corresponding to various I signals or Q signals is stored in one ROM 92, and the address is generated corresponding to the input I signal sequence or Q signal sequence. Circuit 19
Since the address of the ROM 92 is switched in order to sequentially read the data of the impulse response to the input I-signal series or Q-signal series, the storage capacity of the ROM 92 is different from that of the waveform shaping circuits 16a and 16b in the embodiment of FIG. The storage capacity may be the same as the storage capacity of one of the ROMs 17. Therefore, it is possible to effectively utilize the ROM capacity as compared with the embodiment of FIG. 1 in which one ROM 17 corresponds to one impulse response data.

In this case, the memory 9 of the data holding circuit 93
A plurality of impulse response data corresponding to the input I signal series or Q signal series are individually stored in 4, and read in parallel by the clock signal. Also,
A ROM table corresponding to a plurality of impulse responses can be obtained and stored, and the impulse response data can be selectively output according to the address designation.

In this embodiment, the data holding circuit 93 is arranged to hold the impulse response data stored in the ROM 92, but the input I signal series or Q is used.
It may be arranged so as to retain the signal sequence, and D / A
It can also be arranged so as to hold the converted analog data.

(Embodiment 7) FIG. 10 shows a Q according to this embodiment.
The structure of the principal part of a PSK signal generator is shown. The input time-series digital signal is the mapping circuit 11 shown in FIG.
Is converted into an I signal and a Q signal that form a QPSK signal by, and then input to the I signal processing circuit and the Q signal processing circuit.

In the I signal processing circuit or the Q signal processing circuit, the input I signal or Q signal is sequentially delayed by the plurality of delay elements 101 connected in cascade. Further, the input I signal or Q signal and the output of each delay element 101 are respectively input to a plurality of ROMs 102 as address signals. The ROM 102 stores the impulse response of the digital roll-off filter for various I or Q signals.

The impulse response of the digital roll-off filter with respect to the I and Q signal sequences has portions overlapping with each other as shown in FIG. Therefore, in this embodiment, the impulse response waveform is divided into a plurality of parts, and the ROM 1
02 separately. That is, the input I signal or Q signal is divided into a plurality of parts via the delay element 101, and these are respectively input to the ROM 102 as address signals, whereby each part of the impulse response is individually read from the ROM 102.

The signals read from these ROMs 102 are each modulated by a plurality of multipliers 103 forming a modulation circuit, and further weighted by a predetermined weighting coefficient in a weighting circuit 104. Weighting circuit 10
The plurality of weighted modulation signals from 4 are converted into analog signals by the D / A converter 105, and then added by the adder circuit 22a or 22b in the same manner as in FIG. 1, and the unnecessary component is further filtered by the filter 23a or 23b. By being removed, it becomes a QPSK signal.

In this embodiment, the weighting coefficient αi (i = 1, 2, ..., N) of the weighting circuit 104 is variably set according to the amplitude of the impulse response waveform shown in FIG. That is, αi is set to be small in a portion where the amplitude of the impulse response waveform is small, and conversely, αi is set to be large in a portion where the amplitude is large. Then, the impulse response data stored in the ROM 102 is multiplied by 1 / αi corresponding to this weighting. By doing so, the influence of quantization noise can be reduced. That is, the impulse response of the input roll-off filter is a signal having a small amplitude at both ends of the data and a large amplitude at the center, as shown in FIG. In ΔΣ modulation, this signal is represented by only two values. Therefore, the difference between this binary value and the impulse response signal of the roll-off filter becomes quantization noise. Therefore,
Quantization noise can be reduced by changing the magnitude of the above two values according to the signal and bringing them closer to the signal amplitude.

(Embodiment 8) FIG. 12 shows a Q according to this embodiment.
The structure of the principal part of a PSK signal generator is shown. Explaining only the differences from the seventh embodiment shown in FIG. 10, in the present embodiment, the ROM 102 stores the impulse response of the digital roll-off filter for various I signals or Q signals by ΔΣ.
It is stored as a 1-bit or several-bit signal modulated by an oversampling modulator represented by a modulator.

That is, the impulse response waveform Sa shown in FIG. 14 is divided into a plurality of pieces, and each divided waveform Sd is converted into ΔΣ modulation data and stored in the ROM 102. The ROM 102 has values of the I axis or the Q axis on the IQ plane shown in FIG. 15, that is, 1, ^{1/2 1/2} , 0, -1/2.
5 storage areas corresponding to ^1/2 and -1, respectively,
By addressing these storage areas with the I signal or the Q signal, the ΔΣ modulated data corresponding to the I signal or the Q signal is read.

By storing the above-mentioned signal in the ROM 102, the circuit scale of the D / A converter 106 for converting the modulation signal from the multiplier 103 into an analog signal is significantly reduced, and in particular, one bit is included in the ΔΣ modulation data. When the code is used, a 1-bit D / A converter can be used and its effect is great. That is, by using the 1-bit code, the output code length of the D / A converter 106 becomes 1 bit, and not only the circuit scale is reduced but also the D / A converter 106 can be configured only by the switch element. In principle, the requirement for accuracy disappears. Therefore, the QPSK signal generator can be easily configured on the LSI. Further, since the oversampling code is used, the requirement for filter performance is relaxed.

Further, also in the present embodiment, the weighting coefficient αi of the weighting circuit 104 is changed according to the impulse response waveform in the same manner as in the seventh embodiment, and αi is small in the small amplitude portion of the impulse response waveform, and conversely the large amplitude. In part α
By setting i to be large and correspondingly multiplying the impulse response data to be stored in the ROM 102 by 1 / αi, the influence of quantization noise can be reduced.

FIG. 16 shows how the output waveform changes in amplitude corresponding to one impulse response at this time. The vertical axis represents amplitude and the horizontal axis represents time. As shown in the figure, the amplitude change of the output waveform shows a step-like envelope. As is clear from this figure, the ΔΣ modulation signal can significantly reduce the quantization noise. The reason for this is as described above with reference to FIG.

Therefore, the characteristics required of the filters 23a and 23b for removing the unnecessary components need not be particularly steep filter characteristics. (Embodiment 9) FIG. 13 shows the configuration of the main part of a QPSK signal generator according to this embodiment. In this embodiment, 1 bit D
The current output type D / A converter as shown in FIG. 4 or FIG. 5 is used as the A / A converter 106.
Adder circuits 22a and 22b are configured by adding the current output of 06 by connection. Therefore, the circuit scale of the adder circuit can be further reduced. The D / A converter 1
A similar effect can be obtained by using a voltage output type D / A converter as 06 and converting its output into a voltage-current and adding them by connection.

When the D / A converter 106 has a current output, the filters 23a and 23b connected to the outputs of the adding circuits 22a and 22b may be current type, or the filters 23a and 23b may be voltage type. Adder circuit 22a,
The output of 22b is converted into current-voltage, and then the filter 23
You may input into a and 23b.

(Embodiment 10) Q described in the above embodiments
In the PSK signal generator, it is possible to reduce the in-band quantization noise by noise shaping, but on the other hand, since the out-of-band noise increases,
Problems with other signals may be a problem. FIG. 1 shows an embodiment for reducing the influence on other signals in such a case.
2, and FIG. 17 and FIG. 18 will be described below.

In this embodiment, an oversampling modulator having a noise shaping characteristic for suppressing the noise level in a certain specific frequency band is used, and is stored in the ROM described in the above embodiments. By generating the impulse response data, the unnecessary noise level at a specific frequency is suppressed, and the requirement to the filters 23a and 23b for removing the unnecessary component outside the band is relaxed.

FIG. 17 shows a configuration example of the ΔΣ modulator, which is an adder 192 connected to the X input terminal 191.
And a plurality of delay circuits connected in series, that is, Z ⁻¹
Circuits 193 _{I to} 193 _N and a plurality of α coefficient circuits 194 _I
˜194 _N and a plurality of β coefficient circuits 195 _{I to} 195 _N
, Adder 196, comparator 197, and delay circuit 198
Composed of and. Such a delta-sigma modulator is configured to have a noise shaping characteristic that suppresses noise at a frequency at which it is difficult to impair other signals.

The transfer function from the input x to the output y in FIG. 17 is represented by y = a (z) x + b (z) Q. Here, Q is the quantization noise generated in the quantizer. At this time, the frequency b
By setting α and β so that (z) has a zero point, the above noise shaping characteristic can be provided. For example, in the case of a fourth-order ΔΣ modulator, in order to set the two zero points to fs / m, α and β are set so that
Should be set.

[0059]

[Equation 1]

FIG. 18 shows the noise shaping characteristic when the zero point is placed at 600 kHz. As can be seen from the figure, noise is reduced in the vicinity of the frequency of 600 kHz which is affected by the obstacle. Conventionally, it was necessary to sufficiently suppress this noise by a filter (corresponding to 23a and 23b) provided in the QPSK signal generator, but according to the present embodiment, the characteristics of the filters 23a and 23b can be relaxed. , QPSK signal generator can be contributed to miniaturization.

Although the above embodiment describes the QPSK signal generator, the present invention is not limited to this, and can be applied to a device for generating a PSK signal such as a two-phase or eight-phase signal and other modulated signals. The modulation signal format is not particularly limited.

[0062]

As described above, according to the present invention, a digital adder having a large circuit scale, which has been required in the past, is unnecessary, and the circuit scale can be reduced. In addition, the modulation circuit can be configured by only the switch, and the requirement for the element accuracy of the circuit element is greatly relaxed. As a result, the requirement for the element accuracy of the circuit element is greatly relaxed, the VLSI or the like can be easily realized, the yield can be improved, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a modulation signal generator according to a first embodiment.

FIG. 2 is a block diagram of a modulation signal generation device according to a second embodiment.

FIG. 3 is a block diagram of a modulation signal generation device according to a third embodiment.

FIG. 4 is a circuit diagram showing an example of a current output type D / A converter.

FIG. 5 is a circuit diagram showing another example of a current output type D / A converter.

FIG. 6 is a circuit diagram of a main part of a modulation signal generation device according to a fourth embodiment.

FIG. 7 is a block diagram of a main part of a modulation signal generation device according to a fifth embodiment.

8 is a circuit diagram showing a configuration of an address generation circuit in FIG.

FIG. 9 is a block diagram of a main part of a modulation signal generation device according to a sixth embodiment.

FIG. 10 is a block diagram of a main part of a modulation signal generation device according to a seventh embodiment.

FIG. 11 is a diagram showing an impulse response waveform.

FIG. 12 is a block diagram of essential parts of a modulated signal generator according to an eighth embodiment.

FIG. 13 is a block diagram of a main part of a modulation signal generation device according to a ninth embodiment.

FIG. 14 is a diagram showing an impulse response waveform and a ΔΣ modulation signal waveform.

FIG. 15 is a diagram showing an IQ plane.

FIG. 16 is a diagram showing an impulse response waveform.

FIG. 17 is a block diagram of a ΔΣ modulator for explaining a modulation signal generation device according to a tenth embodiment.

FIG. 18 is a diagram showing noise shaping characteristics.

FIG. 19 is a block diagram of a conventional QPSK signal generator.

FIG. 20 is a diagram showing an IQ plane.

FIG. 21 is a diagram showing a configuration of a digital roll-off filter in a conventional QPSK signal generator.

[Explanation of symbols]

10 ... Input terminal 11 ... Mapping circuit 12a, 12b ... Data holding circuit 13 ... Switch 14 ... Memory 15 ... Reference clock generator 16a, 16b ... Waveform shaping circuit 17 ... ROM 18a, 18b ... Modulation circuit 19 ... Multiplier 20 ... Local part Oscillator 21 ... π / 2 phase shifter 22a, 22b, 22 ... Adder circuit 23a, 23b,
23 ... Filter 24 ... Adder 25 ... Power amplifier 26 ... Antenna 61 ... Memory 71 ... Address generation circuit 72 ... ROM 73 ... D / A converter 74 ... Multiplier 81 ... Shift register 82 ... Address conversion circuit 91 ... Address generation circuit 92 ... ROM 93 ... Data holding circuit 94 ... Memory 95 ... Multiplier 96 ... D / A converter 101 ... Delay element 102 ... ROM 103 ... Multiplier 104 ... Weighting circuit 105 ... D / A converter 106 ... 1 bit D / A converter

Claims (5)

[Claims] 1. A holding means for dividing a time series digital signal into a plurality of digital signals and holding the plurality of digital signals and outputting the plurality of digital signals in parallel, and a plurality of digital signals which can be output from the holding means, respectively. Waveform shaping means having a storage means for storing a plurality of oversampling codes and reading out the oversampling codes corresponding to the plurality of digital signals output from the holding means from the storage means and outputting as a waveform shaping signal; Modulating means for modulating the plurality of waveform shaping signals from the waveform shaping means, adding means for adding the plurality of modulated signals from the modulating means, and filter means for removing unnecessary components from the added signal from the adding means. A modulated signal generating device, comprising: 2. A holding means for dividing a time-series digital signal into a plurality of digital signals and holding the plurality of digital signals, and outputting the plurality of digital signals in parallel, and a plurality of digital signals that can be output from the holding means. Waveform shaping means having a storage means for storing a plurality of oversampling codes and reading out the oversampling codes corresponding to the plurality of digital signals output from the holding means from the storage means and outputting as a waveform shaping signal; Modulation means for modulating the plurality of waveform shaping signals from the waveform shaping means, weighting means for weighting the plurality of modulated signals from the modulation means with a predetermined weighting coefficient, and weighting by the weighting means Addition means for adding a plurality of modulated signals and an unnecessary component is removed from the addition signal from this addition means. Modulation signal generating apparatus characterized by comprising a filter means. 3. A holding means for dividing a time-series digital signal into a plurality of digital signals and holding the plurality of digital signals, and outputting the plurality of digital signals in parallel, and a plurality of digital signals which can be output from the holding means, respectively. Waveform shaping means having a storage means for storing a plurality of ΔΣ modulation data, and reading the ΔΣ modulation data corresponding to the plurality of digital signals output from the holding means from the storage means and outputting it as a waveform shaping signal; Modulating means for modulating the plurality of waveform shaping signals from the waveform shaping means, adding means for adding the plurality of modulated signals from the modulating means, and filter means for removing unnecessary components from the added signal from the adding means. A modulated signal generating device, comprising: 4. Holding means for dividing a time-series digital signal into a plurality of digital signals and holding the plurality of digital signals and outputting the plurality of digital signals in parallel, and a plurality of digital signals that can be output from the holding means, respectively. Waveform shaping means having a storage means for storing a plurality of ΔΣ modulation data, and reading the ΔΣ modulation data corresponding to the plurality of digital signals output from the holding means from the storage means and outputting it as a waveform shaping signal; Modulation means for modulating the plurality of waveform shaping signals from the waveform shaping means, weighting means for weighting the plurality of modulated signals from the modulation means with a predetermined weighting coefficient, and weighting by the weighting means An addition means for adding a plurality of modulation signals and a filter means for removing an unnecessary component from the addition signal from the addition means are provided. A modulation signal generator characterized by being provided. 5. A holding means for dividing a time-series digital signal into a plurality of digital signals and holding the plurality of digital signals and outputting the plurality of digital signals in parallel, and a plurality of digital signals that can be output from the holding means, respectively. Waveform shaping having storage means for storing a plurality of corresponding oversampling codes, and reading out oversampling codes corresponding to a combination of a plurality of digital signals output from the holding means from the storage means and outputting as waveform shaping signals A modulated signal generating device comprising: a means, a modulating means for modulating the waveform shaped signal from the waveform shaping means, and a filter means for removing an unnecessary component from the modulated signal from the modulating means.